`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria1 Virginia 22313- 1450
`www.uspto.gov
`
`APPLICATION NO.
`
`
`
`
`
` F ING DATE
`
`FIRST NAMED INVENTOR
`
`ATTORNEY DOCKET NO.
`
`
`
`
`CONF {MATION NO.
`
`12/289,669
`
`10/31/2008
`
`Hajime Akimoto
`
`HARU—0015
`
`1287
`
`7590
`“”0”“
`9999c99199 AMq —
`c/o Stites & Harbison PLLC
`SITTA, GRANT
`1199 North Fairfax Street
`9 999
`Alexandria, VA 223 14- 1437
`
`NM
`
`2694
`
`
`
`
`NOT *ICATION DATE
`
`DELIVERY MODE
`
`04/10/2013
`
`ELECTRONIC
`
`Please find below and/0r attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above—indicated "Notification Date" to the
`following e—mail address(es):
`
`iplaw @ stites.com
`
`PTOL—90A (Rev. 04/07)
`
`

`

`
`
`Applicant(s)
`Application No.
` 12/289,669 AKIMOTO ET AL.
`
`Examiner
`Art Unit
`AIA (First Inventor to File)
`Office Action Summary
`
`GRANT SITTA its“ 2694
`
`-- The MAILING DA TE of this communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`
`
`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE 3 MONTH(S) OR THIRTY (30) DAYS,
`WHICHEVER IS LONGER, FROM THE MAILING DATE OF THIS COMMUNICATION.
`Extensions of time may be available under the provisions of 37 CFR 1.136(a).
`In no event however may a reply be timely filed
`after SIX () MONTHS from the mailing date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any
`earned patent term adjustment. See 37 CFR 1 .704(b).
`
`Status
`
`1)IZI Responsive to communication(s) filed on 1 October 2012.
`El A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/were filed on
`
`2b)|:l This action is non-final.
`2a)|Z| This action is FINAL.
`3)I:I An election was made by the applicant in response to a restriction requirement set forth during the interview on
`
`; the restriction requirement and election have been incorporated into this action.
`
`4)|:| Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`
`closed in accordance with the practice under Exparte Quay/e, 1935 CD. 11, 453 O.G. 213.
`
`Disposition of Claims
`
`5)IZI Claim(s) 149 is/are pending in the application.
`5a) Of the above claim(s)
`is/are withdrawn from consideration.
`
`is/are allowed.
`6)I:I Claim(s)
`7)|Z| CIaim(s)_1-9is/are rejected.
`8)|:I Claim(s)_ is/are objected to.
`
`
`are subject to restriction and/or election requirement.
`9)I:I Claim((s)
`* If any claims have been determined allowable, you may be eligible to benefit from the Patent Prosecution Highway program at a
`
`participating intellectual property office for the corresponding application. For more information, please see
`htt
`:/'/\WNI.LIsoto. ovI’ atentS/init events/
`
`
`
`hI/index.‘s or send an inquiry to PPI-iieedback{®usgto.00v.
`
`Application Papers
`
`10)I:l The specification is objected to by the Examiner.
`11)IXI The drawing(s) filed on 31 October 2008 is/are: a)IXI accepted or b)|:l objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`
`12)IXI Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
`Certified copies:
`
`a)IZl All
`
`b)|:l Some * c)I:l None of the:
`
`1.IXI Certified copies of the priority documents have been received.
`2.|:l Certified copies of the priority documents have been received in Application No.
`3.|:| Copies of the certified copies of the priority documents have been received in this National Stage
`
`application from the International Bureau (PCT Rule 17.2(a)).
`* See the attached detailed Office action for a list of the certified copies not received.
`
`Interim copies:
`
`a)|:l All
`
`b)I:I Some
`
`c)I:I None of the:
`
`Interim copies of the priority documents have been received.
`
`Attachment(s)
`
`1) D Notice of References Cited (PTO-892)
`
`3) D Interview Summary (PTO-413)
`
`Paper N°ISI/Ma" Date' —
`PTO/SB/Os
`t
`t
`St
`I
`D'
`I'
`f
`2 IZI I
`)
`4) I:I Other:
`a emen (s) (
`Isc osure
`n orma Ion
`)
`Paper No(s)/Mai| Date 4/23/2012.
`U.S. Patent and Trademark Office
`PTOL—326 (Rev. 03-13)
`
`Part of Paper No./Mai| Date 20130405
`
`Office Action Summary
`
`

`

`Application/Control Number: 12/289,669
`
`Page 2
`
`Art Unit: 2694
`
`DETAILED ACTION
`
`1.
`
`All claims are drawn to the same invention claimed in the application prior to the
`
`entry of the submission under 37 CFR 1.114 and could have been finally rejected on the
`
`grounds and art of record in the next Office action if they had been entered in the
`
`application prior to entry under 37 CFR 1.114. Accordingly, THIS ACTION IS MADE
`
`FINAL even though it is a first action after the filing of a request for continued
`
`examination and the submission under 37 CFR 1.114. See MPEP § 706.07(b).
`
`Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
`
`A shortened statutory period for reply to this final action is set to expire THREE
`
`MONTHS from the mailing date of this action.
`
`In the event a first reply is filed within
`
`TWO MONTHS of the mailing date of this final action and the advisory action is not
`
`mailed until after the end of the THREE-MONTH shortened statutory period, then the
`
`shortened statutory period will expire on the date the advisory action is mailed, and any
`
`extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of
`
`the advisory action. In no event, however, will the statutory period for reply expire later
`
`than SIX MONTHS from the mailing date of this final action.
`
`2.
`
`Applicant's arguments filed 10/1/2012 have been fully considered but they are
`
`Response to Arguments
`
`not persuasive.
`
`3.
`
`Applicant contends:
`
`

`

`Application/Control Number: 12/289,669
`
`Page 3
`
`Art Unit: 2694
`
`For example, neither Akimoto nor Kimura teaches or suggests that "the driving transistor
`operates in a saturation region of the driving transistor to control light emission intensity of the
`light emitting means and a length of the light emission period with the inclined wave voltage" as
`required by independent claim 1. Rather, as noted by the Examiner On page 9 of the Final Office
`Action, Akimoto fails to include any teaching or suggestion of this required limitation of claim 1
`
`4.
`
`Examiner respectfully disagrees. Applicant first points out that Examiner points to
`
`different embodiments of Kimura. However, Examiner points out again that [0448]
`
`points out that this driving method can be used with embodiment modes 1 to 9. The
`
`driving method in embodiment to is controlling “the driving transistor of the pixel is
`
`operated in a saturation region, and the gate-source voltage of the driving transistor is
`
`increased in order of gradation 1, gradation 2, .
`
`.
`
`.
`
`, and gradation 7 in the case of 8-
`
`gradation display, a current ld flowing into the display element 210 can be controlled in
`
`accordance with the gradation of the pixel.” Or, in other words the driving transistor is
`
`operated in the saturation region and controlled by the gate source voltage. The gate-
`
`source gate voltage is increased as the gradation increases. The brighter the pixel the
`
`more the gate is opened.
`
`5.
`
`As pointed out previously Akimoto teaches the structure and driving of
`
`Applicant’s disclosure (see fig. 4 SWP and triangle wave). Exactly the same as
`
`applicant’s fig. 5 except Applicant’s figure 5 reproduces the brightness. The brightness
`
`will follow the triangle wave because this is the data that was provided. Akimoto fails to
`
`expressly teach operating the driving transistor in the saturation region. Examiner notes
`
`implicitly Akimoto may already be driving the driving transistor in the saturation region
`
`otherwise the brightness would be saturated in Akimoto since the driving means and
`
`structure are the same as applicant’s (see Applicant’s disclosure [0087]).
`
`

`

`Application/Control Number: 12/289,669
`
`Page 4
`
`Art Unit: 2694
`
`6.
`
`Kimura teaches an analog means of driving the driving transistor in the saturation
`
`region [0456, 483 and 704]. It would have been obvious to one of ordinary skill in the art
`
`to operate the driving transistor in the saturation region in order to reduce flicker, drive
`
`in a technique that is well known (analog means) and to control the brightness, i.e, over
`
`saturate the brightness.
`
`7.
`
`In response to Applicant’s remarks that Examiner fails to provide a rebuttal
`
`examiner would respectfully disagree. The driving method of embodiment 10 is a well-
`
`known method of controlling the gate-source voltage of the driving transistor in order
`
`increase the order of gradation, which expressly is operating in the saturation region.
`
`The driving method of embodiment 10 is not only embodied in only providing a constant
`
`data signal. Kimura goes on to teach how a triangle wave can be used while the driving
`
`transistor can operate in the saturation region [0700-0711]. The test for obviousness is
`
`not whether the features of a secondary reference may be bodily incorporated into the
`
`structure of the primary reference; nor is it that the claimed invention must be expressly
`
`suggested in any one or all of the references. Rather, the test is what the combined
`
`teachings of the references would have suggested to those of ordinary skill in the art.
`
`See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
`
`Applicant goes on to state, “[t]hus, while non-preferred implementations of this
`
`embodiment of Kimura may result in the driving transistor 5101 controlling the gradation
`
`that is expressed by the pixel with the triangular wave voltage for a brief portion of the
`
`light emission period, it is very clear that the driving transistor 5101 in Kimura does not
`
`control the length of the light emission period when operating in the saturation region.
`
`

`

`Application/Control Number: 12/289,669
`
`Page 5
`
`Art Unit: 2694
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`Rather, as Kimura explicitly states, "the light emitting period is Set...when the driving
`
`transistor 5101 operates in the linear region." (Paras. [0712].)(Pg.11). Examiner notes,
`
`any operation in the saturation region that controls light intensity and length reads on
`
`the claims even if it briefly. The intensity could be gradation 1 or gradation 0 and the
`
`length is present from no length to some length as expressed in [0713] which points to
`
`fig. 50 and the saturation region.
`
`8.
`
`In response to applicant’s argument that there is no teaching, suggestion, or
`
`motivation to combine the references, the examiner recognizes that obviousness may
`
`be established by combining or modifying the teachings of the prior art to produce the
`
`claimed invention where there is some teaching, suggestion, or motivation to do so
`
`found either in the references themselves or in the knowledge generally available to one
`
`of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir.
`
`1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR
`
`International Co. v. Te/ef/ex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
`
`In this case,
`
`Kimura provides means wherein the light emitting time can be dispersed within
`
`one frame. Consequently, the frame frequency appears to be improved and screen
`
`flicker can be prevented [167] and [457]. Flicker is prevented in multiple embodiments of
`
`Kimura see fig. 59. It is the because of the light emitting time can be dispersed with in
`
`one frame, i.e, varied. Kimura shows different means of dispersing the light whether it is
`
`controlling the data in a triangle form, or providing a constant data with a varied
`
`gradation, or a combination of both. Examiner is relying on these teachings to improve
`
`Akimoto.
`
`

`

`Application/Control Number: 12/289,669
`
`Page 6
`
`Art Unit: 2694
`
`Applicant is invited to schedule an examiner interview if they believe it would help
`
`advance prosecution.
`
`Claim Rejections - 35 USC § 103
`
`1.
`
`The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all
`
`obviousness rejections set forth in this Office action:
`
`(a) A patent may not be obtained though the invention is not identically disclosed or described as set
`forth in section 102 of this title, if the differences between the subject matter sought to be patented and
`the prior art are such that the subject matter as a whole would have been obvious at the time the
`invention was made to a person having ordinary skill in the art to which said subject matter pertains.
`Patentability shall not be negatived by the manner in which the invention was made.
`
`2.
`
`The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148
`
`USPQ 459 (1966), that are applied for establishing a background for determining
`
`obviousness under 35 U.S.C. 103(a) are summarized as follows:
`
`1.
`
`2.
`3.
`4.
`
`Determining the scope and contents of the prior art.
`Ascertaining the differences between the prior art and the claims at issue.
`Resolving the level of ordinary skill in the pertinent art.
`Considering objective evidence present in the application indicating
`obviousness or nonobviousness.
`
`3.
`
`Claims 1-9 are rejected under 35 U.S.C. 103(a) as being unpatentable over
`
`Akimoto (US 20070132693 A1) in view of Kimura et al (2009/0051674) hereinafter,
`
`Kimura, as a translation of Kimura (KR10-2007-0091146) Published 09-07-2007.
`
`In regards to claim 1, Akimoto teaches an image display device ("organic EL
`
`display") [fig. 1; par. 44] having a plurality of pixels (“pixels 1”) [figs. 1 and 2], into each
`
`of which an image voltage is input during a writing period and an inclined wave voltage
`
`

`

`Application/Control Number: 12/289,669
`
`Page 7
`
`Art Unit: 2694
`
`which changes a voltage level thereof according to time is input during a light emission
`
`period following the writing period [fig. 4; pars. 55-58], wherein
`
`each of the pixels has
`
`a light emitting means (“organic EL element 2”) [fig. 2; par. 47],
`
`a driving transistor for driving the light emitting means according to the image voltage
`
`(p-type drive TFT 4”) [fig. 2], and “[0062] Next, if the light-emission control switch 12 is
`
`switched OFF by use of the light-emission control switch control line 13, the drain end of
`
`the drive TFT 4 is saturated toward the voltage whose value is obtained by subtracting
`
`the threshold voltage Vth from the supply voltage prr. At this point of time, the drive
`
`TFT 4 is turned OFF (period from III to IV). “
`
`a capacitance device having one end connected to a gate electrode of the driving
`
`transistor and wherein (“storage capacitance 6”) [fig. 2; par. 47],
`
`the image voltage and the inclined wave voltage are input to other end of the
`
`capacitance device during the writing period and the light emission period, respectively,
`
`(The pixel switch 7 is switched ON during a writing period of a selected pixel 1 by
`
`driving the gate of the pixel switch low by use of switch control line 9. While in the
`
`writing period, the storage capacitance 6 is input with an image voltage by way of this
`
`pixel switch. Once the writing period for the selected pixel is over triangular switch 8 is
`
`switched ON while pixel switch 7 is turned OFF a light emission period for the selected
`
`pixel begins. During this light emission period a triangular wave is input to storage
`
`

`

`Application/Control Number: 12/289,669
`
`Page 8
`
`Art Unit: 2694
`
`capacitance 6 by way of triangular switch 8.) [figs. 2, 4, and 5; par. 47 and pars. 55-58]
`
`and
`
`Akimoto fails to expressly teach wherein the driving transistor operates in a
`
`saturation region of the driving transistor to control light emission intensity of the light
`
`emitting means and a length of the light emission period with the inclined wave voltage.
`
`However, Kimura teaches wherein the driving transistor operates in a saturation
`
`region of the driving transistor to control light emission intensity of the light emitting
`
`means and a length of the light emission period. (fig. 3 light emitting period and” [0456]
`
`For example, as shown in FIG. 82, the driving transistor of the pixel is operated in a
`
`saturation region, and the gate-source voltage of the driving transistor is increased in
`
`order of gradation 1, gradation 2, .
`
`.
`
`.
`
`, and gradation 7 in the case of 8—gradation
`
`display, a current ld flowing into the display element 210 can be controlled in
`
`accordance with the gradation of the pixel.
`
`It is to be noted that the gate-source voltage
`
`of the driving transistor 206 of the pixel in the case of gradation O is made lower than
`
`the threshold voltage thereof so that the current ld is O. [0457] By employing the driving
`
`method described in this embodiment mode, the emission intensity of the pixel can be
`
`controlled in an analog manner to express gradation. Accordingly, screen flicker can be
`
`prevented. “ and [704].
`
`

`

`Application/Control Number: 12/289,669
`
`Page 9
`
`Art Unit: 2694
`
`FIG. 82
`
`id"
`
`Iinear region -— —-» saturation region
`
`gradation 7
`
`gradation 6
`
`gradation 1
`
`gradation 5
`
`gradation 4
`
`gradation 3
`
`gradation 2
`
`We
`
`The prior art contained a “base device” upon which the claimed invention can be
`
`seen as an “improvement”. The prior contained a known technique that is applicable to
`
`the base device (i.e, “the driving transistor operated in a saturation region”) One of
`
`ordinary skill in the art would have recognized that applying the known technique would
`
`have yield predictable results and resulted in the improved system of driving the driving
`
`transistor and further providing means of reducing flicker.
`
`Therefore, Akimoto as modified by Kimura teaches to control light emission
`
`intensity of the light emitting means and a length of the light emission period with the
`
`inclined wave voltage ([figs. 2, 4, and 5; par. 47 and pars. 55-58] Akimoto). Examiner
`
`

`

`Application/Control Number: 12/289,669
`
`Page 10
`
`Art Unit: 2694
`
`notes the intensity control depends on the gray scale voltage of the pixel and any
`
`amount of time display time is a control of the length of light emission.
`
`light emission intensity of the light emitting means while emitting light always
`
`changes within the light emission period (Light emission intensity is controlled by use of
`
`triangular wave voltage during the light emission period, once the signal voltage is
`
`stored in storage capacitance 6 during the writing period.) [par. 58] Akimoto and fig. 3
`
`light emitting period of Kimura.
`
`IlIIII1 I
`
`FIG. 3
`
`G1 line
`i-th row
`
`(E52 line
`i-th row
`
`(31 line
`
`{i+1)—ih row
`
`GE tine
`
`(i-r1)~th row
`
`Data line
`
`jvth column
`
`.d.—--.—
`
`‘-l-—.—-———-
`
`
`
`
`qall-I:-
`
`
`
`
`
`
`
`
`
`~u--—-—-—.--———--—1..-...-
`
`
`
`
`
`
`writing period
`
`77777777hghlemtthng period
`
`

`

`Application/Control Number: 12/289,669
`
`Page 11
`
`Art Unit: 2694
`
`In regards to claim 2, Akimoto teaches an image display device ("organic EL
`
`display") [fig. 1; par. 44], having
`
`a plurality of pixels (“pixels 1”) [figs. 1 and 2],
`
`a plurality of signal lines (“signal line DAT”) [figs.
`
`1 and 2] for inputting an image
`
`voltage to each of the plurality of pixels [par. 44], and
`
`pixel selecting means (“scanning circuit 22”) [fig. 1] for selecting from the plurality
`
`of pixels a pixel into which the image voltage is to be written via the plurality of signal
`
`lines (scanning circuit 22 controls which pixel is to be written into by use pixel switch
`
`control line 9.) [par. 47 last sentence], wherein
`
`each of the pixels has
`
`a light emitting device of a current driving-type (“organic EL element 2”) [fig. 2;
`
`par. 47],
`
`a driving transistor for driving the light emitting means according to the image
`
`voltage and connected between a power line and the light emitting device p-type drive
`
`TFT 4”) [fig. 2] [0062], and
`
`

`

`Application/Control Number: 12/289,669
`
`Page 12
`
`Art Unit: 2694
`
`a capacitance device having one end connected to a gate electrode of the driving
`
`transistor (“storage capacitance 6”) [fig. 2; par. 47],
`
`the image voltage is input to other end of the capacitance device during the
`
`writing period [0058-0062],
`
`inclined wave voltage which changes a voltage level thereof according to time is
`
`input to the other end of the capacitance device during a light emission period following
`
`the writing period (The pixel switch 7 is switched ON during a writing period of a
`
`selected pixel 1 by driving the gate of the pixel switch low by use of switch control line 9.
`
`While in the writing period, the storage capacitance 6 is input with an image voltage by
`
`way of this pixel switch. Once the writing period for the selected pixel is over triangular
`
`switch 8 is switched ON while pixel switch 7 is turned OFF and a light emission period
`
`for the selected pixel begins. During this light emission period a triangular wave is input
`
`to storage capacitance 6 by way of triangular switch 8.) [figs. 2, 4, and 5; par. 47 and
`
`pars. 55-58], and
`
`Akimoto fails to expressly teach wherein the driving transistor operates in a
`
`saturation region of the driving transistor to control light emission intensity of the light
`
`emitting means and a length of the light emission period with the inclined wave voltage.
`
`However, Kimura teaches wherein the driving transistor operates in a saturation
`
`region of the driving transistor to control light emission intensity of the light emitting
`
`means and a length of the light emission period [0456-0457].
`
`

`

`Application/Control Number: 12/289,669
`
`Page 13
`
`Art Unit: 2694
`
`The prior art contained a “base device” upon which the claimed invention can be
`
`seen as an “improvement”. The prior contained a known technique that is applicable to
`
`the base device (i.e, “the driving transistor operated in a saturation region”) One of
`
`ordinary skill in the art would have recognized that applying the known technique would
`
`have yield predictable results and resulted in the improved system of driving the driving
`
`transistor.
`
`Therefore, Akimoto as modified by Kimura teaches to control light emission
`
`intensity of the light emitting means and a length of the light emission period with the
`
`inclined wave voltage ([figs. 2, 4, and 5; par. 47 and pars. 55-58] Akimoto). Examiner
`
`notes the intensity control depends on the gray scale voltage of the pixel and any
`
`amount of time display time is a control of the length of light emission.
`
`the light emission intensity of the light emitting device while emitting light always
`
`changes within the light emission period (Light emission intensity is controlled by use of
`
`triangular wave voltage during the light emission period, once the signal voltage is
`
`stored in storage capacitance 6 during the writing period.) [par. 58 ] Akimoto and fig. 3
`
`light emitting period of Kimura.
`
`In regards to claim 3, Akimoto teaches the image display device according to
`
`claim 2, wherein
`
`

`

`Application/Control Number: 12/289,669
`
`Page 14
`
`Art Unit: 2694
`
`the pixel selecting means has a plurality of scanning lines (One end of each pixel
`
`switch control line 9, one end of each light-emission control switch control line 13, and
`
`one end of each reset switch control line 11 are connected to a scanning circuit 22.)
`
`[figs. 2 and 3; par 44 and par. 47 last sentence],
`
`each of the pixels has a reset transistor (“reset switch 5”) [fig. 2] connected
`
`between the gate electrode of the driving transistor and an electrode of the driving
`
`transistor, the electrode being connected to the light emitting device [figs. 2 and 7], and
`
`the gate electrode of the reset transistor is connected to a corresponding
`
`scanning line among the plurality of scanning lines (The gate electrode of reset
`
`transistor 5 is connected to reset switch control line 11.) [par. 47 last sentence].
`
`In regards to claim 4, Akimoto teaches the image display device according to
`
`claim 2, wherein
`
`the pixel selecting means has a plurality of lighting control lines (“light-emission
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`control switch control line 13”) [figs. 1 and 2],
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`each of the pixels has a lighting transistor (“light-emission control switch 12”)
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`connected between the driving transistor and the light emitting device [fig. 2],
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`a gate electrode of each lighting transistor is connected to a corresponding
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`lighting control line among the plurality of lighting control lines (The gate electrode of
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`Application/Control Number: 12/289,669
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`Page 15
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`Art Unit: 2694
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`lighting transistor 12 is connected to light-emission control switch control line 13.) [par.
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`47 last sentence].
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`In regards to claim 5, Akimoto teaches the image display device according to
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`claim 4, wherein
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`the writing period is divided into successive first to third periods (Periods II, III,
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`and IV are successive first to third period of a writing period.) [pars. 60-63],
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`the reset transistor of each of the pixels remains on during the first period and the
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`second period within the writing period and off during the third period within the writing
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`period and the light emission period (Reset transistor 5 remains on while reset switch
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`control line 11 is at a high voltage value. As can be seen on figure 5, reset transistor 5
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`remains on during periods II and III of the writing period and is off during period IV of the
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`writing period and all of the light emission period, which begins after the writing period
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`ends.) [fig. 5; pars. 60-63],
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`the lighting transistor of each of the pixels remains on during the light emission
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`period and the first period within the writing period and off during the second period and
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`the third period within the writing period (Lighting transistor 12 remains on while light-
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`emission control switch control line 13 is at a low voltage value. As can be seen on
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`figure 5, lighting transistor 12 remains on during the lighting period and period ll of the
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`writing period and is off during periods Ill and IV of the writing period.) [fig. 5; pars. 60-
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`63].
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`In regards to claim 6, Akimoto teaches the image display device according to
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`claim 2, further comprising
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`a plurality of inclined wave voltage input lines (“triangular wave line SWP”) [figs. 1
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`and 2] for inputting the inclined wave voltage to each of the pixels (As can be seen on
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`figures 4 and 5, the triangular, i.e. incline, wave voltage is applied to each pixel when
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`pixel switch control line goes from a low voltage to a high voltage, that is when the
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`writing period ends and the lighting period begins. ) [par. 44 last line and par. 58],
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`wherein
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`each of the pixels includes
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`a first switching transistor (“p-type pixel switch 7”) [fig. 2] for connecting the other
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`end of the capacitance device to a corresponding signal line among the plurality of
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`signal lines during the writing period (P-type transistor 7 connects a corresponding
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`signal line DAT while the voltage level of pixel switch control line 9 is a low voltage level,
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`i.e. the writing period.) [figs. 4 and 5; par. 47 last sentence and par. 55], and
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`a second switching transistor (“n-type triangular wave switch 8”) [fig. 2] for
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`connecting the other end of the capacitance device to a corresponding inclined wave
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`voltage input line among the plurality of inclined wave voltage input lines during the light
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`emission period (As can be seen on figures 4 and 5, the triangular, i.e. incline, wave
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`voltage is applied to each pixel when pixel switch control line goes from a low voltage to
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`Application/Control Number: 12/289,669
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`Page 17
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`Art Unit: 2694
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`a high voltage, that is when the writing period ends and the lighting period begins. ) [par.
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`44 last line and par. 58].
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`In regards to claim 7, Akimoto teaches the image display device according to
`
`claim 6, wherein
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`the pixel selecting means includes a plurality of switch control lines (“pixel switch
`
`control line 9”) [figs. 1 and 2],
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`the first switching transistor and the second switching transistor differ from each
`
`other in an electricity conductive type (The first switching transistor 7 is p-type and the
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`second switching transistor 8 is n-type.) [fig. 2],
`
`a gate electrode of the first switching transistor of each of the pixels and a gate
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`electrode of the second switching transistor are connected to a corresponding same
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`switch control line among the plurality of switch control lines [fig. 2],
`
`the first switching transistor and the second switching transistor of each of the
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`pixels remain on and off, respectively, during the writing period [figs. 4 and 5; and par.
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`55], and
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`the first switching transistor and the second switching transistor of each of the
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`pixels remain off and on, respectively, during the light emission period [figs. 4 and 5;
`
`and par. 58].
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`In regards to claim 8, Akimoto teaches the image display device according to
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`claim 1 wherein the light emitting device is an organic light emitting diode device
`
`(“organic EL element 2”) [fig. 2; par. 47 first sentence].
`
`In regards to claim 9, Akimoto teaches the image display device according to
`
`claim 2 wherein the light emitting device is an organic light emitting diode device
`
`(“organic EL element 2”) [fig. 2; par. 47 first sentence].
`
`Conclusion
`
`1.
`
`THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time
`
`policy as set forth in 37 CFR 1.136(a).
`
`A shortened statutory period for reply to this final action is set to expire THREE
`
`MONTHS from the mailing date of this action.
`
`In the event a first reply is filed within
`
`TWO MONTHS of the mailing date of this final action and the advisory action is not
`
`mailed until after the end of the THREE-MONTH shortened statutory period, then the
`
`shortened statutory period will expire on the date the advisory action is mailed, and any
`
`extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of
`
`the advisory action.
`
`In no event, however, will the statutory period for reply expire later
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`than SIX MONTHS from the mailing date of this final action.
`
`Any inquiry concerning this communication or earlier communications from the
`
`examiner should be directed to GRANT SITTA whose telephone number is (571 )270-
`
`1542. The examiner can normally be reached on M-F 9-6.
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`

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`Application/Control Number: 12/289,669
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`Page 19
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`Art Unit: 2694
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`If attempts to reach the examiner by telephone are unsuccessful, the examiner’s
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`supervisor, Alexander Beck can be reached on 571 -272-7765. The fax phone number
`
`for the organization where this application or proceeding is assigned is 571-273-8300.
`
`Information regarding the status of an application may be obtained from the
`
`Patent Application Information Retrieval (PAIR) system. Status information for
`
`published applications may be obtained from either Private PAIR or Public PAIR.
`
`Status information for unpublished applications is available through Private PAIR only.
`
`For more information about the PAIR system, see http://pair-direct.uspto.gov. Should
`
`you have questions on access to the Private PAIR system, contact the Electronic
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`Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a
`
`USPTO Customer Service Representative or access to the automated information
`
`system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
`
`/Grant D Sitta/
`
`Primary Examiner, Art Unit 2629
`
`