`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`www.uspto.gov
`
`APPLICATION NO.
`
`
`
`
` FILING DATE
`
`
`FIRST NAMED INVENTOR
`
`ATTORNEY DOCKET NO.
`
`
`
`
`CONFIRMATIONNO.
`
`
`12/033,909
`
`02/20/2008
`
`Tohru SASAKI
`
`520.48540X00
`
`7217
`
`20457
`
`7590
`
`03/11/2013
`
`ANTONELLI, TERRY, STOUT & KRAUS, LLP
`1300 NORTH SEVENTEENTH STREET
`SUITE 1800
`ARLINGTON,VA 22209-3873
`
`BOYD, JONATHAN A
`
`2691
`
`MAIL DATE
`
`03/11/2013
`
`DELIVERY MODE
`
`PAPER
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`PTOL-90A (Rev. 04/07)
`
`

`

`
`Application No.
`Applicant(s)
`
`Office Action Summary
`
`12/033,909
`Examiner
`JONATHAN BOYD
`
`SASAKI, TOHRU
`Art Unit
`2691
`
`-- The MAILING DATEof this communication appears on the cover sheet with the correspondence address--
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLYIS SET TO EXPIRE 3 MONTH(S) OR THIRTY(30) DAYS,
`WHICHEVER IS LONGER, FROM THE MAILING DATE OF THIS COMMUNICATION.
`Extensions of time may be available underthe provisions of 37 CFR 1.136(a).
`In no event, however, may a reply be timely filed
`after SIX (6) MONTHS from the mailing date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Anyreply received by the Office later than three months after the mailing date of this communication, evenif timely filed, may reduce any
`earned patent term adjustment. See 37 CFR 1.704(b).
`
`Status
`
`1)X] Responsive to communication(s)filed on 19 July 2012.
`2a)L] This action is FINAL.
`2b)X] This action is non-final.
`3)L] An election was made bythe applicant in response to a restriction requirement set forth during the interview on
`
`; the restriction requirement and election have been incorporated into this action.
`4)_] Sincethis application is in condition for allowance exceptfor formal matters, prosecution as to the merits is
`closed in accordance with the practice under Ex parte Quayle, 1935 C.D. 11, 453 O.G. 213.
`
`Disposition of Claims
`
`5)X] Claim(s) 13,14 and 36-43 is/are pending in the application.
`
`5a) Of the above claim(s)
`is/are withdrawn from consideration.
`6)L] Claim(s) ___ is/are allowed.
`
`7)X] Claim(s) 13,14 and 36-43is/are rejected.
`8)L] Claim(s) ___is/are objectedto.
`
`9)L] Claim(s)
`are subject to restriction and/or election requirement.
`
`* If any claims have been determined allowable, you maybeeligible to benefit from the Patent Prosecution Highway
`program at a participating intellectual property office for the corresponding application. For more information, please see
`htto//Awww.uspto.gov/patenis/init events/ooh/index.jiso or send an inquiry to PPHieedback@usopio.qov.
`
`
`Application Papers
`
`10)L] The specification is objected to by the Examiner.
`
`11) The drawing(s) filed on
`is/are: a)[_] accepted or b)[_] objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121(d).
`
`Priority under 35 U.S.C. § 119
`
`12)[] Acknowledgmentis made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
`a)L] All
`)LJ Some * c)L] None of:
`1..] Certified copies of the priority documents have been received.
`2.L] Certified copies of the priority documents have been received in Application No.
`3.L] Copiesof the certified copies of the priority documents have been receivedin this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`* See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`1) Xx Notice of References Cited (PTO-892)
`
`2) Xx] Information Disclosure Statement(s) (PTO/SB/08)
`Paper No(s)/Mail Date 6/27/12.
`U.S. Patent and Trademark Office
`
`3) CT] Interview Summary (PTO-413)
`Paper No(s)/Mail Date.
`4) | Other:
`
`PTOL-326 (Rev. 09-12)
`
`Office Action Summary
`
`Part of Paper No./Mail Date 20130305
`
`
`
`

`

`Application/Control Number: 12/033,909
`Art Unit: 2691
`
`Page 2
`
`DETAILED ACTION
`
`Response to Arguments
`
`1.
`
`Applicant’s arguments with respect to claims 13 and 14 have been considered
`
`but are moot because the arguments do notapply to any of the references being used
`
`in the current rejection.
`
`Claim Rejections - 35 USC § 103
`
`2.
`
`The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all
`
`obviousnessrejections setforth in this Office action:
`
`(a) A patent may not be obtained though the invention is not identically disclosed or described as set
`forth in section 102ofthis title, if the differences between the subject matter sought to be patented and
`the prior art are such that the subject matter as a whole would have been obviousat the time the
`invention was made to a person having ordinary skill in the art to which said subject matter pertains.
`Patentability shall not be negatived by the manner in which the invention was made.
`
`3.
`
`The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148
`
`USPQ 459 (1966), that are applied for establishing a background for determining
`
`obviousness under 35 U.S.C. 103(a) are summarized asfollows:
`
`PoNn>
`
`Determining the scope and contentsof the prior art.
`Ascertaining the differences between the prior art and the claims at issue.
`Resolving the level of ordinary skill in the pertinentart.
`Considering objective evidence presentin the application indicating
`obviousness or nonobviousness.
`
`4.
`
`Claims 13, 14 and 36-43 are rejected under 35 U.S.C. 103(a) as being
`
`unpatentable over Shih (2004/0207649)in view of Okumuraetal (6,115,018) (herein
`
`“Okumura’”) and further in view of lwasaki et al (5,774,099) (herein “Iwasaki”)
`
`In regards to claim 13, Shih teaches a liquid crystal display device comprising: a
`
`liquid crystal display panel provided with a plurality of sub-pixels (See; Abstract), a
`
`

`

`Application/Control Number: 12/033,909
`Art Unit: 2691
`
`Page 3
`
`plurality of video wirings for inputting a video voltage to the sub-pixels (See; Fig 3A for
`
`data line 304), a plurality of main-scanning wirings for inputting a selective scanning
`
`voltage to the sub-pixels (See; Fig. 3A for scanning line 302), a plurality of sub-scanning
`
`wirings provided corresponding to the plurality of the main-scanning wirings (See;Fig.
`
`3A for black image line 308), and a retention capacity wiring (See; Fig. 3A for common
`
`line 306); a video wiring drive circuit for supplying the video voltage to the plurality of the
`
`video wirings (See; pf{0098] for data driver IC); a main-scanning wiring drive circuit for
`
`supplying a main-scanning voltage to the plurality of the main-scanning wirings; a sub-
`
`scanning wiring drive circuit for supplying a sub-scanning voltage to the plurality of the
`
`sub-scanning wirings (See; p[0098] and abstract for a gate driver IC which can
`
`separately send two signals to switch each transistor); and a retention capacity voltage
`
`generation circuit for supplying a retention capacity voltage to the retention capacity
`
`wiring (See; Fig. 3a for commonline 306 which is supplied a common voltage from a
`
`commonvoltage generator), wherein eachof the sub-pixels includes a pixel electrode,
`
`an opposedelectrode, a main transistor and a sub transistor (See; Fig. 3A); an opposed
`
`voltage generation circuit is provided for supplying an opposedvoltage to the opposed
`
`electrode (See; Fig 3A for Vcom supplied to the opposedelectrode of the pixel
`
`electrode); the main transistor has a gate electrode connected to the main-scanning
`
`wiring, a first electrode connected to the video wiring, and a second electrode
`
`connected to the pixel electrode (See; Fig. 3A for transistor 312); and the sub transistor
`
`has a gate electrode connected to the sub-scanning wiring, a first electrode connected
`
`to the retention capacity wiring, and a second electrode connectedto the pixel electrode
`
`

`

`Application/Control Number: 12/033,909
`Art Unit: 2691
`
`Page 4
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`(See; Fig. 3A for transistor 318); wherein the retention capacity wiring is divided for
`
`every display line (See; Fig. 3A for an example of a commonpixel, where it is inherent
`
`that all pixels would be similarly wired and therefore the commonline 306 would be
`
`divided for every display line of pixels); wherein the main-scanning wiring drive circuit
`
`supplies the main-scanning voltage which turns the main transistor on in a first period
`
`and turns the main transistor off from a second to a fourth period following the first
`
`period to the plurality of the main-scanning wirings sequentially (See; Fig. 3C and
`
`p[0058] where the main transistor is turned on at time T1 and subsequently turns off
`
`from period T2-T5); the sub-scanning wiring drive circuit supplies the sub-scanning
`
`voltage which turns the sub transistor off in the first period and the following second
`
`period, turns the sub transistor on in the third period following the second period, and
`
`turns the sub transistor off in the fourth period following the third period to the plurality of
`
`the sub-scanning wirings sequentially (See; Fig. 4C and p[O059] where at T2 the black
`
`imagetransistor 318 is turned on andis then off from T3-T5. Period descriptions in Fig.
`
`3C differ from that of the instant application, e.g. T2 of Shih would equalthe third period
`
`of the instant application, and T3-T5 would equal the fourth period of the instant
`
`application). Shih fails to explicitly teach wherein the retention capacity wiring is a
`
`different wiring from a wiring which connects the opposed electrode with the opposed
`
`voltage generation circuit.
`
`However Okumura teachesa retention capacity wiring (See; Figs. 1-2 for Cs Line
`
`N and Col4, line 23-Col 8, line 18) which is different from the wiring which connects the
`
`opposed electrode with the opposed voltage generation circuit (See; Figs. 1-2 for Vcom
`
`

`

`Application/Control Number: 12/033,909
`Art Unit: 2691
`
`Page 5
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`line connected at opposing end ofthe liquid crystal capacitor CLC). Therefore it would
`
`have been obvious to one of ordinary skill in the art at the time of the invention to
`
`separate the retention capacity wiring and common voltage line so as to have more
`
`precise control over the two voltages.
`
`The combination of Shih and Okumura furtherfail to explicitly teach wherein the
`
`video wiring drive circuit is configured to set the video voltage as a positive video
`
`voltage and to supply the positive video voltage to the video wirings from the video
`
`wiring drive circuit at a higher potential than an opposed voltage input to the opposed
`
`electrodein a first operating mode, wherein the video wiring drive circuit is configured to
`
`set the video voltage as a negative video voltage and to supply the negative video
`
`voltage to the video wirings from the video wiring drive circuit at a lower potential than
`
`the opposed voltage input to the opposed electrode in a second operating mode,
`
`wherein the retention capacity voltage generation circuit is configured to supply the
`
`retention capacity voltage Vstat a first level VstH to the retention capacity wiring in the
`
`third and the fourth periods whenthe video wiring drive circuit supplies the positive
`
`video voltage to the video wirings from the video wiring drive circuit in the first and
`
`wherein the retention capacity voltage generation circuit is configured to supply the
`
`retention capacity voltage Vst at a second level VstL at a lower potential than thefirst
`
`level VstH to the retention capacity wiring in the third and the fourth periods when the
`
`video wiring drive circuit supplies the negative video voltage to the video wirings from
`
`the video wiring drive circuit in the first period.
`
`However Iwasaki teaches wherein the video wiring drive circuit is configured to
`
`

`

`Application/Control Number: 12/033,909
`Art Unit: 2691
`
`Page 6
`
`set the video voltage as a positive video voltage and to supply the positive video voltage
`
`to the video wirings from the video wiring drive circuit at a higher potential than an
`
`opposedvoltage input to the opposedelectrodein a first operating mode, wherein the
`
`video wiring drive circuit is configured to set the video voltage as a negative video
`
`voltage and to supply the negative video voltage to the video wirings from the video
`
`wiring drive circuit at a lower potential than the opposed voltage input to the opposed
`
`electrode in a second operating mode, wherein the retention capacity voltage
`
`generation circuit is configured to supply the retention capacity voltage Vstat a first
`
`level VstH to the retention capacity wiring in the third and the fourth periods when the
`
`video wiring drive circuit supplies the positive video voltage to the video wirings from the
`
`video wiring drive circuit in the first and wherein the retention capacity voltage
`
`generation circuit is configured to supply the retention capacity voltage Vst at a second
`
`level VstL at a lower potential than the first level VstH to the retention capacity wiring in
`
`the third and the fourth periods whenthe video wiring drive circuit supplies the negative
`
`video voltage to the video wirings from the video wiring drive circuit in the first period
`
`(See; Figs. 5A), 5C and Column 13, line 26- Column 14, line 56 where the polarity of the
`
`gate voltage video voltage is in direct correspondence with Vcom. Where the gate
`
`voltage is at a first level Vgih when a positive video voltage (Vcomh)is fed and at a
`
`secondlevel Vgil when a negative video voltage (vcoml) is fed, where Vgil has a lower
`
`potential than Vgth).
`
`Therefore it would have been obvious to one ofordinary skill in the art at the time
`
`of the invention to control the opposedelectrode in this manner described by Iwasaki to
`
`

`

`Application/Control Number: 12/033,909
`Art Unit: 2691
`
`Page 7
`
`increase viewing angles ofthe liquid crystal panel and drive and lower power
`
`consumption.
`
`|n regards to claim 14, Shih teachesa liquid crystal display device comprising: a
`
`liquid crystal display panel provided with a plurality of sub-pixels (See; Abstract), a
`
`plurality of video wirings for inputting a video voltage to the sub-pixels (See; Fig 3A for
`
`data line 304), a plurality of main-scanning wirings for inputting a selective scanning
`
`voltage to the sub-pixels (See; Fig. 3A for scanning line 302), a plurality of sub-scanning
`
`wirings provided corresponding to the plurality of the main-scanning wirings (See;Fig.
`
`3A for black image line 308), and a retention capacity wiring (See; Fig. 3A for common
`
`line 306); a video wiring drive circuit for supplying the video voltage to the plurality of the
`
`video wirings (See; pf{0098] for data driver IC); a main-scanning wiring drive circuit for
`
`supplying a main-scanning voltage to the plurality of the main-scanning wirings; a sub-
`
`scanning wiring drive circuit for supplying a sub-scanning voltage to the plurality of the
`
`sub-scanning wirings (See; p[0098] and abstract for a gate driver IC which can
`
`separately send two signals to switch each transistor); and a retention capacity voltage
`
`generation circuit for supplying a retention capacity voltage to the retention capacity
`
`wiring (See; Fig. 3a for commonline 306 which is supplied a common voltage from a
`
`commonvoltage generator), wherein eachof the sub-pixels includes a pixel electrode,
`
`an opposedelectrode, a main transistor and a sub transistor (See; Fig. 3A); an opposed
`
`voltage generation circuit is provided for supplying an opposedvoltage to the opposed
`
`electrode (See; Fig 3A for Vcom supplied to the opposed electrode of the pixel
`
`

`

`Application/Control Number: 12/033,909
`Art Unit: 2691
`
`Page 8
`
`electrode); the main transistor has a gate electrode connected to the main-scanning
`
`wiring, a first electrode connected to the video wiring, and a second electrode
`
`connected to the pixel electrode (See;Fig. 3A for transistor 312); and the sub transistor
`
`has a gate electrode connected to the sub-scanning wiring, a first electrode connected
`
`to the retention capacity wiring, and a second electrode connectedto the pixel electrode
`
`(See; Fig. 3A for transistor 318); wherein the retention capacity wiring is divided for
`
`every display line (See; Fig. 3A for an example of a commonpixel, where it is inherent
`
`that all pixels would be similarly wired and therefore the commonline 306 would be
`
`divided for every display line of pixels); wherein the main-scanning wiring drive circuit
`
`supplies the main-scanning voltage which turns the main transistor on in a first period
`
`and turns the main transistor off from a second to a fourth period following the first
`
`period to the plurality of the main-scanning wirings sequentially (See; Fig. 3C and
`
`p[0058] where the main transistor is turned on at time T1 and subsequently turns off
`
`from period T2-T5); the sub-scanning wiring drive circuit supplies the sub-scanning
`
`voltage which turns the sub transistor off in the first period and the following second
`
`period, turns the sub transistor on in the third period following the second period, and
`
`turns the sub transistor off in the fourth period following the third period to the plurality of
`
`the sub-scanning wirings sequentially (See; Fig. 4C and p[0059] where at T2 the black
`
`imagetransistor 318 is turned on andis then off from T3-T5. Period descriptions in Fig.
`
`3C differ from that of the instant application, e.g. T2 of Shih would equalthe third period
`
`of the instant application, and T3-T5 would equal the fourth period of the instant
`
`application). Shih fails to explicitly teach wherein the retention capacity wiring is a
`
`

`

`Application/Control Number: 12/033,909
`Art Unit: 2691
`
`Page 9
`
`different wiring from a wiring which connects the opposed electrode with the opposed
`
`voltage generation circuit.
`
`However Okumura teachesa retention capacity wiring (See; Figs. 1-2 for Cs Line
`
`N and Col4, line 23-Col 8, line 18) whichis different from the wiring which connects the
`
`opposed electrode with the opposed voltage generation circuit (See; Figs. 1-2 for Vcom
`
`line connected at opposing end ofthe liquid crystal capacitor CLC). Therefore it would
`
`have been obvious to one of ordinary skill in the art at the time of the invention to
`
`separate the retention capacity wiring and common voltage line so as to have more
`
`precise control over the two voltages.
`
`The combination of Shih and Okumura furtherfail to explicitly teach wherein the
`
`video wiring drive circuit is configured to set the video voltage as a positive video
`
`voltage and to supply the positive video voltage to the video wirings from the video
`
`wiring drive circuit at a higher potential than an opposed voltage input to the opposed
`
`electrodein a first operating mode, wherein the video wiring drive circuit is configured to
`
`set the video voltage as a negative video voltage and to supply the negative video
`
`voltage to the video wirings from the video wiring drive circuit at a lower potential than
`
`the opposed voltage input to the opposed electrode in a second operating mode,
`
`wherein the retention capacity voltage generation circuit is configured to supply the
`
`retention capacity voltage Vstat a first level VstH to the retention capacity wiring in the
`
`third and the fourth periods whenthe video wiring drive circuit supplies the positive
`
`video voltage to the video wirings from the video wiring drive circuit in the first and
`
`wherein the retention capacity voltage generation circuit is configured to supply the
`
`

`

`Application/Control Number: 12/033,909
`Art Unit: 2691
`
`Page 10
`
`retention capacity voltage Vst at a second level VstL at a lower potential than thefirst
`
`level VstH to the retention capacity wiring in the third and the fourth periods when the
`
`video wiring drive circuit supplies the negative video voltage to the video wirings from
`
`the video wiring drive circuit in the first period.
`
`However Iwasaki teaches wherein the video wiring drive circuit is configured to
`
`set the video voltage as a positive video voltage and to supply the Positive video
`
`voltage to the video wirings from the video wiring drive circuit at a higher potential than
`
`an opposedvoltage input to the opposedelectrodein a first operating mode, wherein
`
`the video wiring drive circuit is configured to set the video voltage as a negative video
`
`voltage and to supply the negative video voltage to the video wirings from the video
`
`wiring drive circuit at a lower potential than the opposed voltage input to the opposed
`
`electrode in a second operating mode, wherein the retention capacity voltage
`
`generation circuit is configured to supply the retention capacity voltage Vstat a first
`
`level VstH to the retention capacity wiring in the third period when the video wiring drive
`
`circuit supplies the positive video voltage to the video wirings from the video wiring drive
`
`circuit in the first period, and wherein the retention capacity voltage generation circuit is
`
`configured to supply the retention capacity voltage Vst at a second level VstL at the
`
`lower potential than the first level VstH to the retention capacity wiring in the third period
`
`when the video wiring drive circuit supplies the negative video voltage to the video
`
`wirings from the video wiring drive circuit in the first period (See; Figs. 5A, 5C and
`
`Column 13, line 26- Column 14, line 56 where the polarity of the gate voltage video
`
`voltage is in direct correspondence with Vcom. Where the gate voltageis at a first level
`
`

`

`Application/Control Number: 12/033,909
`Art Unit: 2691
`
`Page 11
`
`Vgih when a positive video voltage (Vcomh) is fed and at a secondlevel Vgil when a
`
`negative video voltage (vcoml) is fed, where Vgil has a lowerpotential than Vgth).
`
`Therefore it would have been obvious to one ofordinary skill in the art at the time
`
`of the invention to control the opposedelectrode in this manner described by Iwasaki to
`
`increase viewing angles of the liquid crystal panel and drive and lower power
`
`consumption.
`
`In regards to claims 36 and 40, Shih teaches wherein a retention capacity is
`
`provided at one of portions between the second electrode of the sub transistor and the
`
`retention capacity wiring (See; Fig. 3A).
`
`In regards to claims 37 and 41, Shih teaches wherein the first electrode of the
`
`sub transistor is connected to the retention capacity wiring on the display line scanned
`
`immediately previously (See; Fig. 3A for transistor 318 connected to commonline 306).
`
`In regardsto claims 38 and 42, Shih teaches wherein the first electrode of the
`
`sub transistor is connected to the retention capacity wiring on the display line
`
`subsequently scanned (See; Fig. 3A for transistor 318 connected to commonline 306).
`
`In regards to claims 39 and 43, Shih teaches wherein the opposedelectrodeis
`
`divided for every display line (See; Fig. 3A for an example of a commonpixel, whereit
`
`is inherent that all pixels would be similarly wired and therefore the common line 306
`
`

`

`Application/Control Number: 12/033,909
`Art Unit: 2691
`
`Page 12
`
`would be divided for every display line of pixels). Shih fails to explicitly teach when the
`
`retention capacity voltage supplied to the retention capacity wiring on the display line
`
`corresponds to the second level VstL, the opposed voltage Vcom supplied to the
`
`opposedelectrode on the display line from the opposed voltage generation circuit has a
`
`first level VcomH, and whenthe retention capacity voltage supplied to the retention
`
`capacity wiring on the display line correspondsto the first level VstH, the opposed
`
`voltage Vcom has a secondlevel VcomL at a lower potential than thefirst level VcomH.
`
`However, Iwasaki teaches whenthe retention capacity voltage supplied to the
`
`retention capacity wiring on the display line corresponds to the second level VstL, the
`
`opposed voltage Vcom supplied to the opposedelectrode on the display line from the
`
`opposed voltage generation circuit hasafirst level VcomH, and whenthe retention
`
`capacity voltage supplied to the retention capacity wiring on the displayline
`
`correspondsto the first level VstH, the opposed voltage Vcom has a secondlevel
`
`VcomL at a lower potential than the first level VcomH (See;Figs. 5A, 5B and Column
`
`13, line 26- Column 14, line 56 where the polarity of the gate voltage video voltage is in
`
`direct correspondence with Vcom. Where the gate voltage is at a first level Vglh when a
`
`positive video voltage (Vcomh)is fed and at a secondlevel Vgll when a negative video
`
`voltage (vcoml) is fed, where Vgil has a lower potential than Vgih)..
`
`Therefore it would have been obvious to one ofordinary skill in the art at the time
`
`of the invention to control the opposedelectrode in this manner described by Iwasaki to
`
`increase viewing angles of the liquid crystal panel and drive and lower power
`
`

`

`Application/Control Number: 12/033,909
`Art Unit: 2691
`
`consumption.
`
`Page 13
`
`Conclusion
`
`Anyinquiry concerning this communication or earlier communications from the
`
`examiner should be directed to JONATHAN BOYD whosetelephone numberis
`
`(571)270-7503. The examiner can normally be reached on Mon - Fri 6:00 - 4:00 EST.
`
`If attempts to reach the examiner by telephone are unsuccessful, the examiner's
`
`supervisor, Amr Awad can be reached on 571-272-7764. The fax phone numberfor the
`
`organization wherethis application or proceeding is assigned is 571-273-8300.
`
`Information regarding the status of an application may be obtained from the
`
`Patent Application Information Retrieval (PAIR) system. Status information for
`
`published applications may be obtained from either Private PAIR or Public PAIR.
`
`Status information for unpublished applications is available through Private PAIR only.
`
`For more information about the PAIR system, see http://pair-direct.uspto.gov. Should
`
`you have questions on accessto the Private PAIR system, contact the Electronic
`
`Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a
`
`USPTO Customer Service Representative or access to the automatedinformation
`
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`
`(JONATHAN BOYD/
`Examiner, Art Unit 2691
`
`