VOLTAGE SUPPLY CIRCUIT
`
`BACKGROUND OF THE INVENTION
`
`1.
`
`Field of Invention
`
`The present
`
`invention relates to a voltage supply circuit
`
`for
`
`supplying predetermined DC voltages to electronic circuit blocks inside
`
`various kinds of electronic appliances.
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`1O
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`2.
`
`Description of Related Art
`
`In recent years, as mobile appliances typified by mobile phones
`
`become multifunctional,
`
`the need for supplying different power source
`
`voltages and different reference voltages to various electronic circuit
`
`blocks (hereafter referred to as load circuits)
`is
`increasing.
`For this
`purpose, a voltage supply circuit being used for such load circuits requires
`
`15
`
`multiple power source circuits.
`
`As a conventional example of this kind of voltage supply circuit, for
`
`example, a voltage supply circuit disclosed in Japanese Laid-open Patent
`
`Publication No. 1999-65685 is available.
`
`FIG. 7 is a circuit diagram
`
`20
`
`showing the voltage supply circuit according to this conventional example.
`
`In FIG. 7, the voltage supply circuit according to the conventional example
`
`contains operational amplifier circuits 21p, 22p and 23p, a first constant
`
`current circuit 24p, a second constant current circuit 25p, a third constant
`
`current circuit 26p, and a reference voltage generating circuit 20p. The
`
`25
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`operational amplifier circuits 21 p to 23p generate voltages Vo1p, VoZp and
`
`Vo3p. The operational amplifier circuits 21p to 23p supply power from the
`
`output terminals 11p, 12p and 13p thereof to load circuits, respectively.
`
`The first constant current circuit 24p, the second constant current circuit
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`

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`25p and the third constant current circuit 26p pass constant currents for
`
`operating the respective operational amplifier circuits.
`
`The reference
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`voltage generating circuit 20p supplies a reference voltage Vrefp to the
`
`respective operational amplifier circuits. A power source voltage Vccp is
`
`supplied from a power source terminal 1p to the above—mentioned
`
`respective circuits.
`
`The operational amplifier circuits 21p to 23p and the second
`
`constant current circuit 25p can operate when the power source voltage
`
`Vccp is supplied. On the other hand, the cut terminals Tc1p and Tc3p of
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`10
`
`the first constant current circuit 24p and the third constant current circuit
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`26p are connected to the ground line side. The activation or deactivation
`
`of the constant current circuits 24p and 26p can be set depending on
`
`whether the cut terminals are grounded or not. A constant current
`
`is
`
`supplied to the reference voltage generating circuit 20p from the second
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`15
`
`constant current circuit 25p, whereby the reference voltage generating
`
`circuit 20p generates the reference voltage Vrefp from the constant current.
`
`The reference voltage Vrefp is input to the non—inverting input terminals of
`
`the operational amplifier circuits 21p to 23p. Feedback resistors 42p, 44p
`
`and 46p are connected between the output terminals and the inverting
`
`20
`
`input
`
`terminals of the operational amplifier circuits 21p, 22p and 23p,
`
`respectively, and grounding resistors 43p, 45p and 47p are connected
`
`between the inverting input terminals of the operational amplifier circuits
`
`21p, 22p and 23p and the ground,
`
`respectively.
`
`From the reference
`
`voltage Vrefp, the operational amplifier circuits 21p, 22p and 23p generate
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`25
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`DC constant voltages Vo1p, V02p and V03p determined using the
`
`feedback resistors 42p, 44p and 46p and the grounding resistors 43p, 45p
`
`and 47p,
`
`respectively, as described below.
`
`It
`
`is assumed that
`
`the
`
`resistance values of the resistors 42p, 43p, 44p, 45p, 46p and 47p are R2p,
`
`

`

`R3p, R4p, R5p, R6p and R7p, respectively.
`
`Vo1p = Vrepr(R2p + R3p)/R3p
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`V02p = Vrepr(R4p + R5p)/R5p
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`V03p = Vrepr(R6p + R7p)lR7p
`
`The operational amplifier circuit 21p is configured so that, when the
`
`current supply from the first constant current circuit 24p is cut off,
`
`the
`
`voltage output
`
`from the operational amplifier circuit 21p is stopped.
`
`Similarly, the operational amplifier circuit 23p is configured so that, when
`
`the current supply from the third constant current circuit 26p is cut off, the
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`1O
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`voltage output from the operational amplifier circuit 23p is stopped.
`
`In
`
`other words, whether the DC constant voltages Vo‘lp and Vo3p are output
`
`or not can be determined by switching depending on whether the cut
`
`terminals Tc1p and Tc2p are grounded or opened, respectively. Hence,
`
`when the voltage output from each of the output terminals 11p and 13p is
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`15
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`stopped, power consumption due to the flow of unnecessary current in the
`
`circuits for generating the power source voltages therefor does not
`
`increase, whereby efficient operation can be attained.
`
`SUMMARY OF THE INVENTION
`
`20
`
`However,
`
`in the voltage supply circuit according to the conventional
`
`example described above, since the current supply to the operational
`
`amplifier circuit is cut off when the power source voltage output is stopped,
`
`there is a problem in which a certain time is required when the power
`
`source voltage output is supplied subsequently. Furthermore, in the case
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`25
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`that it
`
`is not necessary to perform voltage supply to two or more load
`
`circuits at a time, a configuration including multiple operational amplifier
`
`circuits has a problem in which the usage efficiency of the voltage supply
`
`circuit is low and the size thereof increases.
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`

`

`For the purpose of solving the problems encountered in the voltage
`
`supply circuit according to the conventional example, an object of the
`
`present invention is to provide a voltage supply circuit capable of being
`
`reduced in size and capable of quickly raising a voltage to be output in the
`
`case that it is not necessary to perform voltage supply to two or more load
`
`circuits at a time.
`
`In order to attain the above-mentioned object,
`
`the voltage supply
`
`circuit according to the present invention comprises a reference voltage
`
`generating circuit operable to generate a predetermined reference voltage;
`
`10
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`an operational amplifier circuit operable to generate an output voltage on
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`the basis of the reference voltage; a selection circuit having at least two
`
`first terminals and controlled on the basis of a control signal from a control
`
`section to select one of the first terminals and to generate a passed output
`
`voltage representing the output voltage passed through the first terminal
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`15
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`selected; a second terminal operable to receive the passed output voltage
`
`and capable of outputting the passed output voltage to a load circuit; and a
`
`detection circuit operable to detect the magnitude of the passed output
`
`voltage and to generate a detection voltage, wherein the selection circuit is
`
`controlled on the basis of
`
`the control signal and selects a voltage
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`20
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`corresponding to the passed output voltage from among at least two of the
`
`detection
`
`voltages
`
`and
`
`generates
`
`a
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`selected
`
`detection
`
`voltage
`
`representing the detection voltage selected, and the operational amplifier
`
`circuit decreases the difference between the reference voltage and the
`
`selected detection voltage.
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`25
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`In the case that voltages different from one another are supplied to
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`two or more load circuits, one voltage at a time, with the use of the
`
`selection circuit,
`
`the voltage supply circuit according to the present
`
`invention can be configured by using only one operational amplifier circuit.
`
`

`

`Hence,
`
`it is possible to reduce the size, power consumption and cost of
`
`the voltage supply circuit. Furthermore, a supply-stop state feedback path
`
`is provided to maintain the operational amplifier circuit at
`
`its activated
`
`state at all times, whereby, when a voltage is started to be supplied to a
`
`load circuit subsequently, the voltage to be supplied can be raised quickly.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG.
`
`1
`
`is a circuit diagram showing a voltage supply circuit
`
`according to a first embodiment of the present invention;
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`1O
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`FIG. 2A is a circuit diagram showing the selection circuit of the
`
`voltage supply circuit according to the first embodiment of the present
`
`invenfion;
`
`FIG. 28 is a relationship diagram showing the selection relationship
`of the selection circuit of the voltage supply circuit according to the first
`
`15
`
`embodiment of the present invention;
`
`FIG. 3 is a circuit diagram showing a voltage supply circuit
`
`according to a second embodiment of the present invention;
`
`FIG. 4 is a circuit diagram showing the selection circuit of the
`
`voltage supply circuit according to the second embodiment of the present
`
`20
`
`invention;
`
`FIG. 5 is a circuit diagram showing a voltage supply circuit
`
`according to a third embodiment of the present invention;
`
`FIG. 6 is a circuit diagram showing a voltage supply circuit
`
`according to a modified example of the third embodiment of the present
`
`25
`
`invention; and
`
`FIG. 7 is a circuit diagram showing the voltage supply circuit
`
`according to the conventional example.
`
`

`

`DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
`
`Some examples of
`
`the best modes for embodying the present
`
`invention will be described below referring to the accompanying drawings.
`
`In the drawings, components having substantially the same configurations,
`
`operations and effects are designated by the same reference codes.
`
`In
`
`addition, numbers described below are all exemplified to specifically
`
`explain the present invention, and the present invention is not limited by
`
`the exemplified numbers. Furthermore,
`
`the logic levels represented by
`
`high/low levels or the switching states represented by ON/OFF states are
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`1O
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`used to specifically exemplify the present invention, and similar results can
`
`also be obtained by variously combining exemplified logic levels or
`
`switching states. Moreover, connections between the components are
`
`exemplified to specifically explain the present invention, and connections
`
`for achieving the functions of the present invention are not limited to these
`
`15
`
`connections.
`
`Still further, although embodiments described below are
`
`configured using hardware and/or software, a configuration implemented
`
`by hardware can also be implemented by software, and a configuration
`
`implemented by software can also be implemented by hardware.
`
`First embodiment
`
`20
`
`FIG.
`
`1
`
`is a circuit diagram showing a voltage supply circuit
`
`according to a first embodiment of the present invention. A DC voltage
`
`source 7, such as a battery, supplies an input DC voltage Vcc to a voltage
`
`supply circuit 6 through the input terminal 1 of the voltage supply circuit 6.
`
`A control section 8 generates a control signal V30 for controlling the
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`25
`
`voltage supply circuit 6. The voltage supply circuit 6 converts the input DC
`
`voltage Vcc into voltages V01, V02 and V03 0n the basis of the control
`
`signal V30 and outputs the voltages V01, V02 and V03 from the output
`
`terminals P01, P02 and P03 0f the voltage supply circuit 6, respectively.
`
`

`

`Load circuits L1, L2 and L3 receive the output voltages Vo1 to V03,
`
`respectively, and perform desired functions. The voltage supply circuit 6
`
`has two states: a supply state and a supply stop state.
`
`In the supply state,
`
`-
`
`the voltage supply circuit 6 receives the input DC voltage Vcc and supplies
`
`one of the output voltages to either one of the load circuits L1 to L3.
`
`In the
`
`supply stop state,
`
`the voltage supply circuit 6 receives the input DC
`
`voltage Vcc, but does not supply the output voltages to any one of the load
`
`circuits L1 to L3.
`
`The voltage supply circuit 6 includes a reference voltage generating
`
`1O
`
`circuit 20, an operational amplifier circuit 2, a selection circuit 3, the output
`
`terminals P01 to P03, and a detection circuit 4. The reference voltage
`
`generating circuit 20 operates by using the input DC voltage Vcc as a
`
`power source voltage and generates a predetermined reference voltage
`
`Vref. The operational amplifier circuit 2 operates by using the input DC
`
`15
`
`voltage Vcc as a power source voltage, receives the reference voltage
`
`Vref at the non—inverting input terminal thereof and generates an output
`
`voltage V0 to the input terminal Po (described later) of the selection circuit
`
`3 on the basis of the reference voltage Vref.
`
`The selection circuit 3 has the input
`
`terminal Po and output
`
`20
`
`terminals P90, P91, P92 and Pg3.‘ The selection circuit 3 receives the
`
`control signal V30 through a control terminal 30 and selects either one of
`
`the output terminals P90 to P93 on the basis of the control signal V30.
`
`Furthermore, the selection circuit 3 passes the output voltage Vo through a
`
`selected one of the output terminals PgO to P93 and generates a passed
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`25
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`output voltage V90, V91, V92 or V93 representing the passed output
`
`voltage V0.
`
`The detection circuit 4 includes resistors 40, 41, 42, 43, 44, 45, 46
`
`and 47 having resistance values R40, R41, R42, R43, R44, R45, R46 and
`
`

`

`R47, respectively. The output terminal P90 of the selection circuit 3 is
`
`connected to a dummy output terminal P00 and to one terminal of the
`
`resistor 40. The other terminal of the resistor 40 is connected to one
`
`terminal of the resistor 41 and to the input terminal PfO of the selection
`
`circuit 3, and the other terminal of the resistor 41 is grounded. The output
`
`terminal P91 of the selection circuit 3 is connected to the output terminal
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`Po1 of the voltage supply circuit 6 and to one terminal of the resistor 42.
`
`The other terminal of the resistor 42 is connected to one terminal of the
`
`resistor 43 and to the input terminal Pf1 of the selection circuit 3, and the
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`1O
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`other terminal of the resistor 43 is grounded. Similarly, the output terminal
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`P92 of the selection circuit 3 is connected to the output terminal P02 of the
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`voltage supply circuit 6 and to one terminal of the resistor 44. The other
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`terminal of the resistor 44 is connected to one terminal of the resistor 45
`
`and to the input terminal Pf2 of the selection circuit 3, and the other
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`15
`
`terminal of the resistor 45 is grounded. Similarly, the output terminal P93
`
`of the selection circuit 3 is connected to the output terminal P03 of the
`
`voltage supply circuit 6 and to one terminal of the resistor 46. The other
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`terminal of the resistor 46 is connected to one terminal of the resistor 47
`
`and to the input
`
`terminal Pf3 of the selection circuit 3, and the other
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`20
`
`terminal of the resistor 47 is grounded. The output terminals Po1 to P03
`
`can be connected to the load circuits L1 to L3, respectively. On the other
`
`hand, the dummy output terminal PoO cannot be connected to any one of
`
`the load circuits L1 to L3.
`
`The output terminal Po1 receives the passed output voltage V91
`
`25
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`and can output the passed voltage Vo1 approximately equal to the passed
`
`output voltage V91 to the load circuit L1.
`
`The output
`
`terminal P02
`
`receives the passed output voltage V92 and can output the passed voltage
`
`V02 approximately equal to the passed output voltage V92 to the load
`
`

`

`circuit L2. The output terminal P03 receives the passed output voltage
`
`Vg3 and can output the passed voltage V03 approximately equal to the
`
`passed output voltage V93 to the load circuit L3. The output terminals P01
`
`to P03 do not receive the passed output voltage VgO.
`
`The detection circuit 4 detects the magnitudes of the passed output
`
`voltages V90, V91, Vg2 and Vg3 and generates detection voltages WC,
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`W1, Vf2 and W3, respectively. More specifically, the detection circuit 4
`
`divides the passed output voltage V00 by multiplying the output voltage
`
`V00 by R41 /(R40 + R41), thereby generating the detection voltage VfO at
`
`1O
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`the input terminal PfO. Similarly, the detection circuit 4 divides the passed
`
`output voltage V01 by multiplying the output voltage V01 by R43/(R42 +
`
`R43), thereby generating the detection voltage Vf1 at the input terminal
`
`Pf1. Similarly, the detection circuit 4 divides the passed output voltage
`
`V02 by multiplying the output voltage V02 by R45/(R44 + R45), thereby
`
`15
`
`generating the detection voltage Vf2 at the input terminal Pf2. Similarly,
`
`the detection circuit 4 divides the passed output voltage V03 by multiplying
`
`the output voltage V03 by R47/(R46 + R47),
`
`thereby generating the
`
`detection voltage Vf3 at the input terminal Pf3. Hence, Expression 1,
`
`Expression 2, Expression 3 and Expression 4 are established.
`
`20
`
`VfO = VoOxR41/(R4o + R41)
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`W1 = V01XR43/(R42 + R43)
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`Vf2 = Vo2xR45/(R44 + R45)
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`m = VosxR47/(R4e + R47)
`
`(1)
`
`(2)
`
`(3)
`
`(4)
`
`The selection circuit 3 selects one of the detection voltages VfO to
`
`25
`
`Vf3 corresponding to the passed output voltages VgO to Vg3 to be
`
`generated, on the basis of the control signal V30, and generates a
`
`selected detection voltage Vf representing the selected detection voltage
`
`at the output terminal Pf of the selection circuit 3. More specifically, in the
`
`

`

`10
`
`case that
`
`the output
`
`terminal P90 is selected and the passed output
`
`voltage VgO is generated,
`
`the selection circuit 3 selects the detection
`
`voltage VfO. Similarly,
`
`in the case that the output terminal Pg1 is selected
`
`and the passed output voltage Vg1 is generated, the selection circuit 3
`
`selects the detection voltage Vf1. Similarly,
`
`in the case that the output
`
`terminal P92 is selected and the passed output voltage V92 is generated,
`
`the selection circuit 3 selects the detection voltage Vf2. Similarly,
`
`in the
`
`case that
`
`the output
`
`terminal P93 is selected and the passed output
`
`voltage V93 is generated,
`
`the selection circuit 3 selects the detection
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`1O
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`voltage Vf3.
`
`The operational amplifier circuit 2 receives the selected detection
`
`voltage Vf at the inverting input terminal thereof and generates the output
`
`voltage Vo so that the difference between the reference voltage Vref and
`
`the selected detection voltage Vf becomes small. More specifically,
`
`in the
`
`15
`
`case that the selected detection voltage Vf is lower than the reference
`
`voltage Vref,
`
`the output voltage Vo rises and the selected detection
`
`voltage Vf rises, whereby the difference between the reference voltage
`
`Vref and the selected detection voltage Vf becomes small. Conversely, in
`
`the case that the selected detection voltage Vf is higher than the reference
`
`20
`
`voltage Vref,
`
`the output voltage Vo lowers and the selected detection
`
`voltage Vf lowers, whereby the difference between the reference voltage
`
`Vref and the selected detection voltage Vf becomes small.
`
`The operational amplifier circuit 2 has the function of an error
`
`amplifier circuit that generates an error amplification voltage,
`
`that is, a
`
`25
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`voltage monotonically increasing with respect to an error voltage obtained
`
`by subtracting the selected detection voltage Vf from the reference voltage
`
`Vref and having a predetermined voltage when the error voltage is zero.
`
`The operational amplifier circuit 2 further has the function of a current
`
`

`

`11
`
`amplifier circuit
`
`that current-amplifies the error amplification voltage to
`
`generate the output voltage Vo.
`
`In other words, the operational amplifier
`
`circuit 2 further has the function of a power amplifier circuit that power-
`
`amplifies the error amplification voltage to generate the output voltage Vo.
`
`FIG. 2A is a detailed circuit diagram showing the selection circuit 3.
`
`The selection circuit 3 includes an output selection circuit 3A, an input
`
`selection circuit SB and a selection control circuit 3C. The selection
`
`control circuit 3C receives the control signal V30 through the control
`
`terminal 30 and controls the output selection circuit 3A and the input
`
`1O
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`selection circuit BB on the basis of the control signal V30. The output
`
`selection circuit 3A selects either one of the output terminals PgO to Pg3,
`
`and passes the output voltage Vo through the selected output terminal to
`
`generate one of the passed output voltages Vg0 to Vg3.
`
`The input
`
`selection circuit 38 selects one of the detection voltages Vf0 to Vf3 at the
`
`15
`
`input terminals PfO, Pf1, Pf2 and Pf3, corresponding to the passed output
`
`voltages VgO to Vg3 to be generated, respectively, thereby generating the
`
`selected detection voltage Vf at the output terminal Pf of the selection
`
`circuit 3.
`
`The selection control circuit 3C includes an inverter 300, a NOR
`
`20
`
`circuit 310, a NAND circuit 311, a NOR circuit 312, a NAND circuit 313,
`
`and inverters 320, 321, 322 and 323. The control signal V30 at the control
`
`terminal 30 includes a control signal V31 at a terminal 31 and a control
`
`signal V32 at a terminal 32. The inverter 300 generates an inverted
`
`control signal V300 obtained by inverting the control signal V31. The NOR
`
`25
`
`circuit 310 generates a gate signal GfO representing the NOR of the
`
`control signal V31 and the control signal V32. The NAND circuit 311
`
`generates a gate signal G01 representing the NAND of the control signal
`
`V32 and the inverted control signal V300. The NOR circuit 312 generates
`
`

`

`12
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`a gate signal Gf2 representing the NOR of the inverted control signal V300
`and the control signal V32. The NAND circuit 313 generates a gate signal
`
`G03 representingthe NAND of the control signal V31 and the control
`signal V32. The inverter 320 generates a gate signal G00 representing the
`
`NOT of the gate signal GfO. The inverter 321 generates a gate signal Gf1
`
`representing the NOT of the gate signal G01. The inverter 322 generates
`
`a gate signal G02 representing the NOT of the gate signal Gf2. The
`
`inverter 323 generates a gate signal Gf3 representing the NOT of the gate
`
`signal G03.
`
`1O
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`FIG. 2B is a relationship diagram showing a selection relationship in
`
`the selection circuit 3. When the control signal V30 changes from O to 3,
`
`the control signal V31 and the control signal V32 each have a value
`
`obtained by binary—coding the control signal V30 as shown in FIG. ZB.
`
`In
`
`the case that
`
`the control signal V30 is 0, only the gate signal G00
`
`15
`
`(underlined) in the output selection circuit 3A becomes low level, and only
`
`the gate signal GfO (underlined) in the input selection circuit BB becomes
`
`high level.
`
`In the case that the control signal V30 is 1, only the gate signal
`
`G01 in the output selection circuit 3A becomes low level, and only the gate
`
`signal Gf1 in the input selection circuit 3B becomes high level.
`
`In the case
`
`20
`
`that the control signal V30 is 2, only the gate signal G02 in the output
`
`selection circuit 3A becomes low level, and only the gate signal Gf2 in the
`
`input selection circuit 3B becomes high level.
`
`In the case that the control
`
`signal V30 is 3, only the gate signal G03 in the output selection circuit 3A
`
`becomes low level, and only the gate signal Gf3 in the input selection
`
`25
`
`circuit 3B becomes high level.
`
`The output selection circuit 3A includes a P-channel MOS (metal
`
`oxide semiconductor) transistor 330, a P—channel MOS transistor 331, a P-
`
`channel MOS transistor 332 and a P-channel MOS transistor 333. The
`
`

`

`13
`
`source terminals of the P-channel MOS transistors 330, 331, 332 and 333
`
`are all connected to the input terminal Po, and the drain terminals of the P-
`
`channel MOS transistors 330 to 333 are connected to the output terminals
`
`PgO to P93,
`
`respectively.
`
`The gate terminals of the P—channel MOS
`
`transistors 330, 331, 332 and 333 are controlled by the gate signals G00,
`
`601 602 and G03, respectively.
`
`In the case that the control signal V30 is 0, only the P—channel MOS
`
`transistor 330 is turned ON. At this time, the P-channel MOS transistor
`
`330 passes the output voltage Vo at the input terminal Po and generates
`
`1O
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`the passed output voltages VgO at the selected output terminal PgO.
`
`In the
`
`case that the control signal V30 is 1, only the P-channel MOS transistor
`
`331 is turned ON. At this time, the P-channel MOS transistor 331 passes
`
`the output voltage Vo at the input terminal Po and generates the passed
`
`output voltages Vg1 at the selected output terminal Pg1.
`
`In the case that
`
`15
`
`the control signal V30 is 2, only the P—channel MOS transistor 332 is
`
`turned ON. At this time, the P-channel MOS transistor 332 passes the
`
`output voltage Vo at the input
`
`terminal Po and generates the passed
`
`output voltages V92 at the selected output terminal P92.
`
`In the case that
`
`the control signal V30 is 3, only the P—channel MOS transistor 333 is
`
`20
`
`turned ON. At this time, the P-channel MOS transistor 333 passes the
`
`output voltage Vo at the input
`
`terminal Po and generates the passed
`
`output voltages Vg3 at the selected output terminal Pg3.
`
`The input selection circuit 3B includes an N—channel MOS transistor
`
`340, an N-channel MOS transistor 341, an N-channel MOS transistor 342
`
`25
`
`and an N-channel MOS transistor 343. The source terminals of the N-
`
`channel MOS transistors 340 to 343 are connected to the input terminals
`
`PfO to Pf3, respectively, and the drain terminals of the P—channel MOS
`
`transistors 340 to 343 are all connected to the output terminal Pf. The
`
`

`

`14
`
`gate terminals of the N—channel MOS transistors 340, 341, 342 and 343
`
`are controlled by the gate signals GfO, Gf1 Gf2 and Gf3, respectively.
`
`In the case that the control signal V30 is 0, only the N—channel MOS
`
`transistor 340 is turned ON. At this time, the N—channel MOS transistor
`
`340 passes the detection voltage VfO at
`
`the input
`
`terminal PfO and
`
`generates the selected detection voltage Vf at the output terminal Pf.
`
`In
`
`the case that
`
`the control signal V30 is 1, only the N-channel MOS
`
`transistor 341 is turned ON. At this time, the N-channel MOS transistor
`
`341 passes the detection voltage Vf1 at
`
`the input
`
`terminal PH and
`
`10
`
`generates the selected detection voltage Vf at the output terminal Pf.
`
`In
`
`the case that
`
`the control signal V30 is 2, only the N-channel MOS
`
`transistor 342 is turned ON. At this time, the N—channel MOS transistor
`
`342 passes the detection voltage Vf2 at
`
`the input
`
`terminal Pf2 and
`
`generates the selected detection voltage Vf at the output terminal Pf.
`
`In
`
`15
`
`the case that
`
`the control signal V30 is 3, only the N—channel MOS
`
`transistor 343 is turned ON. At this time, the N-channel MOS transistor
`
`343 passes the detection voltage Vf3 at
`
`the input
`
`terminal Pf3 and
`
`generates the selected detection voltage Vf at the output terminal Pf.
`
`Returning to FIG. 1,
`
`in the case that each of the detection voltages
`
`20
`
`VfO to Vf3 is selected by the selection circuit 3,
`
`the detection voltage
`
`becomes equal
`
`to the selected detection voltage Vf.
`
`The selected
`
`detection voltage Vf operates so as to become approximately equal to the
`
`reference voltage Vref
`
`in the operational amplifier circuit 2. Hence,
`
`Expressions
`
`1, 2, 3 and 4 can be converted into Expressions 5,
`
`25
`
`Expression 6, Expression 7 and Expression 8, respectively.
`
`In other words,
`
`in the case that each of the selected output voltages VoO to V03 is
`
`selected by the selection circuit 3, the selected output voltages VoO to V03
`
`are represented by Expressions 5 to 8, respectively. The selected output
`
`

`

`15
`
`voltages VoO to V03 in Expressions 5 to 8 can all be equal to or higher
`
`than the reference voltage Vref and different from one another.
`
`VoO = Vrefx(R4o + R41) IR41
`
`Vo1 = VrefX(R42 + R43) IR43
`
`V02 = Vref><(R44 + R45) /R45
`
`V03 = Vref><(R46 + R47) IR47
`
`(5)
`
`(6)
`
`(7)
`
`(8)
`
`In the case that
`
`the output
`
`terminal P90 is not selected in the
`
`selection circuit 3, no current flows in the resistors 40 and 41, and the
`
`selected output voltage VoO is held at a zero potential (in other words, the
`
`1O
`
`ground potential). Similarly,
`
`in the case that the output terminals Pgl
`
`to
`
`Pg3 are not selected in the selection circuit 3, the selected output voltages
`
`V01 to V03 respectively corresponding to the output terminals are held at
`
`a zero potential.
`
`As described above,
`
`the operational amplifier circuit 2 has the
`
`15
`
`functions of an error amplifier circuit and a current amplifier circuit. The
`
`voltage supply circuit 6 includes four auxiliary voltage supply circuits that
`
`generate the selected output voltages VoO to V03 at the output terminal
`
`PoO to P03, respectively, using this one operational amplifier circuit (the
`
`operational amplifier circuit 2).
`
`In other words, the four auxiliary voltage
`
`20
`
`supply circuits for generating the selected output voltages VoO to V03
`
`share the use of the operational amplifier circuit 2 as a circuit having the
`
`functions of an error amplifier circuit and a current amplifier circuit. Among
`
`these circuits,
`
`the auxiliary voltage supply circuits for generating the
`
`selected output voltages V01 to V03 can supply the voltages to the load
`
`25
`
`circuits L1 to L3, respectively. The auxiliary voltage supply circuit for
`
`generating the selected output voltage VoO is also referred to as a supply-
`
`stop state auxiliary voltage supply circuit, and the auxiliary voltage supply
`
`circuits for generating the selected output voltages Vo1 to Vol3 are also
`
`

`

`16
`
`referred to as supply state auxiliary voltage supply circuits.
`
`In the case that the voltage supply circuit 6 is in the supply stop
`
`state, the selection circuit 3 selects the output terminal P90 and the input
`
`terminal PfO and generates the selected output voltage VoO represented
`
`by Expression 5 at the dummy output terminal P00.
`
`In the supply stop
`
`state of the voltage supply circuit 6, the path from the input terminal P0 to
`
`the inverting input terminal of the operational amplifier circuit 2 through the
`
`output terminal PgO, the dummy output terminal PoO, the resistor 40, the
`
`input terminal Pm and the output terminal Pf is referred to as a supply—stop
`
`1O
`
`state feedback path. Even in the supply stop state of the voltage supply
`
`circuit 6, the operational amplifier circuit 2 is in a steady operation state by
`
`using
`
`the
`
`supply-stop state
`
`feedback path
`
`as described
`
`above.
`
`Furthermore, the selected output voltages V01 to V03 are held at a zero
`
`potential. Next,
`
`in the supply state of the voltage supply circuit 6, when
`
`15
`
`the selection circuit 3 selects the output
`
`terminal P92 and the input
`
`terminal Pf2 to operate the load L2, for example, among the load circuits
`
`L1 to L3, the selected detection voltage Vf changes from the reference
`
`voltage Vref to a zero potential. At this time, the difference between the
`
`selected detection voltage Vf at
`
`the inverting input
`
`terminal and the
`
`20
`
`reference voltage Vref at the non-inverting input terminal
`
`is sufficiently
`
`large. Hence, the voltage supply circuit 6 can quickly raise the selected
`
`output voltage V02 so that
`
`the selected output voltage Vf
`
`is quickly
`
`brought close to the reference voltage Vref by using the operational
`
`amplifier circuit 2 being in the operation state at all times.
`
`In other words,
`
`25
`
`the voltage supply circuit 6 can quickly raise each of the selected output
`
`voltages VoO to V03 by switching the supply-stop state auxiliary voltage
`
`supply circuit to one of the supply state auxiliary voltage supply circuits
`
`using the selection circuit 3.
`
`

`

`17
`
`With the use of the selection circuit 3 as described above,
`
`in the
`
`case that voltages different from one another are supplied to two or more
`
`load circuits, i.e., the load circuits L1 to L3, only one voltage at a time, the
`
`voltage supply circuit 6 according to the first embodiment can be
`
`configured by using only one operational amplifier circuit (the operational
`
`amplifier circuit 2). Hence, the size of the circuit can be reduced, and the
`
`power consumption and cost thereof can also be reduced. Furthermore,
`
`by setting the operational amplifier circuit 2 at its operation state at all
`
`times by providing the supply-stop state feedback path, the voltage supply
`
`1O
`
`circuit 6 can quickly raise the voltage to be supplied in the case that the
`
`voltage is started to be supplied subsequently to one of the load circuits L1
`
`to L3.
`
`Second embodiment
`
`FIG. 3 is a circuit diagram showing a voltage supply circuit 6a. The
`
`15
`
`voltage supply circuit 6a according to the second embodiment is different
`
`from the voltage supply circuit 6 (FIG. 1) according to the first embodiment
`
`in that a buffer circuit 5 is included additionally,
`
`that
`
`the operational
`
`amplifier circuit 2a of the voltage supply circuit 6a is modified from the
`
`operational amplifier circuit 2 and that
`
`the selection circuit 3a of the
`
`20
`
`voltage supply circuit 6a is modified from the selection circuit 3. Since the
`
`other configurations, operations and effects of the voltage supply circuit 6a
`
`are similar to those of the voltage supply circuit 6, descriptions thereof are
`
`omitted.
`
`The buffer circuit 5 includes an N-channel MOS transistor 50, an N-
`
`25
`
`channel MOS transistor 51, an N-channel MOS transistor 52 and an N—
`
`channel MOS transistor 53. The drain terminals of the N-channel MOS
`
`transistors 50, 51, 52 and 53 are all connected to the input terminal 1, and
`
`the gate terminals thereof are respectively connected to the output
`
`

`

`18
`
`terminals PgO to P93.
`
`The source terminals of the N—c