`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria1 Virginia 22313- 1450
`wwwnsptogov
`
`APPLICATION NO.
`
`
`
`
`
` F ING DATE
`
`FIRST NAMED INVENTOR
`
`ATTORNEY DOCKET NO.
`
`
`
`
`
`CONF {MATION NO.
`
`12/809, 126
`
`06/18/2010
`
`Yasunobu Tsukio
`
`MAT— 103 74US
`
`7377
`
`EXAMINER
`RATNERPRESTIA —
`WW —
`”90
`W
`PO. BOX 980
`HAIDER, SYED
`VALLEY FORGE, PA 19482-0980
`
`PAPER NUMBER
`
`ART UNIT
`
`2611
`
`MAIL DATE
`
`08/22/2012
`
`DELIVERY MODE
`
`PAPER
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`PTOL—90A (Rev. 04/07)
`
`

`

`
`
`Office Action Summary
`
`Application No.
`
`Applicant(s)
`
`
` 12/809,126 TSUKIO ET AL.
`Examiner
`Art Unit
`SYED HAIDER
`2611
`
`-- The MAILING DA TE of this communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE 3 MONTH(S) OR THIRTY (30) DAYS,
`WHICHEVER IS LONGER, FROM THE MAILING DATE OF THIS COMMUNICATION.
`Extensions of time may be available under the provisions of 37 CFR1. 136(a).
`In no event however may a reply be timely filed
`after SIX () MONTHS from the mailing date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any
`earned patent term adjustment. See 37 CFR 1.704(b).
`
`Status
`
`1)|Zl Responsive to communication(s) filed on 27 June 2012.
`
`2a)IZI This action is FINAL.
`
`2b)|:l This action is non-final.
`
`3)I:I An election was made by the applicant in response to a restriction requirement set forth during the interview on
`
`
`; the restriction requirement and election have been incorporated into this action.
`
`4)|:l Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`
`closed in accordance with the practice under Exparte Quay/e, 1935 CD. 11, 453 O.G. 213.
`
`Disposition of Claims
`
`5)IXI Claim(s) 1-14 is/are pending in the application.
`
`5a) Of the above claim(s) _ is/are withdrawn from consideration.
`
`6)|:| Claim(s) _ is/are allowed.
`
`7)|Xl Claim(s)_1-14 is/are rejected.
`
`8)|:| Claim(s) _ is/are objected to.
`
`9)I:I Claim(s) _ are subject to restriction and/or election requirement.
`
`Application Papers
`
`10)I:I The specification is objected to by the Examiner.
`
`11)I:| The drawing(s) filed on _ is/are: a)|:| accepted or b)|:| objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`12)I:I The oath or declaration is objected to by the Examiner. Note the attached Office Action or form PTO-152.
`
`Priority under 35 U.S.C. § 119
`
`13)|:| Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
`
`a)|:| AII
`
`b)|:l Some * c)I:I None of:
`
`1.I:I Certified copies of the priority documents have been received.
`
`2.|:l Certified copies of the priority documents have been received in Application No. _
`
`3.I:I Copies of the certified copies of the priority documents have been received in this National Stage
`
`application from the International Bureau (PCT Rule 17.2(a)).
`
`* See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`
`
`1) IZI Notice of References Cited (PTO-892)
`2) I] Notice of Draftsperson‘s Patent Drawing Review (PTO-948)
`3) I] Information Disclosure Statement(s) (PTO/SB/08)
`Paper No(s)/Mai| Date _.
`U.S. Patent and Trademark Office
`
`4) I] Interview Summary (PTO-413)
`Paper N0(S )/Mai| Date. _
`5)I:I NOTICQ 0f Informal Patent Application
`6)I:I Other:—
`
`PTOL-326 (Rev. 03-11)
`
`Office Action Summary
`
`Part of Paper No./Mai| Date 20120802
`
`

`

`Application/Control Number: 12/809,126
`
`Page 2
`
`Art Unit: 2611
`
`DETAILED ACTION
`
`Claim Rejections - 35 USC § 102
`
`1.
`
`The following is a quotation of the appropriate paragraphs of 35
`
`U.S.C. 102 that form the basis for the rejections under this section made in this
`
`Office action:
`
`A person shall be entitled to a patent unless —
`
`(b) the invention was patented or described in a printed publication in this or a foreign country
`or in public use or on sale in this country, more than one year prior to the date of application
`for patent in the United States.
`
`2.
`
`Claims 1, rejected under 35 U.S.C. 102(b) as being anticipated by Lee
`
`(US PGPUB 2006/0068720 A1).
`
`3.
`
`As per claim 1, Lee discloses a frequency synthesizer for receiving a
`
`frequency compensation signal and a reference oscillation signal, and for
`
`outputting a first signal and a second signal, the reference oscillation signal
`
`having a varying frequency (Lee, Fig. 2), said frequency synthesizer comprising:
`
`A phase locked loop (PLL) circuit for generating the first signal based on the
`
`reference oscillation signal (Lee, Fig. 2:210:220); and
`
`a frequency divider/multiplier for generating the second signal by frequency-
`
`dividing or frequency-multiplying the first signal from said PLL circuit (Lee, Fig.
`
`2220242), and outputting the second signal to demodulator circuit (Lee, Fig. 2,
`
`demodulator),
`
`wherein the varying frequency of the first signal generated by said PLL circuit is
`
`compensated by the frequency compensation signal (Lee, Fig. 2:220, and
`
`paragraph 13).
`
`

`

`Application/Control Number: 12/809,126
`
`Page 3
`
`Art Unit: 2611
`
`Claim Rejections - 35 USC § 103
`
`4.
`
`The following is a quotation of 35 U.S.C. 103(a) which forms the basis for
`
`all obviousness rejections set forth in this Office action:
`
`(a) A patent may not be obtained though the invention is not identically disclosed or described
`as set forth in section 102 of this title, if the differences between the subject matter sought to
`be patented and the prior art are such that the subject matter as a whole would have been
`obvious at the time the invention was made to a person having ordinary skill in the art to which
`said subject matter pertains. Patentability shall not be negatived by the manner in which the
`invention was made.
`
`5.
`
`Claims 2, 5, 6 and 12-13, are, rejected under 35 U.S.C. 103(a) as being
`
`unpatentable over Lee (US PG PUB 2006/0068720 A1) and further in view of
`
`Saka (US Patent 5,483,686).
`
`6.
`
`As per claim 2, Lee further discloses the frequency synthesizer according
`
`to claim 1, wherein said PLL circuit includes:
`
`a frequency divider for dividing a frequency of the first signal by a frequency-
`
`division rate (Lee, Fig. 4:442); and
`
`Lee does not explicitly disclose a phase comparator for outputting a signal
`
`corresponding to a phase difference between the reference oscillation signal and
`
`the first signal divided by the frequency divider, the oscillator generates the first
`
`signal having a frequency based on the phase difference, and the frequency
`
`divider compensates the frequency of the first signal by controlling the frequency-
`
`division rate based on the frequency compensation signal.
`
`

`

`Application/Control Number: 12/809,126
`
`Page 4
`
`Art Unit: 2611
`
`Saka discloses a phase comparator for outputting a signal corresponding to a
`
`phase difference between the reference oscillation signal and the first signal
`
`divided by the frequency divider (Saka, Fig. 1:103:104:105:106), the oscillator
`
`generates the first signal having a frequency based on the phase difference
`
`(Saka, Fig. 1 :106:103), and the frequency divider compensates the frequency of
`
`the first signal by controlling the frequency-division rate based on the frequency
`
`compensation signal (Saka, Fig. 1:104:106:110).
`
`At the time of the invention it would have been obvious to one of ordinary skill in
`
`the art to modify Lee teachings by generating a signal corresponding to a phase
`
`difference between the reference oscillation signal and the first signal divided by
`
`the frequency divider, as taught by Saka.
`
`The motivation would be to stabilize the synchronization acquisition operation, as
`
`taught by Saka.
`
`7.
`
`As per claim 5, Lee further discloses a receiver comprising:
`
`a frequency synthesizer including a phase locked loop (PLL) circuit for
`
`generating a first signal based on a reference oscillation signal (Lee, Fig.
`
`2210220),
`
`and a frequency divider/multiplier for outputting a second signal by frequency-
`
`dividing or frequency-multiplying the first signal (Lee, Fig. 2:220:242);
`
`Lee does not explicitly disclose a frequency compensator for controlling a
`
`frequency of the first signal,
`
`

`

`Application/Control Number: 12/809,126
`
`Page 5
`
`Art Unit: 2611
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`a frequency converter for outputting an intermediate frequency (IF) signal by
`
`heterodyning a received signal with the first signal; and
`
`a subsequent-stage circuit for processing the IF signal with the second signal.
`
`Saka discloses a frequency compensator for controlling a frequency of the first
`
`signal (Saka, Fig. 1:104:108, and Column 3, lines 5-25),
`
`a frequency converter for outputting an intermediate frequency (IF) signal by
`
`heterodyning a received signal with the first signal (Saka, Fig. 1:103:101 and
`
`Column 3, lines 5-25); and
`
`a subsequent-stage circuit for processing the IF signal with the second signal
`
`(Saka, Fig. 1:102).
`
`At the time of the invention it would have been obvious to one of ordinary skill in
`
`the art to modify Lee teachings by implementing a frequency converter to the
`
`system of Lee, as taught by Saka.
`
`The motivation would be to stabilize the synchronization acquisition operation, as
`
`taught by Saka.
`
`8.
`
`As per claim 6, Lee in view of Saka further discloses the receiver
`
`according to claim 5, wherein the subsequent- stage circuit includes a
`
`demodulator for demodulating the IF signal (Saka, Fig. 1:102), the demodulator
`
`operating with the second signal (Saka, Fig. 1:102).
`
`9.
`
`As per claim 12, Lee further discloses the frequency synthesizer according
`
`to claim 1, wherein said PLL circuit includes:
`
`

`

`Application/Control Number: 12/809,126
`
`Page 6
`
`Art Unit: 2611
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`a frequency divider for dividing a frequency of the second signal by a frequency-
`
`division rate (Lee, Fig. 4:442, and paragraph 13); and
`
`Lee does not explicitly disclose a phase comparator for outputting a signal
`
`corresponding to a phase difference between the reference oscillation signal and
`
`the second signal divided by the frequency divider,
`
`the oscillator generates the first signal having a frequency based on the phase
`
`difference, and the frequency divider compensates the frequency of the first
`
`signal by controlling the frequency-division rate based on the frequency
`
`compensation signal.
`
`Saka discloses a phase comparator for outputting a signal corresponding to a
`
`phase difference between the reference oscillation signal and the second signal
`
`divided by the frequency divider (Saka, Fig. 1:106:103:104),
`
`the oscillator generates the first signal having a frequency based on the phase
`
`difference (Saka, Fig. 1 :103), and the frequency divider compensates the
`
`frequency of the first signal by controlling the frequency-division rate based on
`
`the frequency compensation signal (Saka, Fig. 1 :104:108, and Column 3, lines 5-
`
`25).
`
`At the time of the invention it would have been obvious to one of ordinary skill in
`
`the art to modify Lee teachings by generating a signal corresponding to a phase
`
`difference between the reference oscillation signal and the first signal divided by
`
`the frequency divider, as taught by Saka.
`
`The motivation would be to stabilize the synchronization acquisition operation, as
`
`taught by Saka.
`
`

`

`Application/Control Number: 12/809,126
`
`Page 7
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`Art Unit: 2611
`
`10.
`
`As per claim 13, Lee in view of Saka further discloses the receiver
`
`according to claim 5, wherein said frequency synthesizer further includes: a
`
`frequency divider for dividing a frequency of the second signal by a frequency-
`
`division rate (Lee, Fig. 4:442, and paragraph 13); and
`
`a phase comparator for outputting a signal corresponding to a phase difference
`
`between the reference oscillation signal and the second signal divided by the
`
`frequency divider (Saka, Fig. 1 :106:103:104), the oscillator generates the first
`
`signal having a frequency based on the phase difference (Saka, Fig. 1:103), and
`
`the frequency divider compensates the frequency of the first signal by controlling
`
`the frequency-division rate based on the frequency compensation signal (Saka,
`
`Fig. 1:104:108, and Column 3, lines 5-25).
`
`11.
`
`Claim 3, rejected under 35 U.S.C. 103(a) as being unpatentable over
`
`Lee (US PG PUB 2006/0068720 A1) and further in view of Mizuta (JP 2006-
`
`254060 A, provided by the Applicant).
`
`12.
`
`As per claim 3, Lee further discloses the frequency synthesizer according
`
`to claim 1, further comprising:
`
`and the frequency divider compensates the frequency of the first signal by
`
`controlling the frequency-division rate based on the frequency compensation
`
`signal (Lee, paragraph 13).
`
`

`

`Application/Control Number: 12/809,126
`
`Page 8
`
`Art Unit: 2611
`
`Lee does not explicitly disclose a frequency divider for dividing a frequency of the
`
`second signal by a frequency-division rate; and
`
`a phase comparator for comparing phases of the reference oscillation signal and
`
`the second signal frequency-divided by the frequency divider, wherein the
`
`oscillator generates the first signal having a frequency based on a result of the
`
`comparison by the phase comparator,
`
`Mizuta discloses a frequency divider for dividing a frequency of the second signal
`
`by a frequency-division rate (Mizuta, Fig. 1:8:9:10, output of the dividing circuits
`
`would be second signal); and
`
`a phase comparator for comparing phases of the reference oscillation signal and
`
`the second signal frequency-divided by the frequency divider (Mizuta, Fig. 1 :10:
`
`reference signal from outside, please see paragraph 14), wherein the oscillator
`
`generates the first signal having a frequency based on a result of the comparison
`
`by the phase comparator (Mizuta, Fig. 1:4),
`
`At the time of the invention it would have been obvious to one of ordinary skill in
`
`the art to modify Lee teachings by implementing a multiple frequency divider to
`
`the circuit of Lee, as taught by Mizuta.
`
`The motivation would be to provide a circuit with less power consumption, as
`
`taught by Mizuta.
`
`

`

`Application/Control Number: 12/809,126
`
`Page 9
`
`Art Unit: 2611
`
`13.
`
`Claim 4, rejected under 35 U.S.C. 103(a) as being unpatentable over
`
`Lee (US PG PUB 2006/0068720 A1) and further in view of Hashimoto (US
`
`Patent 5,204,972).
`
`14.
`
`As per claim 4, Lee further discloses the frequency synthesizer according
`
`to claim 1, Lee does not explicitly disclose wherein the frequency of the reference
`
`oscillation signal varies according to a temperature, and the frequency
`
`compensation signal is generated based on the temperature.
`
`Hashimoto discloses wherein the frequency of the reference oscillation signal
`
`varies according to a temperature, and the frequency compensation signal is
`
`generated based on the temperature (Hashimoto Fig. 8:18:52).
`
`At the time of the invention it would have been obvious to one of ordinary skill in
`
`the art to modify Lee teachings by generating a frequency compensation signal
`
`based on temperature, as taught by Hashimoto.
`
`The motivation would be to provide a method of compensating for temperature
`
`dependent performance characteristics of a surface acoustic wave type band-
`
`pass filter for use in a double superheterodyne receiver, as taught by Hashimoto.
`
`15.
`
`Claim 7, rejected under 35 U.S.C. 103(a) as being unpatentable over
`
`Lee (US PG PUB 2006/0068720 A1) and further in view of Saka (US Patent
`
`5,483,686) and further in view of Bhat (US PGPUB 2002/0012074 A1).
`
`16.
`
`As per claim 7, Saka further discloses the receiver according to claim 6,
`
`

`

`Application/Control Number: 12/809,126
`
`Page 10
`
`Art Unit: 2611
`
`Lee in view of Saka does not explicitly disclose wherein the subsequent- stage
`
`circuit further includes a display for displaying the demodulated signal.
`
`Bhat discloses wherein the subsequent- stage circuit further includes a display
`
`for displaying the demodulated signal (Bhat, paragraph 28).
`
`At the time of the invention it would have been obvious to one of ordinary skill in
`
`the art to modify Lee in view of Saka teachings by displaying the demodulated
`
`signal, as taught by Bhat.
`
`The motivation would be to provide a system in which audio quality and even the
`
`picture quality can be enhanced, as taught by Bhat.
`
`17.
`
`Claim 8, rejected under 35 U.S.C. 103(a) as being unpatentable over
`
`Lee (US PG PUB 2006/0068720 A1) and further in view of Saka (US Patent
`
`5,483,686) and further in view of Nakamura (JP 2007-336294 A, provided by
`
`the Applicant).
`
`18.
`
`As per claim 8,Lee in view of Saka further discloses the receiver according
`
`to claim 5, wherein the subsequent- stage circuit includes
`
`Lee in view of Saka does not explicitly disclose a circuit includes a filter for
`
`filtering the IF signal, the filter operating with the second signal.
`
`Nakamura discloses a circuit includes a filter for filtering the IF signal, the filter
`
`operating with the second signal (Nakamura, Fig. 1:103:124).
`
`

`

`Application/Control Number: 12/809,126
`
`Page 11
`
`Art Unit: 2611
`
`At the time of the invention it would have been obvious to one of ordinary skill in
`
`the art to modify Lee in view of Saka teachings by implementing a filter into the
`
`subsequent circuit as taught by Nakmura.
`
`The motivation would be to provide an improved control method for tuner circuit,
`
`as taught by Nakamura.
`
`19.
`
`Claim 9, rejected under 35 U.S.C. 103(a) as being unpatentable over
`
`Lee (US PG PUB 2006/0068720 A1) and further in view of Saka (US Patent
`
`5,483,686) and further in view of Toki (JP 2006-140960 A, provided by the
`
`Applicant).
`
`20.
`
`As per claim 9, Lee in view of Saka further discloses the receiver
`
`according to claim 5, wherein the subsequent- stage circuit includes
`
`Lee in view of Saka does not explicitly disclose a sampling unit for sampling the
`
`IF signal with the second signal.
`
`Toki discloses a sampling unit for sampling the IF signal with the second signal
`
`(Toki, Fig. 7:110:702).
`
`At the time of the invention it would have been obvious to one of ordinary skill in
`
`the art to modify Lee in view of Saka teachings by implementing a sampling unit
`
`to the subsequent circuit of Saka, as taught by Toki.
`
`The motivation would be provide an improved receiver structure, as taught by
`
`Toki.
`
`

`

`Application/Control Number: 12/809,126
`
`Page 12
`
`Art Unit: 2611
`
`21.
`
`Claims 10 and 11, are rejected under 35 U.S.C. 103(a) as being
`
`unpatentable over Lee (US PG PUB 2006/0068720 A1) and further in view of
`
`Saka (US Patent 5,483,686) and further in view of Partridge (US PGPUB
`
`2005/0151592 A1 ).
`
`22.
`
`As per claim 10, Lee in view of Saka further discloses the receiver
`
`according to claim 5,
`
`Lee in view of Saka does not explicitly disclose wherein the reference oscillator
`
`includes an oscillator made of semiconductor.
`
`Patridge discloses wherein the reference oscillator includes an oscillator made of
`
`semiconductor (Patridge, Figs. 15A-15E).
`
`At the time of the invention it would have been obvious to one of ordinary skill in
`
`the art to modify Lee in view of Saka teachings by using an oscillator in the circuit
`
`which is being made of semiconductor, as taught by Patridge.
`
`The motivation would be to provide an improved frequency adjustment circuitry,
`
`as taught by Patridge.
`
`23.
`
`As per claim 11, Lee in view of Saka further discloses the receiver
`
`according to claim 5,
`
`Lee in view of Saka does not explicitly disclose wherein the reference oscillator
`
`and the frequency synthesizer are unitarily formed.
`
`Patridge discloses disclose wherein the reference oscillator and the frequency
`
`synthesizer are unitarily formed (Patridge, Fig. 15A-15E).
`
`

`

`Application/Control Number: 12/809,126
`
`Page 13
`
`Art Unit: 2611
`
`At the time of the invention it would have been obvious to one of ordinary skill in
`
`the art to modify Lee in view of Saka teachings by using a reference oscillator
`
`and frequency synthesizer which are unitarily formed in the circuit of Saka, as
`
`taught by Patridge.
`
`The motivation would be to provide an improved frequency adjustment circuitry,
`
`as taught by Patridge.
`
`24.
`
`Claim 14, rejected under 35 U.S.C. 103(a) as being unpatentable over
`
`Lee (US PG PUB 2006/0068720 A1) and further in view of Saka (US Patent
`
`5,483,686)
`
`25.
`
`As per claim 14, Lee further discloses a frequency synthesizer for
`
`receiving a frequency compensation signal and a reference oscillation signal, and
`
`for outputting a first signal and a second signal, the reference oscillation signal
`
`having a varying frequency (Lee, Fig. 2), said frequency synthesizer comprising a
`
`phase locked loop (PLL) circuit (Lee, Fig. 2:220) which includes:
`
`a oscillator for generating the first signal based on the reference oscillation signal
`
`(Lee, Fig. 2210220); and
`
`a frequency divider/multiplier for generating the second signal by frequency-
`
`dividing or frequency-multiplying the first signal from said PLL circuit (Lee, Fig.
`
`2:200:242),
`
`a frequency divider for dividing a frequency of the second signal by a frequency-
`
`division rate (Lee, paragraph 13); and
`
`

`

`Application/Control Number: 12/809,126
`
`Page 14
`
`Art Unit: 2611
`
`wherein the varying frequency of the first signal generated by said PLL circuit is
`
`compensated by the frequency compensation signal (Lee, Fig. 2:220, and
`
`paragraph 13),
`
`Lee does not explicitly disclose a phase comparator for outputting a signal
`
`corresponding to a phase difference between the reference oscillation signal and
`
`the second signal divided by the frequency divider,
`
`wherein the oscillator generates the first signal having a frequency based on the
`
`phase difference, and wherein the frequency divider compensates the frequency
`
`of the first signal by controlling the frequency-division rate based on the
`
`frequency compensation signal.
`
`Saka discloses a phase comparator for outputting a signal corresponding to a
`
`phase difference between the reference oscillation signal and the second signal
`
`divided by the frequency divider (Saka, Fig. 1:106),
`
`wherein the oscillator generates the first signal having a frequency based on the
`
`phase difference (Saka, Fig. 1 :106:103), and wherein the frequency divider
`
`compensates the frequency of the first signal by controlling the frequency-
`
`division rate based on the frequency compensation signal (Saka, Fig.
`
`104:106:110).
`
`At the time of the invention it would have been obvious to one of ordinary skill in
`
`the art to modify Lee teachings by generating a signal based on the phase
`
`difference, as taught by Saka.
`
`The motivation would be to stabilize the synchronization acquisition operation, as
`
`taught by Saka.
`
`

`

`Application/Control Number: 12/809,126
`
`Page 15
`
`Art Unit: 2611
`
`Conclusion
`
`26.
`
`Applicant's amendment necessitated the new ground(s) of rejection
`
`presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL.
`
`See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as
`
`set forth in 37 CFR1.136(a).
`
`A shortened statutory period for reply to this final action is set to expire
`
`THREE MONTHS from the mailing date of this action.
`
`In the event a first reply is
`
`filed within TWO MONTHS of the mailing date of this final action and the advisory
`
`action is not mailed until after the end of the THREE-MONTH shortened statutory
`
`period, then the shortened statutory period will expire on the date the advisory
`
`action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be
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`calculated from the mailing date of the advisory action.
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`In no event, however, will
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`the statutory period for reply expire later than SIX MONTHS from the date of this
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`final action.
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`Any inquiry concerning this communication or earlier communications from
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`the examiner should be directed to SYED HAIDER whose telephone number is
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`(571)270-5169. The examiner can normally be reached on Monday thru Friday
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`8:00 AM to 5:00 PM EST.
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`lf attempts to reach the examiner by telephone are unsuccessful, the
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`examiner’s supervisor, David Payne can be reached on 571 -272-3024. The fax
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`phone number for the organization where this application or proceeding is
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`assigned is 571-273-8300.
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`

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`Application/Control Number: 12/809,126
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`Page 16
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`Art Unit: 2611
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`Information regarding the status of an application may be obtained from
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`/S. H./
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`Examiner, Art Unit 2611
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`/David C. Payne/
`Supervisory Patent Examiner, Art Unit 2611
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`