vs! “111%
`\.\_:
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMIVHSSIONER FOR PATENTS
`PO. Box 1450
`Alexandria1 Virginia 22313-1450
`wwwusptogov
`
`
`
`
`
`14/449,922
`
`08/01/2014
`
`Ryutaro OKE
`
`20326.0065USW1
`
`2307
`
`08’01’20” —HAMRE, SCHUMANN,MUELLER&LARSONP.C. m
`7590
`53148
`45 South Seventh Street
`SHEN, YUZHEN
`Suite 2700
`MINNEAPOLIS, MN 55402- 1683
`
`PAPER NUMBER
`
`ART UNIT
`2691
`
`NOTIFICATION DATE
`
`DELIVERY MODE
`
`08/01/2017
`
`ELECTRONIC
`
`Please find below and/0r attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above—indicated "Notification Date" to the
`following e—mail address(es):
`PTOMail @hsml.com
`
`PTOL—90A (Rev. 04/07)
`
`

`

`
`
`Applicant(s)
`Application No.
` 14/449,922 OKE ET AL.
`
`
`AIA (First Inventor to File)
`Art Unit
`Examiner
`Office Action Summary
`
`
`StatusNo YUZHEN SHEN 2691
`-- The MAILING DA TE of this communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE g MONTHS FROM THE MAILING DATE OF
`THIS COMMUNICATION.
`Extensions of time may be available under the provisions of 37 CFR1. 136( a).
`after SIX () MONTHS from the mailing date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any
`earned patent term adjustment. See 37 CFR 1 .704(b).
`
`In no event, however, may a reply be timely filed
`
`Status
`
`1)IZI Responsive to communication(s) filed on 05/08/2017.
`El A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/were filed on
`
`2b)|:l This action is non-final.
`2a)|Z| This action is FINAL.
`3)I:I An election was made by the applicant in response to a restriction requirement set forth during the interview on
`
`; the restriction requirement and election have been incorporated into this action.
`
`4)|:| Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`
`closed in accordance with the practice under Exparte Quay/e, 1935 CD. 11, 453 O.G. 213.
`
`Disposition of Claims*
`
`5)IZI CIaim(s)1;8is/are pending in the application.
`5a) Of the above claim(s) 1,2 and 4 is/are withdrawn from consideration.
`
`is/are allowed.
`6)I:I Claim(s)
`
`7)|Z| Claim(s)_3 and 5-8 is/are rejected.
`8)|:| Claim(s)_ is/are objected to.
`
`
`are subject to restriction and/or election requirement.
`9)I:I Claim((s)
`* If any claims have been determined allowable, you may be eligible to benefit from the Patent Prosecution Highway program at a
`
`participating intellectual property office for the corresponding application. For more information, please see
`hit
`I/'/\WIIW.USOI.O. ovI’ atentS/init events/
`
`
`
`iindex.‘s or send an inquiry to PPI-iieedback{®usgtc.00v.
`
`Application Papers
`
`10)I:l The specification is objected to by the Examiner.
`11)I:l The drawing(s) filed on
`is/are: a)I:I accepted or b)I:I objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`
`12)I:| Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
`Certified copies:
`
`a)I:l All
`
`b)|:l Some” c)I:l None of the:
`
`1.I:I Certified copies of the priority documents have been received.
`2.|:l Certified copies of the priority documents have been received in Application No.
`3.|:| Copies of the certified copies of the priority documents have been received in this National Stage
`
`application from the International Bureau (PCT Rule 17.2(a)).
`** See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`
`
`3) D Interview Summary (PTO-413)
`1) E Notice of References Cited (PTO-892)
`Paper No(s)/Mai| Date.
`.
`.
`4) I:I Other'
`2) I] InformatIon DIsclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`Paper No(s)/Mai| Date
`US. Patent and Trademark Office
`PTOL—326 (Rev. 11-13)
`
`Office Action Summary
`
`Part of Paper No./Mai| Date 20170607
`
`

`

`Application/Control Number: 14/449,922
`
`Art Unit: 2691
`
`Page 2
`
`Detailed Action
`
`1.
`
`The present application is being examined under the pre-AIA first
`
`to invent
`
`provisions.
`
`Response to Amendment
`
`2.
`
`The Amendment filed on 05/08/2017 has been entered. Claim 3 is amended.
`
`Claims 1-8 remain pending in the application.
`
`Claim Rejections - 35 USC § 103
`
`3.
`
`The following is a quotation of 35 U.S.C. 103 which forms the basis for all
`
`obviousness rejections set forth in this Office action:
`
`A patent for a claimed invention may not be obtained, notwithstanding that
`
`the claimed invention is not identically disclosed as set forth in section 102
`
`if the differences between the claimed invention and the prior
`of this title,
`art are such that the claimed invention as a whole would have been
`
`obvious before the effective filing date of the claimed invention to a person
`
`having ordinary skill
`
`in the art to which the claimed invention pertains.
`
`Patentability shall not be negated by the manner in which the invention
`was made.
`
`4.
`
`Claims 3 and 5-8 are rejected under 35 U.S.C. 103 as unpatentable over Ooishi
`
`(us 20100309108 A1) in view of Jang (us 20070229433 A1).
`
`

`

`Application/Control Number: 14/449,922
`
`Art Unit: 2691
`
`Page 3
`
`Regarding claim 3, Ooishi (Figs. 1- 4) discloses a liquid crystal display device,
`
`comprising:
`
`video lines (Fig. 1; data lines DLHs and DLLs), which are provided in each of a
`
`plurality of display regions (Fig. 1; display regions DAH and DAL) obtained by
`
`horizontally dividing a screen (Fig. 1; display screen is horizontally divided to
`
`include display regions DAH and DAL) including a plurality of pixels arranged in
`
`matrix (Fig. 1 and [0028]; gate lines GLs intersect with data lines DLs and form
`
`pixels in matrix, Fig. 2 shows an example of one pixel), so as to correspond to
`
`respective columns of the plurality of pixels (Figs. 1-2; data lines DLs correspond to
`
`columns of the pixels as shown in Fig. 2);
`
`scanning lines (Figs. 1-2; gate lines GLs) provided so as to correspond to
`
`respective rows of the plurality of pixels (Figs. 1-2; gate lines GLs correspond to
`
`rows of the pixels as shown in Fig. 2);
`
`a thin film transistor (Fig. 2; transistor TFT; [0029]), provided in each of the
`
`plurality of pixels (Fig. 2; each pixel includes a transistor TFT) and, that controls
`
`conduction (Fig. 2 and [0029]; transistor TFT is switched on and in conduction
`
`state when a gate voltage is applied to gate line GL) between a pixel electrode (Fig.
`
`2 and [0029]; pixel electrode PX) and corresponding one of the video lines (Fig. 2 and
`
`[0029]; data line DL) based on a voltage applied to corresponding one of the scanning
`
`lines (Fig. 2 and [0029]; transistor TFT is switched on and in conduction state
`
`when a gate voltage is applied to gate line GL);
`
`

`

`Application/Control Number: 14/449,922
`
`Art Unit: 2691
`
`Page 4
`
`a scanning line drive circuit (Fig. 1; vertical drive circuit YDV; [0026] and
`
`[0031]) configured to sequentially apply a selection voltage ([0031] teaches vertical
`
`drive circuit YDV includes two vertical drive circuits YVD for the upper display
`
`region DAH and the lower display region DAL; [0034] teaches each vertical drive
`
`circuit YDV sequentially supply a gate signal to gate lines GLs; Fig. 4 shows an
`
`example that each vertical drive circuit YDV sequentially supply a gate signal to
`
`gate lines GLs) for passing electricity through the thin film transistor (Figs. 1-2;
`
`transistor TFT is turned on to conduct electricity) to a plurality of the scanning lines
`
`provided in each of the plurality of display regions (Figs. 1 and 4; gate lines GL1 -GLm
`
`are in the upper display region DAH and gate lines GLm+1-GL2m are in the lower
`
`display region DAL),
`
`to thereby perform vertical scanning of the plurality of display
`
`regions in parallel (Fig. 1 and 4 and [0031]; vertical drive circuit YDV includes two
`
`vertical drive circuits YVD to drive the gate lines GL1-GLm in the upper display
`
`region DAH and the gate lines GLm+1 —GL2m in the lower display region DAL in
`
`parallel); and
`
`a video line drive circuit (Fig. 1; data line drive circuit XDVL) configured to:
`
`apply, during an effective scanning period of the vertical scanning (Fig. 4; data writing
`
`period TWL; [0034]), a signal voltage (Figs. 2 and 4 and [0034]; data voltage signal)
`
`corresponding to a pixel value (Figs. 2 and 4 and [0034]; data voltage corresponds
`
`to pixel voltage applied to pixel electrode PX) via one of the video lines (Figs. 1, 2
`
`and 4 and [0034]; data lines DLs) to corresponding one of the plurality of pixels (pixel
`
`as shown in Fig. 2; [0034]) in a selected row (Figs. 1, 2 and 4 and [0034]; a row of
`
`

`

`Application/Control Number: 14/449,922
`
`Art Unit: 2691
`
`Page 5
`
`pixels is selected when a corresponding gate voltage is applied to turn on
`
`transistor TFT) that is applied with the selection voltage (Figs. 1, 2 and 4 and [0034];
`
`gate voltage supplied from vertical drive circuit YDV) via one of the scanning lines
`
`(Figs. 1, 2 and 4 and [0034]; gate line GL), the liquid crystal display device being
`
`configured to divisionally drive the screen (Figs. 1 and 4 and [0031]; vertical drive
`
`circuit YDV includes two vertical drive circuits YVD to divisionally drive the gate
`
`lines GL1 -GLm in the upper display region DAH and the gate lines GLm+1 —GL2m
`
`in the lower display region DAL),
`
`wherein the scanning line drive circuit (Fig. 1; vertical drive circuit YDV; [0026]
`
`and [0031])
`
`is configured to start the vertical scanning for a specific scanning display
`
`region (Figs. 1 and 4; e.g., lower display region DAL, including gate lines GLm+1—
`
`GL2m, vertical scanning is started from gate line GLm) predetermined out of the
`
`plurality of display regions (Figs. 1 and 4; the upper display region DAH and the
`
`lower display region DAL)
`
`from a pixel
`
`row (Figs.
`
`1 and 4; m+1-th pixel row
`
`corresponding to GLm+1) that is adjacent to another of the plurality of display regions
`
`(Figs. 1 and 4; m+1-th pixel row corresponding to GLm+1 is adjacent to the
`
`display region DAH);
`
`Ooishi (Figs. 1-2 and 4 and [0034]) discloses, during the effective scanning period, a
`
`selection voltage is applied to the thin film transistor in a selected row (e.g., a gate
`
`voltage is applied to gate line G1 through a switching TFT) and a selection voltage
`
`is applied to the thin film transistor in a subsequent selected row (e.g., a gate voltage
`
`

`

`Application/Control Number: 14/449,922
`
`Art Unit: 2691
`
`Page 6
`
`is applied to gate line G2 through a switching TFT), but does not disclose wherein a
`
`maximum value of the selection voltage that is applied to the thin film transistor in a
`
`selected row at a head of the effective scanning period is higher than a subsequent
`
`maximum value of a selection voltage that is applied to the thin film transistor in a
`
`subsequent selected row. However, Jang (Figs. 2-3 and 6-7) discloses a liquid crystal
`
`display device, wherein a maximum value of the selection voltage (gate voltage Vout1
`
`has a maximum value of Vamp1; [0044] and [0055]) that is applied to the thin film
`
`transistor in a selected row (gate voltage Vout1 is applied to gate line G1 through
`
`switching element formed of TFT; [0044] and [0054]-[0055] and [0005]) at a head of
`
`the effective scanning period (Figs. 3 and 7 show effective scanning period) is higher
`
`than a subsequent maximum value of a selection voltage (gate voltage Vout2 has a
`
`maximum value of Vamp2; [0044] and [0055]) that is applied to the thin film transistor
`
`in a subsequent selected row (gate voltage Vout2 is applied to gate line G2 through
`
`switching element formed of TFT, Vamp1>Vamp2; [0044] and [0055]). Therefore, it
`
`would have been obvious to one skilled in the art at the effective filing date of the
`
`claimed invention to incorporate the teaching from Jang on gate signal driving to the
`
`display device as taught by Ooishi. The combination/motivation would be to provide a
`
`display device capable of decreasing a luminance difference between adjacent pixels by
`
`modulating pulse amplitude of gate pulses supplied to respective gate lines (Jang,
`
`[0010]).
`
`

`

`Application/Control Number: 14/449,922
`
`Art Unit: 2691
`
`Page 7
`
`Regarding claim 5, Ooishi
`
`in view of Jang discloses the liquid crystal display
`
`device according to claim 3, Ooishi (Figs. 1- 4) further discloses wherein the plurality of
`
`display regions (Figs. 1 and 4; the upper display region DAH and the lower display
`
`region DAL)
`
`includes an upper display region (Figs.
`
`1 and 4; the upper display
`
`region DAH) and a lower display region (Figs. 1 and 4; the lower display region
`
`DAL) which are aligned in a vertical direction (Figs. 1 and 4; vertical direction), the
`
`lower display region being the specific scanning display region (Figs. 1 and 4; e.g.,
`
`lower display region DAL, including gate lines GLm+1—GL2m, vertical scanning is
`
`started from gate line GLm), and wherein the scanning line drive circuit (Fig. 1 and 4
`
`and [0031]; vertical drive circuit YDV includes two vertical drive circuits YVD to
`
`drive the gate lines GL1 -GLm in the upper display region DAH and the gate lines
`
`GLm+1—GL2m in the lower display region DAL in parallel) is configured to start the
`
`vertical scanning for the upper display region (Figs. 1 and 4; the upper display region
`
`DAH) from a pixel row (Fig. 1 and 4; pixel row associated with a gate line of GL1-
`
`GLm (e.g., G1) in the upper display region DAH) located opposite to the specific
`
`scanning display region (Fig. 1 and 4; the lower display region DAL, corresponding
`
`to gate lines GLm+1—GL2m).
`
`Regarding claim 6, Ooishi
`
`in view of Jang discloses the liquid crystal display
`
`device according to claim 3. Ooishi (Figs. 1- 4) further discloses wherein the video line
`
`drive circuit (Fig. 1; data line drive circuit XDVL) is configured to apply, during a
`
`blanking period of the vertical scanning (Fig. 4; vertical blanking period TBL; [0034]),
`
`

`

`Application/Control Number: 14/449,922
`
`Art Unit: 2691
`
`Page 8
`
`a predetermined reference voltage to the video lines (Fig. 4 and [0034]; pre-data
`
`signal, which has the same potential as the data signal in the m-th row).
`
`Regarding claim 7, Ooishi
`
`in view of Jang discloses the liquid crystal display
`
`device according to claim 3. Ooishi (Figs. 1- 4) further discloses wherein the scanning
`
`line drive circuit (Fig. 1; vertical drive circuit YDV; [0026] and [0031]) is configured to
`
`control,
`
`in at least the specific scanning display region (Figs. 1 and 4; e.g., lower
`
`display region DAL,
`
`including gate lines GLm+1—GL2m) out of the plurality of
`
`display regions (Figs. 1 and 4; the upper display region DAH and the lower display
`
`region DAL),
`
`the selection voltage (Figs. 1-2 and 4; gate voltage supplied from
`
`vertical drive circuit YDV) so that the thin film transistor (Fig. 2; transistor TFT;
`
`[0029]) in a selected row at a head of the effective scanning period (Figs. 1-2 and 4;
`
`m+1-th pixel row corresponding to GLm+1 is at the head or front of the data
`
`writing period TWL) enters a conductive state (Figs. 1-2 and 4; transistor TFT of
`
`m+1-th pixel
`
`row is turned on, corresponding to a conductive state) with a
`
`resistance lower than a resistance of a selected row subsequent thereto (Figs. 1-2 and
`
`4; transistors TFT corresponding to m+1-th pixel row to 2m-th pixel row are
`
`sequentially turned on, when the m+1-th pixel row is selected and in a conductive
`
`state, the subsequent m+2-th pixel row is not selected and in a non-conductive
`
`state and corresponding resistance is infinitely high,
`
`i.e., V=Rl, nonconductive
`
`state corresponds to I: 0 and R is infinitive; therefore, the conductive m+1-th
`
`

`

`Application/Control Number: 14/449,922
`
`Art Unit: 2691
`
`Page 9
`
`pixel row has a resistance lower than that of the subsequent non-conductive
`
`m+2-th pixel row).
`
`Regarding claim 8, Ooishi
`
`in view of Jang discloses the liquid crystal display
`
`device according to claim 3. Ooishi (Figs. 1-2 and 4) discloses wherein each selection
`
`voltage which is applied to the thin film transistor in a selected row during the effective
`
`scanning period is a single pulse voltage (Fig. 4 shows an example that each gate
`
`pulse applied to a corresponding gate line is a single pulse).
`
`In addition, Jang
`
`(Figs. 2-3 and 6-7) also discloses wherein each selection voltage which is applied to
`
`the thin film transistor in a selected row during the effective scanning period is a single
`
`pulse voltage (Figs. 3 and 7 show examples that each gate pulse Vout applied to a
`
`corresponding gate line is a single pulse). Therefore, it would have been obvious to
`
`one skilled in the art at the effective filing date of the claimed invention to incorporate
`
`the teaching from Jang on gate signal driving to the display device as taught by Ooishi.
`
`The combination/motivation would be to provide a display device capable of decreasing
`
`a luminance difference between adjacent pixels by modulating pulse amplitude of gate
`
`pulses supplied to respective gate lines (Jang, [0010]).
`
`Response to Arguments
`
`5.
`
`Applicant’s arguments have been considered but are moot because the
`
`arguments do not apply to the reference being used in the current rejection.
`
`In view of
`
`

`

`Application/Control Number: 14/449,922
`
`Art Unit: 2691
`
`Page 10
`
`amendment, the new reference of Jang (US 20070229433 A1) has been used for new
`
`ground of rejection.
`
`Conclusion
`
`Applicant's amendment necessitated the new ground(s) of rejection presented in
`
`this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a).
`
`Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
`
`A shortened statutory period for reply to this final action is set to expire THREE
`
`MONTHS from the mailing date of this action.
`
`In the event a first reply is filed within
`
`TWO MONTHS of the mailing date of this final action and the advisory action is not
`
`mailed until after the end of the THREE-MONTH shortened statutory period, then the
`
`shortened statutory period will expire on the date the advisory action is mailed, and any
`
`extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of
`
`the advisory action.
`
`In no event, however, will the statutory period for reply expire later
`
`than SIX MONTHS from the date of this final action.
`
`Inquiry
`
`Any inquiry concerning this communication or earlier communications from the
`
`examiner should be directed to YUZHEN SHEN whose telephone number is (571)272-
`
`1407. The examiner can normally be reached on Monday-Thursday 8:30am-5:00pm.
`
`

`

`Application/Control Number: 14/449,922
`
`Art Unit: 2691
`
`Page 11
`
`If attempts to reach the examiner by telephone are unsuccessful, the examiner’s
`
`supervisor, Chanh Nguyen can be reached on 571-272-7772. The fax phone number
`
`for the organization where this application or proceeding is assigned is 571 -273-8300.
`
`Information regarding the status of an application may be obtained from the
`
`Patent Application Information Retrieval
`
`(PAIR)
`
`system.
`
`Status information for
`
`published applications may be obtained from either Private PAIR or Public PAIR.
`
`Status information for unpublished applications is available through Private PAIR only.
`
`For more information about the PAIR system, see http://pair-direct.uspto.gov. Should
`
`you have questions on access to the Private PAIR system, contact the Electronic
`
`Business Center (EBC) at 866-217-9197 (toll-free).
`
`If you would like assistance from a
`
`USPTO Customer Service Representative or access to the automated information
`
`system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
`
`/YUZH EN SHEN/
`
`Examiner, Art Unit 2691
`
`