UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`PO. Box 1450
`Alexandria, Virginia 2231371450
`www.uspto.gov
`
`15/240,305
`
`08/18/2016
`
`Masatoshi UENO
`
`HOKUP0327US
`
`5340
`
`MARK D. SARALINO (PAN)
`RENNER, OTTO, BOISSELLE & SKLAR, LLP
`1621 EUCLID AVENUE
`19TH FLOOR
`CLEVELAND, OH 44115
`
`YESILDAG LAURA G
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`ART UNIT
`2844
`
`PAPER NUMBER
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`NOTIFICATION DATE
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`DELIVERY MODE
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`01/25/2019
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`ELECTRONIC
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`Please find below and/or attached an Office communication concerning this application or proceeding.
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`The time period for reply, if any, is set in the attached communication.
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`Notice of the Office communication was sent electronically on above—indicated "Notification Date" to the
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`following e—mail address(es):
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`ipdoeket@rennerotto.eom
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`PTOL-90A (Rev. 04/07)
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`

`

`Off/09 A0170” Summary
`
`Application No.
`15/240,305
`Examiner
`LAURA YESILDAG
`
`Applicant(s)
`UENO etal.
`Art Unit
`2844
`
`AIA Status
`Yes
`
`- The MAILING DA TE of this communication appears on the cover sheet wit/7 the correspondence address -
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE g MONTHS FROM THE MAILING
`DATE OF THIS COMMUNICATION.
`Extensions of time may be available under the provisions of 37 CFR 1.136(a). In no event, however, may a reply be timely filed after SIX (6) MONTHS from the mailing
`date of this communication.
`|f NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any earned patent term
`adjustment. See 37 CFR 1.704(b).
`
`Status
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`1). Responsive to communication(s) filed on 10/22/2018.
`[:1 A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/were filed on
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`2a). This action is FINAL.
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`2b) C] This action is non-final.
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`3)[:] An election was made by the applicant in response to a restriction requirement set forth during the interview on
`; the restriction requirement and election have been incorporated into this action.
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`4)[:] Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Expat/7e Quay/e, 1935 CD. 11, 453 O.G. 213.
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`Disposition of Claims*
`5)
`Claim(s)
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`1—12 is/are pending in the application.
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`5a) Of the above claim(s) fl is/are withdrawn from consideration.
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`E] Claim(s)
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`is/are allowed.
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`Claim(s) fl is/are rejected.
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`E] Claim(s) _ is/are objected to.
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`) ) ) )
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`6 7
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`8
`
`
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`are subject to restriction and/or election requirement
`[:1 Claim(s)
`9
`* If any claims have been determined allowable, you may be eligible to benefit from the Patent Prosecution Highway program at a
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`participating intellectual property office for the corresponding application. For more information, please see
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`http://www.uspto.gov/patents/init events/pph/index.'sp or send an inquiry to PPeredback@uspto.gov.
`
`Application Papers
`10):] The specification is objected to by the Examiner.
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`11):] The drawing(s) filed on
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`is/are: a)C] accepted or b)E] objected to by the Examiner.
`
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`12)C] Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
`Certified copies:
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`a)C] All
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`b)C] Some”
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`c)C] None of the:
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`1C] Certified copies of the priority documents have been received.
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`2C] Certified copies of the priority documents have been received in Application No.
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`3.[:] Copies of the certified copies of the priority documents have been received in this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
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`** See the attached detailed Office action for a list of the certified copies not received.
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`Attachment(s)
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`1)
`
`Notice of References Cited (PTO-892)
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`2) E] Information Disclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`Paper No(s)/Mail Date_
`U.S. Patent and Trademark Office
`
`3) C] Interview Summary (PTO-413)
`Paper No(s)/Mail Date
`4) CI Other-
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`PTOL-326 (Rev. 11-13)
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`Office Action Summary
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`Part of Paper No./Mai| Date 20181126
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`

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`Application/Control Number: 15/240,305
`Art Unit: 2844
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`Page 2
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`DETAILED ACTION
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`The present application, filed on or after March 16, 2013, is being examined under the
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`first inventor to file provisions of the AIA.
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`Foreign Priority
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`The present application claims the benefit of priority of japanese Patent Application No,
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`2015179032, filed on September 11, 2015, which is acknowledged.
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`However, Applicant cannot rely upon the certified copies of foreign priority papers
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`because a certified English translation of said papers has not been made of record in accordance
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`with 37 CFR 1.55. See MPEP §§ 215 and 216.
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`Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)—
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`(d), a certified English translation of the foreign application must be submitted in reply to this
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`action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in
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`no benefit being accorded for the non—English application.
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`Claim Rejections - 35 USC § 103
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`The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness
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`rejections set forth in this Office action:
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`A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention
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`is not identically disclosed as set forth in section 102 of this title, if the differences between the
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`claimed invention and the prior art are such that the claimed invention as a whole would have
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`been obvious before the effective filing date of the claimed invention to a person having ordinary
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`skill in the art to which the claimed invention pertains. Patentability shall not be negated by the
`manner in which the invention was made.
`
`
`Note: In the event the determination of the status of the application as subject to AIA 35 U.S.C.
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`102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory
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`

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`Application/Control Number: 15/240,305
`Art Unit: 2844
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`Page 3
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`basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and
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`the rationale supporting the rejection, would be the same under either status.
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`Claims 1-5 are re'ected under 35 U.S.C. 103 as bein
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`un atentable over Ara ai
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`I US
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`2013 0214592 in view of Ara ai
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`II US 2013 0062936 in further view of Kami a US
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`201510001924).
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`Regarding claim 1, Aragai | discloses in Fig. 1 and Fig. 9 a lighting control device (power supply
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`control circuit 101) comprising: a controller (switching control circuit 111 including a CPU 121)
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`configured to output a control signal based on an indicating signal indicating whether to turn
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`on or off a light source of a vehicle ([0053—54] CPU 121 transmits control signal to issue an
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`instruction to electrically connect or disconnect power supply 102 from a load 103 based on a
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`reset signal, however when abnormality occurs [0202] the counter overflow exceedance occurs
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`and the reset signal is transmitted to the reset terminal of the CPU indicating abnormality); a
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`diagnosis circuit (monitor circuit 112) configured to output a M signal when detecting
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`irregular operation of the controller ([0056] monitor circuit 112 monitors existence or non—
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`existence of an abnormality ofthe CPU 121 or switching control circuit 111, when abnormality is
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`detected, the monitor circuit 112 transmits a reset signal to reset the state of the switching
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`control circuit when detecting abnormality of the switching control circuit or CPU); a latch circuit
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`(Fig. 10 latch 714; [0011] the switching part includes a relay or a combination of a latch IC and a
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`switching element) configured to set second signal in a first state until receiving the Msignal
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`and set the second signal in a second state when receiving the first signal ([0020] the first state
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`is a state in which the relay electrically connects the power supply to the load, and the second
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`state is a state in which the relay electrically disconnects the power supply from the load, [0181]
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`when input voltage at the reset terminal of the latch 714 becomes high, the disconnection
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`

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`Application/Control Number: 15/240,305
`Art Unit: 2844
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`Page 4
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`instruction signal is received and the latch 714 starts the disconnection state (second state) of
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`outputting the electric—power supply and transistor is turned off); and a logic circuit (switching
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`circuit 613) configured to receive the control signal, and the second signal (Fig. 9 control signal,
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`disconnection and connection signals, abnormal time connection instruction signal), the logic
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`circuit being configured to control the light source in accordance with the control signal while
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`the second signal is in the first state ([0160] switching circuit 613 can switch between the
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`connection state in which the power supply 102 is electrically connected to the load 103 and the
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`disconnection state in which the power supply 102 is electrically disconnected from the load,
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`[0020] the first state is a state in electrical connection of the power supply to the load, and the
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`second state is a state in electrical disconnection of the power supply from the load).
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`Although Aragai | teaches the logic circuit as recited above, Aragai | perhaps may not explicitly
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`specify that the logic circuit is configured to receive an ignition signal indicating whether a motor
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`of the vehicle is in an activated state or a rest state and further configured to control the light
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`source in accordance with the ignition signal while the second signal is in the second state.
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`Nonetheless, Aragai
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`|| explicitly discloses that the logic circuit configured to receive an
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`ignition signal indicating whether a motor of the vehicle is in an activated state or a rest state
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`([0084] CPU 232 detects the ON and OFF state of the ignition power source) and further
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`configured to control the light source in accordance with the ignition signal while the second
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`signal is in the second state ([0120] the CPU 232 controls the output of the lighting command
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`signal based on the state ofthe ignition power source IG providing input voltage signal and [0121]
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`the CPU 232 stops the output of the lighting command signal while the lighting command signal
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`is set to the low level state, while the off state (second state) of the ignition power source IG is
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`

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`Application/Control Number: 15/240,305
`Art Unit: 2844
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`Page 5
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`detected. Therefore, the headlight 213 is turned off. The CPU turns on the headlight 123 when
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`ON state of the ignition power source IG is detected and the lighting command signal is on high
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`level state, therefore the headlight 123 is lit and [0122] even if the CPU 232 has communication
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`failure, the ignition switch ofthe vehicle is set to the ignition to turn on the ignition power source
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`IG, which allows the headlight 213 to be lit).
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`Based on Aragai ||, one of ordinary skill in the art would have recognized that it is old and well
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`known to receive an ignition signal indicating whether a motor of the vehicle is in an activated
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`state or a rest state (on or off state) and further configured to control the light source in
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`accordance with the ignition signal being in a on or off state while the second signal is in a first
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`or second state.
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`Thus, prior to the effective filing date of the claimed invention, it would have been obvious
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`to one of ordinary skill in the art to recognize the benefit of modifying Aragai | by incorporating
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`the features taught by Aragai II in order to further enhance the logic circuit of Aragai I such that
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`”the vehicle load can surely be actuated even if communication failure is generated" and
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`”headlights can be lit during the running of the vehicle to ensure safe driving" (Aragai || [0022]
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`and [0122] respectively).
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`Furthermore, Kamiya explicitly specifies the amended claim 1 having a logic circuit configured
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`to control the load or light source in accordance with control signal while the second signal is in
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`the first state ([0018] and [0020]) and control the light or load in accordance with the ignition
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`signal while the second signal is in the second state ([0012—0013]).
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`Thus, prior to the effective filing date of the claimed invention, it would have been obvious
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`to one of ordinary skill in the art to recognize the benefit of modifying Aragai | by incorporating
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`

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`Application/Control Number: 15/240,305
`Art Unit: 2844
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`Page 6
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`the features taught Kamiya in order to further enhance the logic circuit of Aragai | to ”provide a
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`latching relay drive circuit used for a vehicle which, even when a trouble is caused to a control
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`signal output of a controller, enables to arbitrarily turn on and off the latching relay used for
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`turning on and off a load of a vehicle according to usage condition and the like of the load."
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`([0011]), thus, even when the trouble is caused to the control signal output of the controller of
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`the vehicle, the latching relay can be arbitrarily turned on or off [0014])..
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`Regarding claim 2, the combination prior art discloses lighting control device according to
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`claim 1, wherein the controller is configured in Fig.1 and 9 to set the control signal in a first state
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`when the indicating signal indicates turning on the light source (Aragai | [0008]), and set the
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`control signal in a second state when the indicating signal indicates turning off the light source
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`(Aragai | [0008]), and ignition signal is in a first state while the motor of the vehicle is in the
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`activated state; the ignition signal is in a second state while the motor ofthe vehicle is in the rest
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`state (Aragai || [0084]), the logic circuit is configured in Fig. l and 9 to turn on the light source
`
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`while the second signal is in the first state and the control signal is in the first state, turn off the
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`light source while the second signal is in the first state and the control signal is in the second state
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`(Aragai | [0009] and claim 6), turn on the light source while the second signal is in the second
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`state and the ignition signal is in the first state, and turn off the light source while the second
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`signal is in the second state and the ignition signal is in the second state (Aragai || [0121—122]).
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`Regarding claim 3, the combination prior art discloses that the latch circuit is configured to
`
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`set the second signal
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`in the first state when receiving a reset signal (Aragai
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`I; [0009] when
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`abnormality of the switching control circuit is detected, the reset signal is transmitted and the
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`

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`Application/Control Number: 15/240,305
`Art Unit: 2844
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`Page 7
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`third control signal which represents the abnormal time connection signal is transmitted to the
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`switching part/latch IC which sets the lighting signal to a first state and further [0012] and [0057])
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`and the controller (Fig. 1 switching control circuit 111 including a CPU 121) is configured to when
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`determining that the controller can communicate with a sender outputting the indicating signal
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`output reset signal (Fig. 1 and 9 and [0012] and [0104]) to the latch circuit (Fig. 10 latch 714) at a
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`timing of setting the control signal in either the first or second state (Aragai II; [0121—122] and
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`[0103]and[0208D.
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`Regarding claim 4, the combination prior art discloses that the latch circuit is configured to
`
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`set the second signal
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`in the first state when receiving a reset signal (Aragai
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`I; [0009] when
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`abnormality of the switching control circuit is detected, the reset signal is transmitted and the
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`third control signal which represents the abnormal time connection signal is transmitted to the
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`switching part/latch IC which sets the lighting signal to a first state and further [0012] and [0057])
`
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`and the controller (Fig. 1 switching control circuit 111 including a CPU 121) is configured to when
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`determining that the controller can communicate with a sender outputting the indicating signal
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`output reset signal (Fig. 1 and 9 and [0012] and [0104]) to the latch circuit (Fig. 10 latch 714) at a
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`timing of setting the ignition signal in either the first or second state (Aragai II; [0084] and [0121—
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`122]and[0103]and[0208D.
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`Regarding claim 5, the combination prior art discloses the latch circuit is configured to set
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`the second signal
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`in the first state when receiving a reset signal
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`(Aragai
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`I;
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`[0009] when
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`abnormality of the switching control circuit is detected, the reset signal is transmitted and the
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`

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`Application/Control Number: 15/240,305
`Art Unit: 2844
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`Page 8
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`third control signal which represents the abnormal time connection signal is transmitted to the
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`switching part/latch IC which sets the lighting signal to a first state and further [0012] and [0057])
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`and the controller (Fig. 1 switching control circuit 111 including a CPU 121) is configured to start
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`a process of periodically outputting the reset signal (Fig. 1 and 9 and [0012] and [0104]) to the
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`latch circuit (Fig. 10 latch 714) when determining that the controller can communicate with a
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`sender outputting the indicating signal ([0103] and [0208]).
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`Response to Amendment and Arguments
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`Applicant’s amendment and arguments have been acknowledged however does not
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`overcome the prior art since they are found to be unpersuasive.
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`Furthermore, Kamiya explicitly specifies the amended claim 1 having a logic circuit configured
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`to control the load or light source in accordance with control signal while the second signal is in
`
`the first state ([0018] and [0020]) and control the light or load in accordance with the ignition
`
`signal while the second signal is in the second state ([0012—0013]). Thus, prior to the effective
`
`filing date ofthe claimed invention, it would have been obvious to one of ordinary skill in the art
`
`to recognize the benefit of modifying Aragai | by incorporating the features taught Kamiya in
`
`order to further enhance the logic circuit of Aragai | to ”provide a latching relay drive circuit used
`
`for a vehicle which, even when a trouble is caused to a control signal output of a controller,
`
`enables to arbitrarily turn on and off the latching relay used for turning on and off a load of a
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`vehicle according to usage condition and the like ofthe load." [0011].
`
`

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`Application/Control Number: 15/240,305
`Art Unit: 2844
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`Page 9
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`Conclusion
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`THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant
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`is reminded of the
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`extension of time policy as set forth in 37 CFR 1.136(a).
`
`A shortened statutory period for reply to this final action is set to expire THREE MONTHS
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`from the mailing date ofthis action. In the event a first reply is filed within TWO MONTHS of the
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`mailing date of this final action and the advisory action is not mailed until after the end of the
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`THREE—MONTH shortened statutory period, then the shortened statutory period will expire on
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`the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be
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`calculated from the mailing date of the advisory action. In no event, however, will the statutory
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`period for reply expire later than SIX MONTHS from the date of this final action.
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`Any inquiry concerning this communication or earlier communications from the examiner
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`should be directed to LAURA YESILDAG whose telephone number is (571) 270—5066. Examiner
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`interviews
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`are
`
`available
`
`using
`
`the USPTO Automated
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`Interview Request
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`(AIR)
`
`at
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`http://www.uspto.gov/interviewpractice.
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`For sending Interview agendas, the Examiner’s direct fax number is (571) 270—6066.
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`Communications via Internet email are at
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`For
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`filing
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`Communication,
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`please
`
`see
`
`https://www.uspto.gov/sites/default/files/documents/sb0439.pdf.
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`

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`Application/Control Number: 15/240,305
`Art Unit: 2844
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`Page 10
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`The Examiner's Part—Time work schedule and general availability is typically 9:00 AM —
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`If attempts to reach the Examiner are unsuccessful, the Examiner’s Supervisor,
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`DOUGLAS W. OWENS can be reached at (571) 272—1662.
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`
`/Laww Ye/yl/Lotag/
`
`Patent Examiner, Art Unit 2844
`
`/JIMMY T VU/
`
`Primary Examiner, Art Unit 2844
`
`