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`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`PO. Box 1450
`Alexandria, Virginia 2231371450
`
`15/280,554
`
`09/29/2016
`
`Tetsuo FUKAMI
`
`20326.0086USOI
`
`7752
`
`53148
`
`759°
`
`09’1”)”
`
`HAMRE, SCHUMANN, MUELLER & LARSON RC.
`45 South Seventh Street
`Suite 2700
`
`MINNEAPOLIS, MN 55402-1683
`
`MATTHEWS” ANDREL
`
`ART UNIT
`2621
`
`PAPER NUMBER
`
`NOTIFICATION DATE
`
`DELIVERY MODE
`
`09/17/2019
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above—indicated "Notification Date" to the
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`following e—mail address(es):
`PTOMail@hsml.eom
`
`PTOL-90A (Rev. 04/07)
`
`

`

`0/7709 A0170” Summary
`
`Application No.
`15/280,554
`Examiner
`ANDRE L MATTH EWS
`
`Applicant(s)
`FUKAMI et al.
`Art Unit
`2621
`
`AIA (FITF) Status
`Yes
`
`- The MAILING DA TE of this communication appears on the cover sheet wit/7 the correspondence address -
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE g MONTHS FROM THE MAILING
`DATE OF THIS COMMUNICATION.
`Extensions of time may be available under the provisions of 37 CFR 1.136(a). In no event, however, may a reply be timely filed after SIX (6) MONTHS from the mailing
`date of this communication.
`|f NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any earned patent term
`adjustment. See 37 CFR 1.704(b).
`
`Status
`
`1). Responsive to communication(s) filed on 8/12/2019.
`[:1 A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/were filed on
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`2a)D This action is FINAL.
`
`2b)
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`This action is non-final.
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`3)[:] An election was made by the applicant in response to a restriction requirement set forth during the interview on
`; the restriction requirement and election have been incorporated into this action.
`
`4)[:] Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Expat/7e Quay/e, 1935 CD. 11, 453 O.G. 213.
`
`Disposition of Claims*
`5)
`Claim(s)
`
`1—6 and 13 is/are pending in the application.
`
`5a) Of the above claim(s)
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`is/are withdrawn from consideration.
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`E] Claim(s)
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`is/are allowed.
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`Claim(s) 1—6 and 13 is/are rejected.
`
`[:1 Claim(s) _ is/are objected to.
`
`) ) ) )
`
`6 7
`
`8
`
`
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`are subject to restriction and/or election requirement
`[j Claim(s)
`9
`* If any claims have been determined aflowabie. you may be eligible to benefit from the Patent Prosecution Highway program at a
`
`participating intellectual property office for the corresponding application. For more information, please see
`
`http://www.uspto.gov/patents/init events/pph/index.jsp or send an inquiry to PPeredback@uspto.gov.
`
`Application Papers
`10)[:] The specification is objected to by the Examiner.
`
`11). The drawing(s) filed on 9/29/2016 is/are: a). accepted or b)E] objected to by the Examiner.
`
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`12). Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
`Certified copies:
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`a). All
`
`b)D Some**
`
`C)D None of the:
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`1.. Certified copies of the priority documents have been received.
`
`2.[:] Certified copies of the priority documents have been received in Application No.
`
`3:] Copies of the certified copies of the priority documents have been received in this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`
`** See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`1) C] Notice of References Cited (PTO-892)
`
`Information Disclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`2)
`Paper No(s)/Mail Date_
`U.S. Patent and Trademark Office
`
`3) C] Interview Summary (PTO-413)
`Paper No(s)/Mail Date
`4) CI Other-
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`PTOL-326 (Rev. 11-13)
`
`Office Action Summary
`
`Part of Paper No./Mai| Date 20190912
`
`

`

`Application/Control Number: 15/280,554
`Art Unit: 2621
`
`Page 2
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`DETAILED ACTION
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`Notice of Pre-AIA or AIA Status
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`1.
`
`The present application, filed on or after March 16, 2013, is being examined
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`under the first inventor to file provisions of the AIA.
`
`Continued Examination Under 37 CFR 1. 1 14
`
`1.
`
`A request for continued examination under 37 CFR 1.114, including the fee set
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`forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this
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`application is eligible for continued examination under 37 CFR 1.114, and the fee set
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`forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action
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`has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on
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`7/18/2019 has been entered.
`
`Claim Rejections - 35 USC § 102
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`2.
`
`The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that
`
`form the basis for the rejections under this section made in this Office action:
`
`A person shall be entitled to a patent unless —
`(a)(2) the claimed invention was described in a patent issued under section 151, or in an
`application for patent published or deemed published under section 122(b), in which the
`patent or application, as the case may be, names another inventor and was effectively filed
`before the effective filing date of the claimed invention.
`
`3.
`
`Claims 1-4 and 13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated
`
`by Kawachi (US 2015/0029081).
`
`4.
`
`Regarding claim 1, Kawachi teaches A display device, comprising:
`
`a plurality of groups, each group having a plurality of data lines extending in a first
`
`direction (Fig. 2,11,19 data lines yn)and a plurality of gate lines extending in a
`
`

`

`Application/Control Number: 15/280,554
`Art Unit: 2621
`
`Page 3
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`second direction (Figs. 2, 11, 19 gate lies xn), wherein the plurality of gate lines for
`
`each group are adjacent in the first, direction (Fig. 4 [0072-0073] teach how scan lines
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`x are grouped to selection lines 61); a plurality of blocks, each block including: a
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`plurality of selector transistors and each of the plurality of selector transistors includes: a
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`first conductive electrode connected to an end of a corresponding gate line of the
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`plurality of gate lines, a second conductive electrode, and a control electrode (Figs. 4,
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`[0078] transistor 63 is connected to scan line 61x and selection lines 62), wherein
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`each block among the plurality of blocks corresponds to a group among the plurality of
`
`the groups (Fig. 4 groups are defined by TFTs connected to the same scan line 61x
`
`or the same selection line 62); a plurality of selection signal supplying wirings each of
`
`which is connected to the control electrode of each of the plurality of selector
`
`transistors for a corresponding block of the plurality of blocks (Fig. 4 selection lines 62
`
`are connected to transistors 63); a plurality of gate voltage supplying wirings each of
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`which is connected to the second conductive electrode of one of the plurality of selector
`
`transistors in each of the groups(Fig. 4 groups are defined by TFTs connected to the
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`scan line 61x and selection line 62); and a gate driver that sequentially supplies a
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`gate voltage to the plurality of gate voltage supplying wirings and supplies a control
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`voltage to the plurality of selection signal supplying wirings to turn on or off one or more
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`of the plurality of selector transistors([0082]) wherein the plurality of selector transistors
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`for each block are adjacent in the first direction(vertical) and at least partially overlap
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`when viewed in the first direction (Fig. 4 shows selector transistors 63 adjacently
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`disposed in a first direction and where groups of transistors partially overlapping
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`transistors in the same group and adjacent groups).
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`

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`Application/Control Number: 15/280,554
`Art Unit: 2621
`
`Page 4
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`Regarding claim 2, Kawachi teaches wherein a first block and a second block among
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`the plurality of blocks are sequentially arranged in a scanning direction(Fig. 4 groups
`
`are defined by TFTs connected to the same scan line 61x or the same selection
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`line 62 and shows groups sequentially arranged), and the light shielding part is
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`disposed between a selector transistor connected to a gate line scanned last in the first
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`block and a selector transistor connected to a gate line scanned first in the second
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`block([0094] teaches the scanning lines 61 can act as light-blocking to inhibit light
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`transmission to the color filter substrate).
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`Regarding claim 3, Kawachi teaches wherein the control electrodes for each of
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`the plurality of selector transistors included in a block among the plurality of blocks are
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`integrally formed (Fig. 4 groups are defined by TFT electrodes connected to the
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`same scan line 61x or the same selection line 62 and shows groups sequentially
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`arranged).
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`Regarding claim 4, Kawachi teaches wherein the light shielding part is an
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`extended part of the control electrode of a selector transistor among the plurality of
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`selector transistors([0094] teaches the scanning lines 61 can act as light-blocking
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`to inhibit light transmission to the color filter substrate. Scanning lines extended
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`from electrodes).
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`Regarding claim 13, Kawachi a light shielding part that is disposed between at
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`least two adjacent blocks among the plurality of blocks ([0094] teaches the scanning
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`lines 61 can act as light-blocking to inhibit light transmission to the color filter
`
`substrate)
`
`

`

`Application/Control Number: 15/280,554
`Art Unit: 2621
`
`Page 5
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`Claim Rejections - 35 USC § 103
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`5.
`
`The following is a quotation of 35 U.S.C. 103 which forms the basis for all
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`obviousness rejections set forth in this Office action:
`
`A patent for a claimed invention may not be obtained, notwithstanding that the claimed
`invention is not identically disclosed as set forth in section 102, if the differences between the
`claimed invention and the prior art are such that the claimed invention as a whole would have
`been obvious before the effective filing date of the claimed invention to a person having
`ordinary skill in the art to which the claimed invention pertains. Patentability shall not be
`negated by the manner in which the invention was made.
`
`6.
`
`Claims 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over
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`Kawachi (US 2015/0029081) in view of Yuminami (2016/0070130).
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`7.
`
`Regarding claim 5, Kawachi teaches the limitations as discussed above and also
`
`teaches a light blocking function of a scan line, but fails to teach wherein the light
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`shielding part includes a dummy transistor that has a control electrode, and the control
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`electrode of each of the plurality of selector transistors included in a first block among
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`the plurality of blocks and the control electrode of the dummy transistor adjacent to the
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`first block are integrally formed.
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`However in the same field of disposing light blocking elements in a display device
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`Yuminami teaches wherein the light shielding part includes a dummy transistor that has
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`a control electrode, and the control electrode of each of the plurality of selector
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`transistors included in a first block among the plurality of blocks and the control
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`electrode of the dummy transistor adjacent to the first block are integrally formed (Figs.
`
`6-7 [0078] teaches a dummy gate line 31a (i.e. scanning line) connected to a
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`dummy TFT of a dummy pixel having light blocking properties disposed in the
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`non-display area of the panel. Fig. 7 shows the plurality of dummy pixels 31 along
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`

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`Application/Control Number: 15/280,554
`Art Unit: 2621
`
`Page 6
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`the same dummy gate line 31 a, therefore the control electrodes of the TFT are
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`integrally (as a whole) formed by this identical connection).
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`Therefore it would have been obvious to one of ordinary skill at the time of the
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`effective filing date to combine the light blocking method as taught by Kawachi with the
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`light blocking method as taught by Yuminami. This combination would provide a display
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`that reduce shadow and improve appearances of the panel as taught by Yuminami
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`[00051
`
`Regarding claim 6, Yuminami teaches wherein the dummy transistor includes a
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`first conductive electrode and a second conductive electrode (dummy TFT of dummy
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`pixel 31), wherein each of the plurality of selection signal supplying wirings is not
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`connected to the first conductive electrode and the second conductive electrode of the
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`dummy transistor (dummy gate line 31a connected to dummy TFT. This well known
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`the gate line is connected to gate electrode), and wherein each of the plurality of
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`gate voltage supplying wirings (regular gate lines 19) is not connected to the first
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`conductive electrode and the second conductive electrode of the dummy transistor (Fig.
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`7 and [0078] show dummy pixels 31 connected to dummy gate lines 31a and not
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`pixel gate lines 19).
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`Response to Arguments
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`8.
`
`Applicant's arguments filed 7/18/2019 have been fully considered but they are
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`not persuasive. In the remarks submitted that Applicant has argued the prior art fails to
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`teach the limitations of claim 1 as previously presented. Specifically the Applicant has
`
`argued Kawachi does not teach the structure of claim 1 because Kawachi does not
`
`teach the plurality of selector transistors for each block group are adjacent in the first
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`

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`Application/Control Number: 15/280,554
`Art Unit: 2621
`
`Page 7
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`direction because the selector transistor for each block are offset in the first direction
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`and the selector transistors do not at least partially overlap when viewed in the first
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`direction. The Examiner respectfully disagrees.
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`9.
`
`Kawachi teach a liquid crystal display device where supply wiring lines 62 are
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`arranged in a first direction (vertical) and are connected to the control electrode of each
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`of the plurality of selector transistors 62 for a corresponding block, as shown in Fig. 4
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`and acknowledged by the Applicant. Although the selector transistors are offset, the
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`placement shown in Fig. 4 does not affect them being adjacent. The term adjacent does
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`not require the selector transistors of the same group to be directly next or in direct
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`alignment to one another but could be neighboring, close to, or approximate to one
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`another and have the supply wiring line connected to the control terminal of each
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`selector transistor of that group, which is shown in Fig. 4. Since the claim language
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`does not define the first direction, any direction can be considered the first direction
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`including the vertical direction. In Fig. 4 of Kawachi it is shown in the vertical direction
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`that selector transistors 63 of the same group partially overlap (not fully overlap) with
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`each other as well as partially overlap with transistors of other groups.
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`10.
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`In regards to claims 2-6 and 13, since the Applicant has addressed these claims
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`based on the limitations of claim 1, the rejection will remain the same based on the
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`Examiner’s position with reference to claim 1 above.
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`Conclusion
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`2.
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`Any inquiry concerning this communication or earlier communications from the
`
`examiner should be directed to ANDRE L MATTHEWS whose telephone number is
`
`(571)270-5806. The examiner can normally be reached on Mon-Fri 9:00-6:00.
`
`

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`Application/Control Number: 15/280,554
`Art Unit: 2621
`
`Page 8
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`
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`
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`
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`
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`
`supervisor, Amr Awad can be reached on 571 -272-7764. The fax phone number for the
`
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`
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`
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`
`/ANDRE L MATTHEWS/
`
`Examiner, Art Unit 2621
`
`