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`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`PO. Box 1450
`Alexandria, Virginia 2231371450
`
`15/280,554
`
`09/29/2016
`
`Tetsuo FUKAMI
`
`20326.0086USOI
`
`7752
`
`53148
`
`759°
`
`03/19/2020
`
`HAMRE, SCHUMANN, MUELLER & LARSON RC.
`45 South Seventh Street
`Suite 2700
`
`MINNEAPOLIS, MN 55402-1683
`
`MATTHEWS” ANDREL
`
`ART UNIT
`2621
`
`PAPER NUMBER
`
`NOTIFICATION DATE
`
`DELIVERY MODE
`
`03/19/2020
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above—indicated "Notification Date" to the
`
`following e—mail address(es):
`PTOMail@hsml.eom
`
`PTOL-90A (Rev. 04/07)
`
`

`

`017/09 A0170” Summary
`
`Application No.
`15/280,554
`Examiner
`ANDRE L MATTH EWS
`
`Applicant(s)
`FUKAMI et al.
`Art Unit
`2621
`
`AIA (FITF) Status
`Yes
`
`- The MAILING DA TE of this communication appears on the cover sheet wit/7 the correspondence address -
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE g MONTHS FROM THE MAILING
`DATE OF THIS COMMUNICATION.
`Extensions of time may be available under the provisions of 37 CFR 1.136(a). In no event, however, may a reply be timely filed after SIX (6) MONTHS from the mailing
`date of this communication.
`|f NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any earned patent term
`adjustment. See 37 CFR 1.704(b).
`
`Status
`
`1). Responsive to communication(s) filed on 12/17/2019.
`CI A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/were filed on
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`2a). This action is FINAL.
`
`2b) D This action is non-final.
`
`3)[:] An election was made by the applicant in response to a restriction requirement set forth during the interview
`on
`; the restriction requirement and election have been incorporated into this action.
`
`4):] Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Expade Quay/e, 1935 CD. 11, 453 O.G. 213.
`
`Disposition of Claims*
`
`5)
`
`Claim(s)
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`1—6 and 13—14 is/are pending in the application.
`
`5a) Of the above claim(s)
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`is/are withdrawn from consideration.
`
`
`
`[:1 Claim(ss)
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`is/are allowed.
`
`Claim(ss) 1 —6 and 13— 14 is/are rejected.
`
`D Claim(ss_) is/are objected to.
`
`) ) ) )
`
`S)
`are subject to restriction and/or election requirement
`[:1 Claim(s
`* If any claims have been determined aflowable. you may be eligible to benefit from the Patent Prosecution Highway program at a
`
`participating intellectual property office for the corresponding application. For more information, please see
`
`http://www.uspto.gov/patents/init events/pph/index.jsp or send an inquiry to PPeredback@uspto.gov.
`
`Application Papers
`
`10)|:l The specification is objected to by the Examiner.
`
`11). The drawing(s) filed on 9/29/2016 is/are: a). accepted or b)C] objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`
`12). Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
`Certified copies:
`
`a). All
`
`b)C] Some**
`
`c)C] None of the:
`
`1.. Certified copies of the priority documents have been received.
`
`2C] Certified copies of the priority documents have been received in Application No.
`
`SD Copies of the certified copies of the priority documents have been received in this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`
`** See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`1)
`
`Notice of References Cited (PTO-892)
`
`2) C] Information Disclosure Statement(s) (PTO/SB/OBa and/or PTO/SB/08b)
`Paper No(s)/Mail Date_
`U.S. Patent and Trademark Office
`
`3) E] Interview Summary (PTO-413)
`Paper No(s)/Mail Date
`4) CI Other-
`
`PTOL-326 (Rev. 11-13)
`
`Office Action Summary
`
`Part of Paper No./Mai| Date 20200304
`
`

`

`Application/Control Number: 15/280,554
`Art Unit: 2621
`
`Page 2
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`Notice of Pre-AIA or AIA Status
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`1.
`
`The present application, filed on or after March 16, 2013, is being examined
`
`under the first inventor to file provisions of the AIA.
`
`Response to Arguments
`
`1.
`
`Applicant’s arguments with respect to claims 1-4,6, and 14 have been considered
`
`but are moot because the arguments do not apply to any of the references being used
`
`in the current rejection.
`
`2.
`
`The Examiner recognizes the cancellation of claims 5 and 13.
`
`Claim Rejections - 35 USC § 103
`
`3.
`
`The following is a quotation of 35 U.S.C. 103 which forms the basis for all
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`obviousness rejections set forth in this Office action:
`
`A patent for a claimed invention may not be obtained, notwithstanding that the claimed
`invention is not identically disclosed as set forth in section 102, if the differences between the
`claimed invention and the prior art are such that the claimed invention as a whole would have
`been obvious before the effective filing date of the claimed invention to a person having
`ordinary skill in the art to which the claimed invention pertains. Patentability shall not be
`negated by the manner in which the invention was made.
`
`4.
`
`Claims 1-4 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable
`
`over Kawachi (US 2015/0029081) in view of Kim (US 2010/0321248).
`
`5.
`
`Regarding claim 1, Kawachi teaches A display device, comprising:
`
`a plurality of groups, each group having a plurality of data lines extending in a first
`
`direction (Fig. 2,11,19 data lines yn)and a plurality of gate lines extending in a
`
`second direction (Figs. 2, 11, 19 gate lies xn), wherein the plurality of gate lines for
`
`each group are adjacent in the first, direction (Fig. 4 [0072-0073] teach how scan lines
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`x are grouped to selection lines 61); a plurality of blocks, each block including: a
`
`plurality of selector transistors and each of the plurality of selector transistors includes: a
`
`

`

`Application/Control Number: 15/280,554
`Art Unit: 2621
`
`Page 3
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`first conductive electrode connected to an end of a corresponding gate line of the
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`plurality of gate lines, a second conductive electrode, and a control electrode (Figs. 4,
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`[0078] transistor 63 is connected to scan line 61x and selection lines 62), wherein
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`each block among the plurality of blocks corresponds to a group among the plurality of
`
`the groups (Fig. 4 groups are defined by TFTs connected to the same scan line 61x
`
`or the same selection line 62); a plurality of selection signal supplying wirings each of
`
`which is connected to the control electrode of each of the plurality of selector
`
`transistors for a corresponding block of the plurality of blocks (Fig. 4 selection lines 62
`
`are connected to transistors 63); a plurality of gate voltage supplying wirings each of
`
`which is connected to the second conductive electrode of one of the plurality of selector
`
`transistors in each of the groups(Fig. 4 groups are defined by TFTs connected to the
`
`scan line 61x and selection line 62); and a gate driver that sequentially supplies a
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`gate voltage to the plurality of gate voltage supplying wirings and supplies a control
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`voltage to the plurality of selection signal supplying wirings to turn on or off one or more
`
`of the plurality of selector transistors([0082]). Although Kawachi teaches the limitations
`
`as discussed above, he fails to teach a dummy transistor having a control electrode and
`
`being disposed between two adjacent blocks among the plurality of blocks, wherein the
`
`plurality of blocks include a first block and a second block next to the first block, and the
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`control electrode of each of the plurality of selector transistors included in the first block
`
`and the control electrode of the dummy transistor adjacent to the first block are
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`integrally formed, and the control electrode of the dummy transistor adjacent to the first
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`block is electrically isolated from and spaced apart from the control electrode of each of
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`the plurality of selector transistors included in the second block.
`
`

`

`Application/Control Number: 15/280,554
`Art Unit: 2621
`
`Page 4
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`However in the same field of manufacturing a display device, Kim teaches a
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`dummy transistor having a control electrode and being disposed between two adjacent
`
`blocks among the plurality of blocks (Figs. 4-7 dummy circuits comprising dummy
`
`transistors 151 and 155), wherein the plurality of blocks include a first block and a
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`second block next to the first block (blocks can be individual transistor of switching
`
`circuits 161 and 165) , and the control electrode of each of the plurality of selector
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`transistors included in the first block and the control electrode of the dummy transistor
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`adjacent to the first block are integrally formed (Figs. 4-7 show control electrodes of
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`switching transistor blocks 161 and 165 integrally formed with control electrodes
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`of dummy transistors 151 and 155), and the control electrode of the dummy transistor
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`adjacent to the first block is electrically isolated from and spaced apart from the control
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`electrode of each of the plurality of selector transistors included in the second block
`
`(Figs. 4-7 show block 151 isolated from block 155).
`
`Therefore it would have been obvious to one of ordinary skill in the art at the time
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`of the effective filing date to combine the display device as taught by Kawachi with the
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`manufacturing method as taught by Kim. This combination would result in a system that
`
`provides a faster turn-on time for circuits in the display device as taught by Kim [0008].
`
`Regarding claim 2, Kawachi teaches wherein a first block and a second block among
`
`the plurality of blocks are sequentially arranged in a scanning direction(Fig. 4 groups
`
`are defined by TFTs connected to the same scan line 61x or the same selection
`
`line 62 and shows groups sequentially arranged), and the light shielding part is
`
`

`

`Application/Control Number: 15/280,554
`Art Unit: 2621
`
`Page 5
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`disposed between a selector transistor connected to a gate line scanned last in the first
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`block and a selector transistor connected to a gate line scanned first in the second
`
`block([0094] teaches the scanning lines 61 can act as light-blocking to inhibit light
`
`transmission to the color filter substrate).
`
`Regarding claim 3, Kawachi teaches wherein the control electrodes for each of
`
`the plurality of selector transistors included in a block among the plurality of blocks are
`
`integrally formed (Fig. 4 groups are defined by TFT electrodes connected to the
`
`same scan line 61x or the same selection line 62 and shows groups sequentially
`
`arranged).
`
`Regarding claim 4, Kawachi teaches wherein the light shielding part is an
`
`extended part of the control electrode of a selector transistor among the plurality of
`
`selector transistors([0094] teaches the scanning lines 61 can act as light-blocking
`
`to inhibit light transmission to the color filter substrate. Scanning lines extended
`
`from electrodes).
`
`Regarding claim 13, Kawachi a light shielding part that is disposed between at
`
`least two adjacent blocks among the plurality of blocks ([0094] teaches the scanning
`
`lines 61 can act as light-blocking to inhibit light transmission to the color filter
`
`substrate).
`
`Regarding claim 14, Kawachi teaches wherein the plurality of selector transistors
`
`for each block are adjacent in the first direction(vertical) and at least partially overlap
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`when viewed in the first direction (Fig. 4 shows selector transistors 63 adjacently
`
`disposed in a first direction and where groups of transistors partially overlapping
`
`transistors in the same group and adjacent groups).
`
`

`

`Application/Control Number: 15/280,554
`Art Unit: 2621
`
`Page 6
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`4.
`
`Claims 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over
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`Kawachi (US 2015/0029081) in view of Kim (US 2010/0321248) Yuminami
`
`(2016/0070130).
`
`5.
`
`Regarding claim 6, Kawachi teaches the limitations as discussed above
`
`and also teaches a light blocking function of a scan line, but fails to teach wherein the
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`dummy transistor includes a first conductive electrode and a second conductive
`
`electrode, wherein each of the plurality of selection signal supplying wirings is not
`
`connected to the first conductive electrode and the second conductive electrode of the
`
`dummy transistor, and wherein each of the plurality of gate voltage supplying wirings is
`
`not connected to the first conductive electrode and the second conductive electrode of
`
`the dummy transistor
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`However in the same field of disposing light blocking elements in a display
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`device, Yuminami teaches wherein the dummy transistor includes a first conductive
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`electrode and a second conductive electrode (dummy TFT of dummy pixel 31),
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`wherein each of the plurality of selection signal supplying wirings is not connected to the
`
`first conductive electrode and the second conductive electrode of the dummy transistor
`
`(dummy gate line 31a connected to dummy TFT. This well known the gate line is
`
`connected to gate electrode), and wherein each of the plurality of gate voltage
`
`supplying wirings (regular gate lines 19) is not connected to the first conductive
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`electrode and the second conductive electrode of the dummy transistor (Fig. 7 and
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`[0078] show dummy pixels 31 connected to dummy gate lines 31a and not pixel
`
`gate lines 19).
`
`

`

`Application/Control Number: 15/280,554
`Art Unit: 2621
`
`Page 7
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`Therefore it would have been obvious to one of ordinary skill at the time of the
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`effective filing date to combine the light blocking method as taught by Kawachi with the
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`display manufacturing method as taught by Kim and the light blocking method as
`
`taught by Yuminami. This combination would provide a display that reduce shadow and
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`improve appearances of the panel as taught by Yuminami [0005].
`
`Conclusion
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`Applicant's amendment necessitated the new ground(s) of rejection presented in
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`this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP
`
`§ 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37
`
`CFR1.136(a).
`
`A shortened statutory period for reply to this final action is set to expire THREE
`
`MONTHS from the mailing date of this action.
`
`In the event a first reply is filed within
`
`TWO MONTHS of the mailing date of this final action and the advisory action is not
`
`mailed until after the end of the THREE-MONTH shortened statutory period, then the
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`shortened statutory period will expire on the date the advisory action is mailed, and any
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`extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of
`
`the advisory action.
`
`In no event, however, will the statutory period for reply expire later
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`than SIX MONTHS from the date of this final action.
`
`Any inquiry concerning this communication or earlier communications from the
`
`examiner should be directed to ANDRE L MATTHEWS whose telephone number is
`
`(571)270-5806. The examiner can normally be reached on Mon-Fri 9:00-6:00.
`
`Examiner interviews are available via telephone, in-person, and video
`
`conferencing using a USPTO supplied web-based collaboration tool. To schedule an
`
`

`

`Application/Control Number: 15/280,554
`Art Unit: 2621
`
`Page 8
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`interview, applicant is encouraged to use the USPTO Automated Interview Request
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`
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`
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`
`organization where this application or proceeding is assigned is 571-273-8300.
`
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`
`/ANDRE L MATTHEWS/
`
`Examiner, Art Unit 2621
`
`