`“x
`‘\\f
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMIVHSSIONER FOR PATENTS
`PO. Box 1450
`Alexandria1 Virginia 22313-1450
`www.uspto.gov
`
`
`
`
`
`15/428,477
`
`02/09/2017
`
`SHOGO OKITA
`
`PIPMM—57210
`
`8291
`
`07’2”” —PEARNE&GORDON LLP m
`7590
`52054
`1801 EAST 9TH STREET
`MULPURL SAVITRI
`S UITE 1 200
`CLEVELAND, OH 441 14-3 108
`
`PAPER NUMBER
`
`ART UNIT
`2816
`
`NOTIFICATION DATE
`
`DELIVERY MODE
`
`07/20/2017
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above—indicated "Notification Date" to the
`following e—mail address(es):
`
`patdocket @ pearne.c0m
`
`PTOL—90A (Rev. 04/07)
`
`

`

`
`
`Applicant(s)
`Application No.
` 15/428,477 OKITA ET AL.
`
`
`AIA (First Inventor to File)
`Art Unit
`Examiner
`Office Action Summary
`
`
`SAVITR MULPURI $2215 2816
`-- The MAILING DA TE of this communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE g MONTHS FROM THE MAILING DATE OF
`THIS COMMUNICATION.
`Extensions of time may be available under the provisions of 37 CFR1. 136( a).
`after SIX () MONTHS from the mailing date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any
`earned patent term adjustment. See 37 CFR 1 .704(b).
`
`In no event, however, may a reply be timely filed
`
`Status
`
`1)IZI Responsive to communication(s) filed on 2/9/2017.
`El A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/were filed on
`
`2b)|ZI This action is non-final.
`2a)|:l This action is FINAL.
`3)I:I An election was made by the applicant in response to a restriction requirement set forth during the interview on
`
`; the restriction requirement and election have been incorporated into this action.
`
`4)|:| Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`
`closed in accordance with the practice under Exparte Quay/e, 1935 CD. 11, 453 O.G. 213.
`
`Disposition of Claims*
`
`5)IZI Claim(s) fl is/are pending in the application.
`5a) Of the above claim(s)
`is/are withdrawn from consideration.
`
`is/are allowed.
`6)I:I Claim(s)
`7)|Z| CIaim(s)_1-3is/are rejected.
`8)|:I Claim(s)_ is/are objected to.
`
`
`are subject to restriction and/or election requirement.
`9)I:I Claim((s)
`* If any claims have been determined allowable, you may be eligible to benefit from the Patent Prosecution Highway program at a
`
`participating intellectual property office for the corresponding application. For more information, please see
`hit
`:/'I’vaIW.usnI‘.0. ovI’ atentS/init events/
`
`
`
`iindex.‘s or send an inquiry to PPI-iieedback{®usgtc.00v.
`
`Application Papers
`
`10)I:l The specification is objected to by the Examiner.
`11)I:l The drawing(s) filed on
`is/are: a)I:I accepted or b)I:I objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`
`12)IXI Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
`Certified copies:
`
`a)IZl All
`
`b)|:l Some” c)I:l None of the:
`
`1.IXI Certified copies of the priority documents have been received.
`2.|:l Certified copies of the priority documents have been received in Application No.
`3.|:| Copies of the certified copies of the priority documents have been received in this National Stage
`
`application from the International Bureau (PCT Rule 17.2(a)).
`** See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`
`
`3) D Interview Summary (PTO-413)
`1) E Notice of References Cited (PTO-892)
`Paper No(s)/Mai| Date.
`.
`.
`4) I:I Other'
`2) E InformatIon DIsclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`Paper No(s)/Mai| Date 2/9/2017.
`US. Patent and Trademark Office
`PTOL—326 (Rev. 11-13)
`
`Office Action Summary
`
`Part of Paper No./Mai| Date 20170714
`
`

`

`Application/Control Number: 15/428,477
`
`Page 2
`
`Art Unit: 2816
`
`The present application, filed on or after March 16, 2013, is being examined
`
`under the first inventor to file provisions of the AIA.
`
`This action is in response to applicant’s communication field on 2/9/2017.
`
`Receipt is acknowledged of certified copies of papers required by 37 CFR
`
`1.55.
`
`Information Disclosure Statement
`
`The information disclosure statement (IDS) submitted on 2/9/2017 was
`
`considered by the examiner.
`
`Claim Rejections - 35 USC § 102
`
`The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102
`
`that form the basis for the rejections under this section made in this Office action:
`
`A person shall be entitled to a patent unless ,
`
`(a)(l) the claimed invention was patented, described in a printed publication, or in public use, on sale or
`otherwise available to the public before the effective filing date of the claimed invention.
`
`Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by
`
`Geerpuram et al(US 8,691,702)
`
`With respect to claim1 et al teach a method for manufacturing an element
`
`chip, comprising: a mounting' step of mounting a semiconductor substrate with
`
`

`

`Application/Control Number: 15/428,477
`
`Page 3
`
`Art Unit: 2816
`
`flexibility, which has a first main surface and a second main surface located at an
`
`opposite side of the first main surface, which has a plurality element regions and
`
`a dividing region for defining the element regions, and on which a mask
`
`“200”for covering the first main surface in each of the elements “1 lO”region and
`
`for exposing the first main surface in the dividing region is formed, on a stage
`
`which is included in a plasma processing apparatus, in a state where the second
`
`main surface is held on a holding sheet”300”: and a plasma dicing step of dicing
`
`the semiconductor substrate into a plurality of element chips including the element
`
`regions by exposing a side of the first main surface of the semiconductor
`
`substrate”lOO” to plasma on the stage and etching the semiconductor substrate
`
`from the side of the first main surface to the second main surface while forming a
`
`groove on the dividing region, wherein a thickness of the semiconductor substrate
`
`is smaller than a thickness of the holding sheet, and in the plasma dicing step, by
`
`performing the etching the semiconductor substrate from the side of the first main
`
`surface to the second main surface in a state where a bottom portion of the groove
`
`is always exposed, the semiconductor substrate is diced without forming a scallop
`
`on a side surface of each of the element chips”l lO”.(abstract; fig.2,3,5,7 and
`
`related deception)
`
`

`

`Application/Control Number: 15/428,477
`
`Page 4
`
`Art Unit: 2816
`
`With respect to claim 2, Geerpuram et al teach the method, wherein the
`
`thickness of the semiconductor substrate is 50 microns or less(seecol3, lines 5-10) .
`
`With respect to claim 3, Geerpuram et al teach the method, wherein, in the
`
`plasma dicing step, the plasma is generated using a process gas containing sulfur
`
`hexafluoride and oxygen, as a raw material(col. 25, lines 38-58).
`
`Conclusion
`
`The prior art made of record and not relied upon is considered pertinent to
`
`applicant's disclosure. Prior art teach plasma dicing.
`
`Any inquiry concerning this communication or earlier communications from
`
`the examiner should be directed to SAVITR MULPURI Whose telephone number
`
`is (571)272-1677. The examiner can normally be reached on Mon-Fri from 8am to
`
`4.30pm.
`
`If attempts to reach the examiner by telephone are unsuccessful, the
`
`examiner's supervisor, Zandra Smith, can be reached on 571-272-2429 The fax
`
`phone number for the organization Where this application or proceeding is assigned
`
`is 571-273-8300.
`
`Information regarding the status of an application may be obtained from the
`
`Patent Application Information Retrieval (PAIR) system. Status information for
`
`

`

`Application/Control Number: 15/428,477
`
`Page 5
`
`Art Unit: 2816
`
`published applications may be obtained from either Private PAIR or Public PAIR.
`
`Status information for unpublished applications is available through Private PAIR
`
`only. For more information about the PAIR system, see
`
`http://portal.uspto.gov/external/portal. Should you have questions on access to the
`
`Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-
`
`9197 (toll-free).
`
`/SAVITR MULPURI/
`
`Primary Examiner, Art Unit 2816
`
`