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`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`PO. Box 1450
`Alexandria, Virginia 2231371450
`
`15/864,836
`
`01/08/2018
`
`YOShihil‘O IMAJO
`
`20326.0121USW1
`
`1013
`
`53148
`
`759°
`
`08/05/20”
`
`HAMRE, SCHUMANN, MUELLER & LARSON RC.
`45 South Seventh Street
`Suite 2700
`
`MINNEAPOLIS, MN 55402-1683
`
`SHEN' YUZHEN
`
`PAPER NUMBER
`
`ART UNIT
`2691
`
`NOTIFICATION DATE
`
`DELIVERY MODE
`
`08/05/2019
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above—indicated "Notification Date" to the
`
`following e—mail address(es):
`PTOMail@hsml.eom
`
`PTOL-90A (Rev. 04/07)
`
`

`

`0,7709 A0170” Summary
`
`Application No.
`15/864,836
`Examiner
`YUZHEN SHEN
`
`Applicant(s)
`IMAJO et al.
`Art Unit
`2691
`
`AIA (FITF) Status
`Yes
`
`- The MAILING DA TE of this communication appears on the cover sheet wit/7 the correspondence address -
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE g MONTHS FROM THE MAILING
`DATE OF THIS COMMUNICATION.
`Extensions of time may be available under the provisions of 37 CFR 1.136(a). In no event, however, may a reply be timely filed after SIX (6) MONTHS from the mailing
`date of this communication.
`|f NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any earned patent term
`adjustment. See 37 CFR 1.704(b).
`
`Status
`
`1). Responsive to communication(s) filed on 07/03/2019.
`[:1 A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/were filed on
`
`2a)D This action is FINAL.
`
`2b)
`
`This action is non-final.
`
`3)[:] An election was made by the applicant in response to a restriction requirement set forth during the interview on
`; the restriction requirement and election have been incorporated into this action.
`
`4)[:] Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Expat/7e Quay/e, 1935 CD. 11, 453 O.G. 213.
`
`Disposition of Claims*
`
`5)
`
`Claim(s) fl is/are pending in the application.
`
`5a) Of the above claim(s) 5—6,9—15 and 17 is/are withdrawn from consideration.
`
`E] Claim(s) _ is/are allowed.
`
`Claim(s) 1—4,7—8,16 and 18—20 is/are rejected.
`
`C] Claim(s) _
`
`is/are objected to.
`
`) ) ) )
`
`6 7
`
`8
`
`
`
`are subject to restriction and/or election requirement
`[:1 Claim(s)
`9
`* If any claims have been determined allowable, you may be eligible to benefit from the Patent Prosecution Highway program at a
`
`participating intellectual property office for the corresponding application. For more information, please see
`
`http://www.uspto.gov/patents/init events/pph/index.'sp or send an inquiry to PPeredback@uspto.gov.
`
`Application Papers
`10). The specification is objected to by the Examiner.
`
`11). The drawing(s) filed on 01/08/2019 is/are: a). accepted or b)C] objected to by the Examiner.
`
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`12). Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
`Certified copies:
`
`a). All
`
`b)|:] Some**
`
`c)C] None of the:
`
`1.. Certified copies of the priority documents have been received.
`
`21:] Certified copies of the priority documents have been received in Application No.
`
`3D Copies of the certified copies of the priority documents have been received in this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`
`** See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`1)
`
`Notice of References Cited (PTO-892)
`
`Information Disclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`2)
`Paper No(s)/Mail Date_
`U.S. Patent and Trademark Office
`
`3) C] Interview Summary (PTO-413)
`Paper No(s)/Mail Date
`4) CI Other-
`
`PTOL-326 (Rev. 11-13)
`
`Office Action Summary
`
`Part of Paper No./Mai| Date 20190711
`
`

`

`Application/Control Number: 15/864,836
`Art Unit: 2691
`
`Page 2
`
`Detailed Action
`
`1.
`
`The present application, filed on or after March 16,2013, is being examined under
`
`the first inventor to file provisions of the AIA.
`
`Priority
`
`2.
`
`Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C.
`
`119(a)-(d), which papers have been placed of record in the file.
`
`Election/Restrictions
`
`3.
`
`Applicant’s election of Species A of Fig. 5, corresponding to claims 1-4, 7, 8, 16,
`
`and 18-20,
`
`in the reply filed on 07/03/2019 is acknowledged. Because applicant did not
`
`distinctly and specifically point out the supposed errors in the restriction requirement, the
`
`election has been treated as an election without traverse (MPEP § 818.03(a)). Claims 5-
`
`6, 9-15 and 17 are withdrawn from consideration by applicant.
`
`Specification
`
`4.
`
`The title of the invention is not descriptive. A new title is required that is clearly
`
`indicative of the invention to which the claims are directed.
`
`Claim Rejections - 35 USC § 103
`
`5.
`
`The following is a quotation of 35 U.S.C. 103 which forms the basis for all
`
`obviousness rejections set forth in this Office action:
`
`

`

`Application/Control Number: 15/864,836
`Art Unit: 2691
`
`Page 3
`
`A patent for a claimed invention may not be obtained, notwithstanding that
`
`the claimed invention is not identically disclosed as set forth in section 102
`
`if the differences between the claimed invention and the prior
`of this title,
`art are such that
`the claimed invention as a whole would have been
`
`obvious before the effective filing date of the claimed invention to a person
`
`having ordinary skill
`
`in the art to which the claimed invention pertains.
`
`Patentability shall not be negated by the manner in which the invention
`was made.
`
`6.
`
`Claims 1-4, 7-8, 16 and 18 are rejected under 35 U.S.C. 103 as unpatentable over
`
`Li (US 20140313185 A1) in View of Horiuchi (US 20100141570 A1).
`
`Regarding claim 1, Li (Figs. 1-13) discloses a driving circuit (e.g., gate driver 203
`
`as shown in Fig. 3 or gate driver 603 as shown in Fig. 6) comprising:
`
`an output circuit (output circuit 303) that outputs a signal to a lead line (signal
`
`line connected between output circuit 303 and gate line G) electrically connected to
`
`a signal line (gate line G) provided in a display panel (display panel 201); and
`
`an output switching circuit (switching circuit CCn) that is provided in the output
`
`circuit (output circuit 303) and connected to an output terminal (output terminal Sn) of
`
`the output circuit (output circuit 303),
`
`wherein an on-resistance value of the output switching circuit (Fig. 4 and Table 1
`
`and Table 2; compensation resistance switching circuit CCn) is set according to a
`
`resistance value of the lead line electrically connected to the output transistor (Fig. 4 and
`
`Table 1 and Table 2; resistance of lead line and corresponding compensation
`
`resistance).
`
`

`

`Application/Control Number: 15/864,836
`Art Unit: 2691
`
`Page 4
`
`Li discloses an output switching circuit but does not expressly disclose the output
`
`switching circuit comprises an output transistor. However, Horiuchi (Figs. 1-5 and 9)
`
`discloses a driving circuit (e.g., gate driver 203 including shift register 4) comprising:
`
`an output circuit (output circuit as shown in Fig. 3) that outputs a signal to a lead
`
`line (signal
`
`line connected between output circuit 4 and gate line GL) electrically
`
`connected to a signal line (gate line GL) provided in a display panel (display panel 1);
`
`and
`
`an output transistor (output transistor 21 or 22 as shown in Fig. 3) that
`
`is
`
`provided in the output circuit (output circuit as shown in Fig. 3) and connected to an
`
`output terminal of the output circuit (output circuit as shown in Fig. 3),
`
`wherein an on-resistance value of the output transistor (Fig. 3; output transistor
`
`21 or 22) is set according to a resistance value of the signal line electrically connected to
`
`the output transistor (Figs. 1 and 3 and [0087]-[0093]; on-resistance value of the
`
`output transistor 21 or 23 is set by setting channel width of the output transistor in
`
`accordance with the resistance or delay of the signal line connected to the output
`
`transistor).
`
`Horiuchi (Figs. 1-5) discloses on-resistance value of the output transistor 21 or 23 is set
`
`by setting channel width of the output transistor in accordance with the resistance or delay
`
`of the signal line connected to the output transistor (Figs.
`
`1 and 3 and [0087]-[0093]), the
`
`signal line includes both lead line and gate line as shown in Fig. 1. Horiuchi (Figs. 1-5)
`
`also suggests on-resistance value of
`
`the output
`
`transistor 21 or 23 can be set to
`
`compensate the resistance or delay associated with lead lines having different length of
`
`

`

`Application/Control Number: 15/864,836
`Art Unit: 2691
`
`Page 5
`
`adisplay device as shown in Fig. 9. Therefore,
`
`it would have been obvious to one skilled
`
`in the art at the effective filing date of the claimed invention to incorporate the teaching
`
`from Horiuchi to the display device of Li for resistance compensation of lead lines having
`
`different length. The combination/motivation would be to provide a gate driver having a
`
`resistance compensation function to reduce resistance difference between signal lines.
`
`Regarding claim 2, Li
`
`in view of Horiuchi discloses the driving circuit according to
`
`claim 1, wherein the on-resistance value of the output transistor is set (Figs. 1 and 3 and
`
`[0087]-[0093]; on-resistance value of the output transistor 21 or 23 is set by setting
`
`channel width of the output transistor) so as to become smaller as a length of the lead
`
`line electrically connected to the output transistor is lengthened, and so as to become
`
`larger as the length of the lead line is shortened (Li, Tables 1 and 2; resistance
`
`compensation). Therefore,
`
`it would have been obvious to one skilled in the art at the
`
`effective filing date of the claimed invention to incorporate the teaching from Horiuchi
`
`to
`
`the display device of Li for the same reason above.
`
`Regarding claim 3, Li
`
`in view of Horiuchi discloses the driving circuit according to
`
`claim 1, wherein a plurality of the output transistors (TFTs 11) are arrayed in a first
`
`direction (horizontal direction) in which a plurality of the signal
`
`lines (gate lines GL)
`
`electrically connected to the driving circuit (gate driver 4) are arranged, and the on-
`
`resistance value of each of the plurality of the output transistors is set (Figs. 1 and 3 and
`
`[0087]-[0093]; on-resistance value of the output transistor 21 or 23 is set by setting
`
`channel width of the output transistor) so as to become smaller from a center of the
`
`

`

`Application/Control Number: 15/864,836
`Art Unit: 2691
`
`Page 6
`
`driving circuit toward both end sides of the driving circuit in the first direction (Li, Tables
`
`1 and 2; resistance compensation). Therefore,
`
`it would have been obvious to one
`
`skilled in the art at the effective filing date of the claimed invention to incorporate the
`
`teaching from Horiuchi to the display device of Li for the same reason above.
`
`Regarding claim 4, Li
`
`in view of Horiuchi discloses the driving circuit according to
`
`claim 3, wherein the on-resistance value of each of the plurality of the output transistors
`
`is set (Figs. 1 and 3 and [0087]-[0093]; on-resistance value of the output transistor
`
`21 or 23 is set by setting channel width of the output transistor) so as to become
`
`smaller from the center of the driving circuit to both the end sides of the driving circuit in
`
`the first direction (Li, Tables1 and 2; resistance compensation). Therefore,
`
`it would
`
`have been obvious to one skilled in the art at the effective filing date of the claimed
`
`invention to incorporate the teaching from Horiuchi to the display device of Li for the same
`
`reason above.
`
`Regarding claim 7, Li
`
`in view of Horiuchi discloses the driving circuit according to
`
`claim 1, Horiuchi (Figs. 1-5 and 9) discloses wherein the on-resistance value of the output
`
`transistor is set by adjusting a size of a channel portion of the output transistor (Figs. 1
`
`and 3 and [0087]-[0093]; on-resistance value of the output transistor 21 or 23 is set
`
`by setting channel width of the output transistor). Therefore,
`
`it would have been
`
`obvious to one skilled in the art at the effective filing date of the claimed invention to
`
`incorporate the teaching from Horiuchi
`
`to the display device of Li for the same reason
`
`above.
`
`

`

`Application/Control Number: 15/864,836
`Art Unit: 2691
`
`Page 7
`
`Regarding claim 8, Li
`
`in view of Horiuchi discloses the driving circuit according to
`
`claim 1, Horiuchi (Figs. 1-5 and 9) discloses wherein the output transistor (Fig. 3; output
`
`transistor 21 or 22) outputs a gate-on voltage (Figs. 6-7; gate-on voltage signal)
`
`turning on a thin film transistor (Fig. 2; TFT11) connected to a gate line (gate line GL)
`
`in a pixel (Fig. 2; pixel PIX). herefore, it would have been obvious to one skilled in the art
`
`at the effective filing date of the claimed invention to incorporate the teaching from
`
`Horiuchi to the display device of Li for the same reason above.
`
`Regarding claim 16, Li (Figs. 1-13) discloses adisplay device comprising:
`
`a display panel (display panel 201) in which a plurality of signal lines (gate lines
`
`G) and a plurality of lead lines (signal line connected between output circuit 303 and
`
`gate line G) electrically connected to the plurality of signal
`
`lines (gate lines G) are
`
`provided; and
`
`a driving circuit (e.g., gate driver 203 as shown in Fig. 3 or gate driver 603 as
`
`shown in Fig. 6) including a plurality of output circuits (output circuits CC) that output
`
`a signal to the plurality of lead lines (signal lines connected between output circuit CC
`
`and gate lines G) and output switches (switches En) that are provided in the output
`
`circuits (output circuits CC) and connected to output terminals (output terminals Sn)
`
`of the output circuits (output circuits CC),
`
`wherein on-resistance values of the output switches (Fig. 4 and Table1 and Table
`
`2; compensation resistance of switching circuits CCn) are set according to resistance
`
`

`

`Application/Control Number: 15/864,836
`Art Unit: 2691
`
`Page 8
`
`values of the lead lines electrically connected to the output transistors (Fig. 4 and Table
`
`1 and Table 2; resistance of lead line and corresponding compensation resistance).
`
`Li discloses an output switching circuit but does not expressly disclose the output
`
`switching circuit comprises an output transistor. However, Horiuchi (Figs. 1-5 and 9)
`
`discloses a display device comprising:
`
`a display panel (display panel 1) in which a plurality of signal lines (gate lines
`
`GL) and a plurality of lead lines (signal lines connected between output circuit 4 and
`
`gate lines GL) electrically connected to the plurality of signal lines (gate lines GL) are
`
`provided; and
`
`a driving circuit (e.g., gate driver 203 including shift register 4) including a
`
`plurality of output circuits (output circuit as shown in Fig. 3) that output a signal (Figs.
`
`6-7; gate signal) to the plurality of lead lines (signal line connected between output
`
`circuit 4and gate line GL) and output transistors (output transistor 21 or 22 as shown
`
`in Fig. 3) that are provided in the output circuits (output circuit as shown in Fig. 3) and
`
`connected to output terminals of the output circuits (output circuit as shown in Fig. 3),
`
`wherein on-resistance values of the output transistors (Fig. 3; output transistor
`
`21 or 22) are set according to resistance values of the lead lines electrically connected
`
`to the output transistors (Figs. 1 and 3 and [0087]-[0093]; on-resistance value of the
`
`output transistor 21 or 23 is set by setting channel width of the output transistor in
`
`accordance with the resistance or delay of the signal line connected to the output
`
`transistor).
`
`

`

`Application/Control Number: 15/864,836
`Art Unit: 2691
`
`Page 9
`
`Horiuchi (Figs. 1-5) discloses on-resistance value of the output transistor 21 or 23 is set
`
`by setting channel width of the output transistor in accordance with the resistance or delay
`
`of the signal line connected to the output transistor (Figs.
`
`1 and 3 and [0087]-[0093]), the
`
`signal line includes both lead line and gate line as shown in Fig. 1. Horiuchi (Figs. 1-5)
`
`also suggests on-resistance value of
`
`the output
`
`transistor 21 or 23 can be set to
`
`compensate the resistance or delay associated with lead lines having different length of
`
`adisplay device as shown in Fig. 9. Therefore,
`
`it would have been obvious to one skilled
`
`in the art at the effective filing date of the claimed invention to incorporate the teaching
`
`from Horiuchi to the display device of Li for resistance compensation of lead lines having
`
`different length. The combination/motivation would be to provide a gate driver having a
`
`resistance compensation function to reduce resistance difference between signal lines.
`
`Regarding claim 18, Li
`
`in view of Horiuchi discloses the display device according
`
`to claim 16, wherein a part of the plurality of lead lines extends in a direction oblique to a
`
`direction in which the plurality of signal lines electrically connected to the driving circuit
`
`extend (Li, Figs. 1 and 3; Horiuchi, Fig. 9; lead lines extends in an oblique direction).
`
`7.
`
`Claim 19 is
`
`rejected under 35 U.S.C.
`
`103 as unpatentable over
`
`Li
`
`(US
`
`20140313185 A1) in view of Horiuchi (US 20100141570 A1) and further in view of Suzuki
`
`(us 6437764 B1).
`
`Regarding claim 19, Li
`
`in view of Horiuchi discloses the display device according
`
`to claim 16, but does not disclose wherein each of the lead lines is widened with
`
`decreasing length of the lead lines, and is narrowed with increasing length of the lead
`
`

`

`Application/Control Number: 15/864,836
`Art Unit: 2691
`
`Page 10
`
`lines. However, Suzuki (Figs. 1-4) discloses a display device, wherein each of the lead
`
`lines is widened with decreasing length of the lead lines, and is narrowed with increasing
`
`length of the lead lines (Fig. 4). Therefore,
`
`it would have been obvious to one skilled in
`
`the art at the effective filing date of the claimed invention to incorporate the teaching from
`
`Suzuki to the display device of Li
`
`in view of Horiuchi for resistance compensation of lead
`
`lines having different length.
`
`8.
`
`Claim 20 is
`
`rejected under 35 U.S.C. 103 as unpatentable over
`
`Li
`
`(US
`
`20140313185 A1) in View of Horiuchi (US 20100141570 A1) and further in view of Katsuta
`
`(US 20170212624 A1).
`
`Regarding claim 20, Li
`
`in view of Horiuchi discloses the display device according
`
`to claim 16, but does not disclose wherein a width of the lead line connected onto a central
`
`side of the driving circuit is larger than a width of the lead lines connected onto both end
`
`sides of the driving circuit. However, Katsuta (Figs. 2-4) discloses a display device,
`
`wherein a width of the lead line connected onto acentral side of the driving circuit is larger
`
`than a width of the lead lines connected onto both end sides of the driving circuit (Figs.
`
`6-8 and 10-13; a width of the lead line L1d is larger than a width of the lead lines
`
`L1a and L1b). Therefore,
`
`it would have been obvious to one skilled in the art at the
`
`effective filing date of the claimed invention to incorporate the teaching from Katsuta to
`
`the display device of Li
`
`in view of Horiuchi for resistance compensation of lead lines
`
`having different length.
`
`

`

`Application/Control Number: 15/864,836
`Art Unit: 2691
`
`Page 11
`
`Conclusion
`
`9.
`
`The prior art made of record and not
`
`relied upon is considered pertinent
`
`to
`
`applicant's disclosure.
`
`10.
`
`SUzuki
`
`(US 20170123285 A1) are cited to teach resistance compensation by
`
`setting on-resistance of output transistors.
`
`Inquiry
`
`Any inquiry concerning this communication or earlier communications from the
`
`examiner should be directed to YUZHEN SHEN whose telephone number is (571)272-
`
`1407. The examiner can normally be reached on Monday-Thursday 8:30am-5:00pm.
`
`If attempts to reach the examiner by telephone are unsuccessful, the examiner’s
`
`supervisor, Chanh Nguyen can be reached on 571-272-7772. The fax phone number for
`
`the organization where this application or proceeding is assigned is 571 -273-8300.
`
`Information regarding the status of an application may be obtained from the Patent
`
`Application
`
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`
`(PAIR)
`
`system. Status
`
`information for published
`
`applications may be obtained from either Private PAIR or Public PAIR. Status information
`
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`
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`
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`
`If you would like assistance from a USPTO Customer Service
`
`Representative or access to the automated information system, call 800-786-9199 (IN
`
`USA OR CANADA) or 571-272-1000.
`
`

`

`Application/Control Number: 15/864,836
`Art Unit: 2691
`
`/YUZHEN SHEN/
`
`Primary Examiner, Art Unit 2691
`
`Page 12
`
`