www.uspto.gov
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`PO. Box 1450
`Alexandria, Virginia 2231371450
`
`16/154,300
`
`10/08/2018
`
`Daisuke KAJITA
`
`20295.0025U301
`
`4022
`
`53148
`
`759°
`
`03/02/2020
`
`HAMRE, SCHUMANN, MUELLER & LARSON RC.
`45 South Seventh Street
`Suite 2700
`
`MINNEAPOLIS, MN 55402-1683
`
`LIU' SHAN
`
`PAPER NUMBER
`
`ART UNIT
`2871
`
`NOTIFICATION DATE
`
`DELIVERY MODE
`
`03/02/2020
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above—indicated "Notification Date" to the
`
`following e—mail address(es):
`PTOMail@hsml.eom
`
`PTOL-90A (Rev. 04/07)
`
`

`

`0/7709 A0170” Summary
`
`Application No.
`16/154,300
`Examiner
`SHAN LIU
`
`Applicant(s)
`KAJITA, Daisuke
`Art Unit
`AIA (FITF) Status
`2871
`Yes
`
`- The MAILING DA TE of this communication appears on the cover sheet wit/7 the correspondence address -
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE g MONTHS FROM THE MAILING
`DATE OF THIS COMMUNICATION.
`Extensions of time may be available under the provisions of 37 CFR 1.136(a). In no event, however, may a reply be timely filed after SIX (6) MONTHS from the mailing
`date of this communication.
`|f NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any earned patent term
`adjustment. See 37 CFR 1.704(b).
`
`Status
`
`1). Responsive to communication(s) filed on 1/10/2020.
`CI A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/were filed on
`
`2a). This action is FINAL.
`
`2b) D This action is non-final.
`
`3)[:] An election was made by the applicant in response to a restriction requirement set forth during the interview
`on
`; the restriction requirement and election have been incorporated into this action.
`
`4):] Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Expade Quay/e, 1935 CD. 11, 453 O.G. 213.
`
`Disposition of Claims*
`
`5)
`
`Claim(s)
`
`1—3,5—6 and 8—19 is/are pending in the application.
`
`5a) Of the above claim(s)
`
`is/are withdrawn from consideration.
`
`
`
`[:1 Claim(ss)
`
`is/are allowed.
`
`8)
`Claim(s 1 —3, 5—6 and 8— 19 is/are rejected.
`
`D Claim(ss_) is/are objected to.
`
`) ) ) )
`
`S)
`are subject to restriction and/or election requirement
`[:1 Claim(s
`* If any claims have been determined aflowable. you may be eligible to benefit from the Patent Prosecution Highway program at a
`
`participating intellectual property office for the corresponding application. For more information, please see
`
`http://www.uspto.gov/patents/init events/pph/index.jsp or send an inquiry to PPeredback@uspto.gov.
`
`Application Papers
`
`10)|:l The specification is objected to by the Examiner.
`
`is/are: a)[] accepted or b)l:] objected to by the Examiner.
`11)[:] The drawing(s) filed on
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`
`12). Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
`Certified copies:
`
`a). All
`
`b)|:] Some**
`
`c)l:i None of the:
`
`1.. Certified copies of the priority documents have been received.
`
`2C] Certified copies of the priority documents have been received in Application No.
`
`3D Copies of the certified copies of the priority documents have been received in this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`
`** See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`1)
`
`Notice of References Cited (PTO-892)
`
`2) C] Information Disclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`Paper No(s)/Mail Date_
`U.S. Patent and Trademark Office
`
`3) E] Interview Summary (PTO-413)
`Paper No(s)/Mail Date
`4) CI Other-
`
`PTOL-326 (Rev. 11-13)
`
`Office Action Summary
`
`Part of Paper No./Mai| Date 20200224
`
`

`

`Application/Control Number: 16/154,300
`Art Unit: 2871
`
`Page 2
`
`Notice of Pre-AIA or AIA Status
`
`The present application, filed on or after March 16, 2013, is being examined under the first
`
`inventor to file provisions of the AIA.
`
`Response to Amendment
`
`The amendment filed 1/10/2020 has been entered. Claims 4 and 7 are cancelled, claims 1, 5-6,
`
`8, 13 and 15 are amended, and new claims 16-19 are added. Claims 1-3, 5-6 and 8-19 are currently
`
`pending in this application.
`
`In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102
`
`and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory
`
`basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and
`
`the rationale supporting the rejection, would be the same under either status.
`
`Claim Rejections - 35 USC § 102
`
`The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis
`
`for the rejections under this section made in this Office action:
`
`A person shall be entitled to a patent unless —
`(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale
`or otherwise available to the public before the effective filing date of the claimed invention.
`
`Claims 9 and 16-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tanno et al.
`
`(US 2010/0245734).
`
`Regarding claim 9, Tanno et al. teaches a liquid crystal display panel (Fig. 1-4, Fig. 10-12, [0053-
`
`0092, 0116-0125]) having a plurality of pixels (the pixels each corresponding to one opening of BM in
`
`Fig. 1, Fig. 4 and Fig. 10-12) arranged in a matrix (Fig. 1 and Fig. 10-12), comprising:
`
`

`

`Application/Control Number: 16/154,300
`Art Unit: 2871
`
`Page 3
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`a plurality of pixel electrodes (the PIX of 40a and 40b in Fig. 2-4, [0089]) provided in a
`
`corresponding one (the pixel including 40a and 40b in Fig. 2-4, Fig. 1 and Fig. 10-12) of the plurality of
`
`pixels (the pixels each corresponding to one opening of BM in Fig. 1 and Fig. 10-12); and
`
`a plurality (Fig. 1-4 and Fig. 10-12) of pairs of first video signal lines (DL2 in Fig. 3, [0077, 0100],
`
`Fig. 1 and Fig. 10-12) and second video signal lines (DL1 in Fig. 3, [0077, 0100], Fig. 1 and Fig. 10-12)
`
`provided at a corresponding boundary (Fig. 3-4, Fig. 1 and Fig. 10-12) between two pixels (two of the
`
`pixels each corresponding to one opening of BM in Fig. 1, Fig. 4 and Fig. 10-12) adjacent to each other
`
`(Fig. 3-4, Fig. 1 and Fig. 10-12) in a first direction (X in Fig. 1-3 and 10-12), the plurality (Fig. 1-4 and Fig.
`
`10-12) of pairs of the first video signal lines (DL2 in Fig. 3, [0077, 0100], Fig. 1 and Fig. 10-12) and the
`
`second video signal lines (DL1 in Fig. 3, [0077, 0100], Fig. 1 and Fig. 10-12) extending in a second
`
`direction (Y in Fig. 1-3 and 10-12) crossing to the first direction (X in Fig. 1-3 and 10-12),
`
`wherein at least a part (Fig. 2-3) of the pixel electrode (the PIX of 40a and 40b in Fig. 2-4, [0089])
`
`exists between (Fig. 2-3) a first video signal line (DL2 in Fig. 3, [0077, 0100], Fig. 1 and Fig. 10-12) of a
`
`pair of the plurality of pairs of first video signal lines (DL2 in Fig. 3, [0077, 0100], Fig. 1 and Fig. 10-12)
`
`and second video signal lines (DL1 in Fig. 3, [0077, 0100], Fig. 1 and Fig. 10-12) and a second video signal
`
`line (DL1 in Fig. 3, [0077, 0100], Fig. 1 and Fig. 10-12) of the pair of the plurality of pairs of first video
`
`signal lines (DL2 in Fig. 3, [0077, 0100], Fig. 1 and Fig. 10-12) and second video signal lines (DL1 in Fig. 3,
`
`[0077, 0100], Fig. 1 and Fig. 10-12),
`
`each pixel electrode (the PIX of 40a/40b in Fig. 2-4, [0089]) includes a plurality of line electrodes
`
`(21 in Fig. 2-4, [0063-0064]),
`
`at least one of the plurality of line electrodes (21 in Fig. 2-4, [0063-0064]) exists between the
`
`first video signal line (DL1 in Fig. 3, [0077, 0100], Fig. 1 and Fig. 10-12) and the second video signal line
`
`(DL1 in Fig. 3, [0077, 0100], Fig. 1 and Fig. 10-12),
`
`

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`Application/Control Number: 16/154,300
`Art Unit: 2871
`
`Page 4
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`an interval (D1 in Picture 1) between two adjacent pixel electrodes (the PIX of 40a and 40b in
`
`Fig. 2-4, [0089]) is equal to (Picture 1, [0063-0064]) an interval (D2 in Picture 1) between two adjacent
`
`line electrodes (21 in Fig. 2-4, [0063-0064]) in one pixel electrode (40b in Fig. 3), and
`
`a common electrode (COM in Fig. 4, [0055, 0062, 0065-0066]) formed over (Fig. 4, [0055, 0062,
`
`0065-0066]) the plurality of pixels (the pixels each corresponding to one opening of BM in Fig. 1, Fig. 4
`
`and Fig. 10-12), wherein the common electrode (COM in Fig. 4, [0055, 0062, 0065-0066]) covers (Fig. 4)
`
`at least one of the first video signal line (DL2 in Fig. 3, [0077, 0100], Fig. 1 and Fig. 10-12) and the second
`
`video signal line (DL1 in Fig. 3, [0077, 0100], Fig. 1 and Fig. 10-12).
`
`x
`
`x ULtLJLZ}
`
`\..r’
`
`3 g
`g i
`5 g
`5 g
`
`g g
`
`/‘
`
`Picture 1 (From Fig. 3 of Tanno et al., US 2010/0245734)
`
`Regarding claim 16, Tanno et al. teaches a liquid crystal display panel (Fig. 1-4, Fig. 10-12, [0053-
`
`0092, 0116-0125]) having a plurality of pixels (the pixels each corresponding to one opening of BM in
`
`Fig. 1, Fig. 4 and Fig. 10-12) arranged in a matrix (Fig. 1 and Fig. 10-12), comprising:
`
`

`

`Application/Control Number: 16/154,300
`Art Unit: 2871
`
`Page 5
`
`a plurality of pixel electrodes (the PIX of 40a and 40b in Fig. 2-4, [0089]) provided in a
`
`corresponding one (the pixel including 40a and 40b in Fig. 2-4, Fig. 1 and Fig. 10-12) of the plurality of
`
`pixels (the pixels each corresponding to one opening of BM in Fig. 1 and Fig. 10-12); and
`
`a plurality (Fig. 1-4 and Fig. 10-12) of pairs of first video signal lines (DL2 in Fig. 3, [0077, 0100],
`
`Fig. 1 and Fig. 10-12) and second video signal lines (DL1 in Fig. 3, [0077, 0100], Fig. 1 and Fig. 10-12)
`
`provided at a corresponding boundary (Fig. 3-4, Fig. 1 and Fig. 10-12) between two pixels (two adjacent
`
`pixels of the pixels each corresponding to one opening of BM in Fig. 1, Fig. 4 and Fig. 10-12) immediately
`
`adjacent to each other (Fig. 3-4, Fig. 1 and Fig. 10-12) in a first direction (X in Fig. 1-3 and 10-12), the
`
`plurality (Fig. 1-4 and Fig. 10-12) of pairs of the first video signal lines (DL2 in Fig. 3, [0077, 0100], Fig. 1
`
`and Fig. 10-12) and the second video signal lines (DL1 in Fig. 3, [0077, 0100], Fig. 1 and Fig. 10-12)
`
`extending in a second direction (Y in Fig. 1-3 and 10-12) crossing to the first direction (X in Fig. 1-3 and
`
`10-12),
`
`wherein one (DL1 in Fig. 3, [0077, 0100], Fig. 1 and Fig. 10-12) of the first video signal line (DL2
`
`in Fig. 3, [0077, 0100], Fig. 1 and Fig. 10-12) and the second video signal line (DL1 in Fig. 3, [0077, 0100],
`
`Fig. 1 and Fig. 10-12) among one (Fig. 1-4 and Fig. 10-12) of the plurality (Fig. 1-4 and Fig. 10-12) of pairs
`
`of first video signal lines (DL2 in Fig. 3, [0077, 0100], Fig. 1 and Fig. 10-12) and second video signal lines
`
`(DL1 in Fig. 3, [0077, 0100], Fig. 1 and Fig. 10-12) is covered (Fig. 1, Fig. 4 and Fig. 10-12) with a light
`
`shielding layer (BM in Fig. 1, Fig. 4 and Fig. 10-12, [0077, 0072]) formed along the second direction (Y in
`
`Fig. 1-3 and 10-12), and
`
`the other (DL2 in Fig. 3, [0077, 0100], Fig. 1 and Fig. 10-12) of the first video signal line (DL2 in
`
`Fig. 3, [0077, 0100], Fig. 1 and Fig. 10-12) and the second video signal line (DL1 in Fig. 3, [0077, 0100],
`
`Fig. 1 and Fig. 10-12) among one (Fig. 1-4 and Fig. 10-12) of the plurality (Fig. 1-4 and Fig. 10-12) of pairs
`
`of first video signal lines (DL2 in Fig. 3, [0077, 0100], Fig. 1 and Fig. 10-12) and second video signal lines
`
`(DL1 in Fig. 3, [0077, 0100], Fig. 1 and Fig. 10-12) is not covered (Fig. 1-4 and Fig. 10-12, [0077], the
`
`

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`Application/Control Number: 16/154,300
`Art Unit: 2871
`
`Page 6
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`portions of DL2 between 40a and 40b are not covered by BM in Fig. 3-4, and the DL2 are not covered by
`
`the portions of BM formed along the Y direction in Fig. 1-3 and Fig. 10-12) with the light shielding layer
`
`(BM in Fig. 1, Fig. 4 and Fig. 10-12, [0077, 0072]) formed along the second direction (Y in Fig. 1-3 and 10-
`
`12).
`
`Regarding claim 17, Tanno et al. also teaches that at least a part (Fig. 2-3) of the pixel electrode
`
`(the PIX of 40a and 40b in Fig. 2-4, [0089]) exists between (Fig. 2-3) the first video signal line (DL2 in Fig.
`
`3, [0077, 0100], Fig. 1 and Fig. 10-12) and the second video signal line (DL1 in Fig. 3, [0077, 0100], Fig. 1
`
`and Fig. 10-12).
`
`Regarding claim 18, Tanno et al. also teaches that a common electrode (COM in Fig. 4, [0055,
`
`0062, 0065-0066]) formed over (Fig. 4, [0055, 0062, 0065-0066]) the plurality of pixels (the pixels each
`
`corresponding to one opening of BM in Fig. 1, Fig. 4 and Fig. 10-12), wherein the common electrode
`
`(COM in Fig. 4, [0055, 0062, 0065-0066]) covers (Fig. 4) at least one of the first video signal line (DL2 in
`
`Fig. 3, [0077, 0100], Fig. 1 and Fig. 10-12) and the second video signal line (DL1 in Fig. 3, [0077, 0100],
`
`Fig. 1 and Fig. 10-12).
`
`Claim Rejections - 35 USC § 103
`
`The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections
`
`set forth in this Office action:
`
`A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is
`not identically disclosed as set forth in section 102 of this title, if the differences between the claimed
`invention and the prior art are such that the claimed invention as a whole would have been obvious
`before the effective filing date of the claimed invention to a person having ordinary skill in the art to
`which the claimed invention pertains. Patentability shall not be negated by the manner in which the
`invention was made.
`
`

`

`Application/Control Number: 16/154,300
`Art Unit: 2871
`
`Page 7
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`Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Tanno et al. as
`
`applied to claim 9 above, and in view of Kim et al. (US 2012/0218199).
`
`Re claim 10, Tanno et al. does not explicitly teach that a common line electrically connected to
`
`the common electrode.
`
`Kim et al. teaches that (Fig. 3 and Fig. 10A-103, [0047, 0071-0078]) a common line (TY11/TY12 in
`
`Fig. 10A-103, [0078, 0075-0077]) electrically connected to the common electrode (common electrode
`
`COM including C11~C33, [0047, 0078, 0071], Fig. 3 and Fig. 10A-103).
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that a common line electrically connected to the common electrode
`
`as taught by Kim et al. for the system of Tanno et al. since this would help to provide a touch sensor
`
`integrated display device, thus resulting in a reduced thickness of the display device and improved
`
`durability, and a touch sensor integrated display device wherein signal lines for recognizing a touch and
`
`data lines overlap each other to thus improve an aperture ratio of the display device (Kim et al., [0014]).
`
`Re claim 11, Tanno et al. does not explicitly teach that the common line extends in the second
`
`direction, and overlaps the first video signal line or the second video signal line in planar view.
`
`Kim et al. teaches that (Fig. 3 and Fig. 10A-103, [0047, 0071-0078]) the common line (TY11/TY12
`
`in Fig. 10A-103, [0078, 0075-0077]) extends in the second direction (the vertical direction in Fig. 10A and
`
`3), and overlaps a first video signal line (D1 in Fig. 10A, [0074]) or a second video signal line (D2 in Fig.
`
`10A, [0074]) in planar view (Fig. 10A).
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that the common line extends in the second direction, and overlaps a
`
`first video signal line or a second video signal line in planar view as taught by Kim et al. for the system of
`
`Tanno et al. such that the common line extends in the second direction, and overlaps the first video
`
`

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`Application/Control Number: 16/154,300
`Art Unit: 2871
`
`Page 8
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`signal line or the second video signal line of the system of Tanno et al. in planar view since this would
`
`help to provide a touch sensor integrated display device, thus resulting in a reduced thickness of the
`
`display device and improved durability, and a touch sensor integrated display device wherein signal lines
`
`for recognizing a touch and data lines overlap each other to thus improve an aperture ratio of the
`
`display device (Kim et al., [0014]).
`
`Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Tanno et al. as applied to
`
`claim 18 above, and in view of Kim et al. (US 2012/0218199).
`
`Re claim 19, Tanno et al. already teaches the first video signal line or the second video signal
`
`line. Tanno et al. does not explicitly teach that a common line electrically connected to the common
`
`electrode, the common line extends in the second direction, and overlaps the first video signal line or
`
`the second video signal line in planar view.
`
`Kim et al. teaches that (Fig. 3 and Fig. 10A-103, [0047, 0071-0078]) a common line (TY11/TY12 in
`
`Fig. 10A-103, [0078, 0075-0077]) electrically connected to the common electrode (common electrode
`
`COM including C11NC33, [0047, 0078, 0071], Fig. 3 and Fig. 10A-103), the common line (TY11/TY12 in
`
`Fig. 10A-103, [0078, 0075-0077]) extends in the second direction (the vertical direction in Fig. 10A and
`
`3), and overlaps a first video signal line (D1 in Fig. 10A, [0074]) or a second video signal line (D2 in Fig.
`
`10A, [0074]) in planar view (Fig. 10A).
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that a common line electrically connected to the common electrode,
`
`the common line extends in the second direction, and overlaps a first video signal line or a second video
`
`signal line in planar view as taught by Kim et al. for the system of Tanno et al. such that a common line
`
`electrically connected to the common electrode, the common line extends in the second direction, and
`
`overlaps the first video signal line or the second video signal line of the system of Tanno et al. in planar
`
`

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`Application/Control Number: 16/154,300
`Art Unit: 2871
`
`Page 9
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`view since this would help to provide a touch sensor integrated display device, thus resulting in a
`
`reduced thickness of the display device and improved durability, and a touch sensor integrated display
`
`device wherein signal lines for recognizing a touch and data lines overlap each other to thus improve an
`
`aperture ratio of the display device (Kim et al., [0014]).
`
`Claims 1, 2, 5, 6, 8, 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over
`
`Yamazaki et al. (US 2018/0203319) in view of Matsushima (US 2017/0242310) and Kita (US
`
`2017/0045787).
`
`Re claim 1, Yamazaki et al. teaches a liquid crystal display panel (Fig. 1-19, [0075-0190]) having a
`
`plurality of pixels (PIX in Fig. 1-5, [0078]) arranged in a matrix (Fig. 1) comprising:
`
`a plurality of pixel electrodes (21 in Fig. 1-5, [0078], Fig. 9, [0135]) provided in a corresponding
`
`one of the plurality of pixels (PIX in Fig. 1, [0078]); and
`
`a plurality of pairs of first video signal lines (SLL Fig. 1, [0081], Fig. 2-5) and second video signal
`
`lines (SLR in Fig.1, [0081], Fig. 2-5) provided at a corresponding boundary (Fig. 1-5) between two pixels
`
`adjacent to each other (Fig. 1-5) in a first direction (the horizontal direction in Fig. 1-5), the plurality of
`
`pairs of the first video signal lines (SLL Fig. 1, [0081], Fig. 2-5) and the second video signal lines (SLL Fig.
`
`1, [0081], Fig. 2-5) extending in a second direction (the vertical direction in Fig. 1-5) crossing to the first
`
`direction (the horizontal direction in Fig. 1-5),
`
`wherein at least a part (Fig. 1-5) of the pixel electrode (21 in Fig. 1, [0078], Fig. 3-5, Fig. 9) exists
`
`between a first video signal line (the SZ/SLR overlapping 21 in Fig. 1-5, [0095]) of a pair (Fig. 1-5) of the
`
`plurality of pairs of first video signal lines (Fig. 1-5) and second video signal lines (Fig. 1-5) and a second
`
`video signal line (the adjacent Sl/SLL between two neighboring pixels in Fig. 1-5, [0095]) of the pair (Fig.
`
`1-5) of the plurality of pairs (Fig. 1-5) of first video signal lines (Fig. 1-5) and second video signal lines
`
`(Fig. 1-5).
`
`

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`Application/Control Number: 16/154,300
`Art Unit: 2871
`
`Page 10
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`Yamazaki et al. teaches that the first video signal line (the SZ/SLR overlapping 21 in Fig. 1-5,
`
`[0095]) is overlapping a pixel electrode (Fig. 1-5) and located at a middle portion of the pixel (Fig. 1-5)
`
`and the second video signal line (the adjacent Sl/SLL between two pixels in Fig. 1-5, [0095]) is located at
`
`the boundary between two adjacent pixels (Fig. 1-5). Yamazaki et al. does not teach that each pixel
`
`electrode includes a plurality of line electrodes, at least one of the plurality of line electrodes exists
`
`between the first video signal line and the second video signal line, and an interval between two
`
`adjacent pixel electrodes is equal to an interval between two adjacent line electrodes in one pixel
`
`electrode.
`
`Matsushima teaches that (Fig. 12, Fig. 4, 8 and 11) each pixel electrode (E1 in Fig. 12, Fig. 4, 8
`
`and 11, [0097, 0037]) includes a plurality of line electrodes (40 in Fig. 12, Fig. 4, 8 and 11, [0098, 0048]),
`
`and at least one of the plurality of line electrodes (40 in Fig. 12, Fig. 4, 8 and 11, [0098, 0048]) exists
`
`between a middle portion of the pixel (Fig. 12, Fig. 4, 8 and 11) and a second video signal line (S/Sl/SZ in
`
`Fig. 12, Fig. 4, 8 and 11, [0070]) at the boundary between two adjacent pixels (Fig. 12, Fig. 4, 8 and 11).
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that each pixel electrode includes a plurality of line electrodes, and at
`
`least one of the plurality of line electrodes exists between a middle portion of the pixel and a second
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`video signal line at the boundary between two adjacent pixels as taught by Matsushima for the system
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`of Yamazaki et al. such that each pixel electrode includes a plurality of line electrodes, and at least one
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`of the plurality of line electrodes exists between the first video signal line and the second video signal
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`line of the system of Yamazaki et al. since this would help to provide a high-speed response mode type
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`of liquid crystal display device which can improve a display quality (Matsushima, [0027]).
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`Matsushima also teaches that (Fig. 7, 9, 10, [0068, 0077]) an interval (Dmin in Fig. 7, 9, 10,
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`[0068, 0077]) between two adjacent pixel electrodes (Fig. 7, 9, 10, [0068, 0077]) is 5 pm ([0068, 0077,
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`0025], Dmin=5 um).
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`Kita teaches that (Fig 1, [0088, 0053], 5:5 um) an interval (S in Fig 1, [0088, 0053], 5:5 um)
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`between two adjacent line electrodes (Fig. 1) in one pixel electrode (Fig. 1) is 5 pm (Fig 1, [0088, 0053],
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`5:5 um).
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`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that an interval between two adjacent pixel electrodes is 5 pm as
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`taught by Matsushima and employ that an interval between two adjacent line electrodes in one pixel
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`electrode is 5 pm as taught by Kita for the system of Yamazaki et al. in view of Matsushima such that an
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`interval between two adjacent pixel electrodes is equal to an interval between two adjacent line
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`electrodes in one pixel electrode since this would help to provide a high-speed response mode type of
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`liquid crystal display device which can improve a display quality (Matsushima, [0027]), and it helps that
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`occurrence of flickers can be suppressed when low frequency driving is performed in a liquid crystal
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`display device of a transverse electric field mode (Kita, [0033, 0089]).
`
`Re claims 2I 15, Yamazaki et al. also teaches the following structures:
`
`0
`
`(Claim 2) a plurality of scanning lines (GL/Gl/GZ in Fig. 1-5, [0076]), each of which is disposed at
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`a boundary between corresponding two pixels adjacent to each other (Fig. 1-5) in the second
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`direction (the vertical direction in Fig. 1-5) and extends in the first direction (the horizontal
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`direction in Fig. 1-5); and a plurality of transistors (TFTs 30 in Fig. 1-5, [0101]), formed in a
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`corresponding one of the plurality of pixels (PIX in Fig. 1-5, [0078]), wherein gate electrodes
`
`([0101], Fig. 1-5) of the plurality of transistors (TFTs 30 in Fig. 1-5, [0101]) are connected to a
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`corresponding one of the plurality of scanning lines (GL/Gl/GZ in Fig. 1-5, [0076]), first
`
`conductive electrodes (the drain electrode of TFTs in Fig 1-5, [0101-0102]) of the plurality of
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`transistors (TFTs 30 in Fig. 1-5, [0101]) are connected to a corresponding one of the plurality of
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`pixel electrodes (21 in Fig. 1-5, [0078]), each two of the plurality of scanning lines (GL/Gl/GZ in
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`Fig. 1-5, [0076]) are connected to each other (Fig. 1-2, [0076]), a second conductive electrode
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`(the source electrode of TFTs connected to the SZ/SLR in Fig 1-5, [0101-0102]) of a transistor
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`(the TFT 30 connected to the SZ/SLR in Fig. 1-5, [0101]) connected to one of the connected two
`
`scanning lines (GL/Gl/GZ in Fig. 1-5, [0076]) is connected to one of the first video signal line (the
`
`SZ/SLR overlapping 21 in Fig. 1-5, [0095]) and the second video signal line (the adjacent Sl/SLL
`
`between two pixels in Fig. 1-5, [0095]), and a second conductive electrode (the source electrode
`
`of TFTs connected to the Sl/SLL in Fig 1-5, [0101-0102]) of a transistor (the TFT 30 connected to
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`the Sl/SLL in Fig. 1-5, [0101]) connected to the other of the two connected scanning lines (Fig. 3,
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`5 and 21, [0113, 0266]) is connected to the other of the first video signal line (the SZ/SLR
`
`overlapping 21 in Fig. 1-5, [0095]) and the second video signal line (the adjacent Sl/SLL between
`
`two pixels in Fig. 1-5, [0095]).
`
`0
`
`(Claim 15) the first video signal line (the SZ/SLR overlapping 21 in Fig. 1-5, [0095]) and the
`
`second video signal line (the adjacent Sl/SLL between two pixels in Fig. 1-5, [0095]) are covered
`
`(Fig. 4B and Fig. 6, [0112, 0114, 0121]) with a light shielding layer (Fig. 4B and Fig. 6, [0112,
`
`0114, 0121]) formed along (Fig. 4B and Fig. 6, [0112, 0114, 0121]) the second direction (the
`
`vertical direction in Fig. 1-5).
`
`Re claim 5, Yamazaki et al. does not teach that the plurality of line electrodes extend in the
`
`second direction.
`
`Matsushima teaches that (Fig. 12) the plurality of line electrodes (40 in Fig. 12, [0098]) extend in
`
`the second direction (the vertical direction in Fig. 12).
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that the plurality of line electrodes extend in the second direction as
`
`taught by Matsushima for the system of Yamazaki et al. in view of Matsushima and Kita since this would
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`help to provide a high-speed response mode type of liquid crystal display device which can improve a
`
`display quality (Matsushima, [0027]).
`
`Re claim 6, Yamazaki et al. does not teach that each pixel electrode further includes a
`
`connection electrode connecting the plurality of line electrodes.
`
`Matsushima teaches that (Fig. 12, Fig. 4, 8 and 11) each pixel electrode (E1 in Fig. 12, Fig. 4, 8
`
`and 11, [0037, 0097]) further includes a connection electrode (30 in Fig. 12, Fig. 4, 8 and 11, [0048])
`
`connecting the plurality of line electrodes (40 in Fig. 12, Fig. 4, 8 and 11, [0048, 0098]).
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that each pixel electrode further includes a connection electrode
`
`connecting the plurality of line electrodes as taught by Matsushima for the system of Yamazaki et al. in
`
`view of Matsushima and Kita since this would help to provide a high-speed response mode type of liquid
`
`crystal display device which can improve a display quality (Matsushima, [0027]).
`
`Re claim 8, Yamazaki et al. teaches that a first pixel electrode (the second 21 in the first row of
`
`21 in Fig. 1, [0078], Fig. 2-4) and a second pixel electrode (the first 21 in the first row of 21 in Fig. 1,
`
`[0078], Fig. 2-4) among the plurality of pixel electrodes (21 in Fig. 1-5, [0078]) are adjacent to each other
`
`(Fig. 1-4) in the first direction (the horizontal direction in Fig. 1-5), the first video signal line (the SZ/SLR
`
`overlapping 21 in Fig. 1-5, [0095]) overlaps a middle portion (Fig. 1-5) of the second pixel electrode (the
`
`first 21 in the first row of 21 in Fig. 1, [0078], Fig. 2-4) in planar view (Fig. 1-5), and the second video
`
`signal line (the adjacent Sl/SLL between two neighboring pixels in Fig. 1-5, [0095]) is located between
`
`the first pixel electrode (the second 21 in the first row of 21 in Fig. 1, [0078], Fig. 2-4) and the second
`
`pixel electrode (the first 21 in the first row of 21 in Fig. 1, [0078], Fig. 2-4) in planar view (Fig. 1-5).
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`Yamazaki et al. does not teach that a middle portion of the second pixel electrode in planar view is the
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`line electrode of the second pixel electrode.
`
`Matsushima teaches that (Fig. 12, Fig. 4, 8 and 11) teaches that a middle portion (Fig. 12, Fig. 8
`
`and 11) of the second pixel electrode (Fig. 12, Fig. 4, 8 and 11, [0048, 0098]) in planar view is the line
`
`electrode (Fig. 12, Fig. 4, 8 and 11) of the second pixel electrode.
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that a middle portion of the second pixel electrode in planar view is
`
`the line electrode of the second pixel electrode as taught by Matsushima for the system of Yamazaki et
`
`al. in view of Matsushima and Kita such that the first video signal line overlaps the line electrode of the
`
`second pixel electrode in planar view since this would help to provide a high-speed response mode type
`
`of liquid crystal display device which can improve a display quality (Matsushima, [0027]).
`
`Re claim 13, Yamazaki et al. teaches that an edge portion of the pixel electrode (the edge
`
`portion of the 21 between $2 and the left 51 in Fig. 3-4) between the first video signal line (the SZ/SLR
`
`overlapping 21 in Fig. 1-5, [0095]) and the second video signal line (the adjacent Sl/SLL between two
`
`pixels in Fig. 1-5, [0095]) is not covered (Fig. 3-4) with a light shielding layer (Fig. 4B and Fig. 6, [0112,
`
`0114, 0121]). Yamazaki et al. does not teach that the edge portion of the pixel electrode is the line
`
`electrode.
`
`Matsushima teaches that (Fig. 12) the edge portion of the pixel electrode (Fig. 12) is the line
`
`electrode (40 in Fig. 12, [0098]).
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that the edge portion of the pixel electrode is the line electrode as
`
`taught by Matsushima for the system of Yamazaki et al. in view of Matsushima and Kita such that the
`
`line electrode existing between the first video signal line and the second video signal line is not covered
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`with a light shielding layer since this would help to provide a high-speed response mode type of liquid
`
`crystal display device which can improve a display quality (Matsushima, [0027]).
`
`Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. in view of
`
`Matsushima and Kita as applied to claim 2 above, and in view of Ono et al. (US 2007/0252936).
`
`Re claim 3, Yamazaki et al. does not teach that at least two of the plurality of pixel electrodes
`
`and at least two of the plurality of transistors are formed in each of the plurality of pixels.
`
`Ono et al. teaches that (Fig. 1 and 7) at least two of the plurality of pixel electrodes (PX1 and PX2
`
`in Fig. 1 and 7, [0068, 0087, 0093-0095, 0125]) and at least two of the plurality of transistors (TFT1 and
`
`TF2 in Fig. 1 and 7, [0064]) are formed in each of the plurality