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`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and TrademarkOffice
`Address; COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`
`16/156,790
`
`10/10/2018
`
`Daisuke KAJITA
`
`20295 .0026US01
`
`7A07
`
`HAY
`
`M
`
`TLER!
`
`HAMRE, SCHUMANN, MUELLER & LARSON P.C.
`45 South Seventh Street
`Suite 2700
`MINNEAPOLIS, MN 55402-1683
`
`GROSS, ALEXANDERP
`
`2871
`
`PAPER NUMBER
`
`NOTIFICATION DATE
`
`DELIVERY MODE
`
`08/23/2021
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
`following e-mail address(es):
`PTOMail @hsml.com
`
`PTOL-90A (Rev. 04/07)
`
`

`

`
`
`Disposition of Claims*
`1-4,6-17 and 19-22 is/are pending in the application.
`)
`Claim(s)
`5a) Of the above claim(s) ___ is/are withdrawn from consideration.
`C] Claim(s)__ is/are allowed.
`Claim(s) 1-4,6-17 and 19-22 is/are rejected.
`(1 Claim(s)__is/are objectedto.
`C} Claim(s)
`are subjectto restriction and/or election requirement
`* If any claims have been determined allowable, you maybeeligible to benefit from the Patent Prosecution Highway program at a
`participating intellectual property office for the corresponding application. For more information, please see
`http://www.uspto.gov/patents/init_events/pph/index.jsp or send an inquiry to PPHfeedback@uspto.gov.
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`) ) ) )
`
`Application Papers
`10) The specification is objected to by the Examiner.
`11)0) The drawing(s) filedon__ is/are: a)(J accepted or b)() objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`12)1) Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d)or (f).
`Certified copies:
`c)Z None ofthe:
`b)() Some**
`a)C All
`1.2 Certified copies of the priority documents have been received.
`2.1.) Certified copies of the priority documents have been received in Application No.
`3.1.) Copies of the certified copies of the priority documents have been receivedin this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`* See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`1)
`
`Notice of References Cited (PTO-892)
`
`2) (J Information Disclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`Paper No(s)/Mail Date
`U.S. Patent and Trademark Office
`
`3) (J Interview Summary (PTO-413)
`Paper No(s)/Mail Date
`(Qj Other:
`
`4)
`
`PTOL-326 (Rev. 11-13)
`
`Office Action Summary
`
`Part of Paper No./Mail Date 20210818
`
`Application No.
`Applicant(s)
`16/156,790
`KAJITA, Daisuke
`
`Office Action Summary Art Unit|AIA (FITF) StatusExaminer
`ALEXANDER P GROSS
`2871
`Yes
`
`
`
`-- The MAILING DATEofthis communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLYIS SET TO EXPIRE 3 MONTHS FROM THE MAILING
`DATE OF THIS COMMUNICATION.
`Extensions of time may be available underthe provisions of 37 CFR 1.136(a). In no event, however, may a reply betimely filed after SIX (6) MONTHSfrom the mailing
`date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHSfrom the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133}.
`Any reply received by the Office later than three months after the mailing date of this communication, evenif timely filed, may reduce any earned patent term
`adjustment. See 37 CFR 1.704(b).
`
`Status
`
`1) Responsive to communication(s) filed on 06/04/2021.
`C} A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/werefiled on
`2a)¥) This action is FINAL.
`2b) (J This action is non-final.
`3)02 An election was madeby the applicant in responseto a restriction requirement set forth during the interview
`on
`; the restriction requirement and election have been incorporated into this action.
`4\0) Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Exparte Quayle, 1935 C.D. 11, 453 O.G. 213.
`
`

`

`Application/Control Number: 16/156,790
`Art Unit: 2871
`
`Page 2
`
`DETAILED ACTION
`
`Notice of Pre-AIA or AIA Status
`
`The present application, filed on or after March 16, 2013, is being examined underthe
`
`first inventor to file provisions of the AJA.
`
`Claim Rejections - 35 USC § 103
`
`The following is a quotation of 35 U.S.C. 103 which formsthe basis for all obviousness
`
`rejectionsset forth in this Office action:
`
`A patent for a claimed invention maynot be obtained, notwithstanding that the claimed invention is not
`identically disclosed as set forth in section 102, if the differences between the claimed invention and the
`prior art are such that the claimed invention as a whole would have been obvious before the effective
`filing date of the claimed invention to a person having ordinaryskill in the art to which the claimed
`invention pertains. Patentability shall not be negated by the mannerin which the invention was made.
`
`Claims 1 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Um et
`
`al. (US Pub. 20070035675 and hereafter Um) in view of Morishimaet al. (US Pub.
`
`20150153598 and hereafter Morishima) and Tsurumaet al. (US Pub. 20110211145 and
`
`hereafter Tsuruma).
`
`Asperclaim 1, Um teaches(in figures 1-6) a liquid crystal display panel having a
`
`plurality of pixels arranged in a matrix (paragraph 33), comprising: a plurality of pixel electrodes
`
`(191a and 191b) and a plurality of transistors (Q forms two transistors see paragraph 86)
`
`providedin one ofthe plurality of pixels (shown in figures 2 and 3); a commonelectrode (131)
`
`that is opposedto the plurality of pixel electrodes (191a1-191a4 and 191b1-191b4) in the one of
`
`the plurality of pixels; a plurality of scanning lines (121) extendingin a first direction (horizontal
`
`direction as shownin figure 3), including a first scanning line (lower scanning line 121 shownin
`
`figure 3) and a second scanning line (upper scanning line 121 shownin figure 3) being adjacent
`
`to the first scanning line; and a plurality of video signal lines (171) extending in a second
`
`direction (vertical direction as shownin figure 3) crossing the first direction, includinga first
`
`

`

`Application/Control Number: 16/156,790
`Art Unit: 2871
`
`Page 3
`
`video signalline (right video signal line 171 in figure 3) and a second videosignalline (left
`
`video signal line 171 in figure 3) being adjacentto the first video signal line, wherein in each of
`
`the plurality of pixels, a corresponding oneofthe plurality of scanning lines is connected to the
`
`plurality of transistors, in each of the plurality of pixels a corresponding oneofthe plurality of
`
`video signal lines is connected to the plurality of transistors in the one of the plurality of pixels
`
`defined by the first scanning line, the second scanningline, the first video signal line and the
`
`second videosignalline, the plurality of pixel electrodes and the plurality of transistors are
`
`arranged in the first direction, the plurality of pixel electrodes includesa first pixel electrode
`
`(191b) and a second pixel electrode (19 1a), the first pixel electrode is located adjacent to the
`
`second pixel electrode in the first direction, the first pixel electrodeis electrically connected to
`
`the first video signal line (through thefirst transistor formed by TFT Q), the second pixel
`
`electrode is electrically connected to the first video signal line (through the second transistor
`
`formed by TFT Q) each pixel electrode includesa plurality of line electrodes (191al-191a4 and
`
`191b1-191b4) extending in a second direction (vertical direction as shownin figure 3), a
`
`plurality of slits are formed in each pixel electrode (gaps between branchelectrodes).
`
`Um doesnot specifically teach a metal piece that is provided betweenatleast one of the
`
`plurality of pixel electrodes and the commonelectrodein the at least one of the plurality of
`
`pixels, wherein the metal piece electrically connected to the commonelectrode, and an entirety
`
`of the metal piece overlaps with one of the plurality of pixel electrodes in planar view orthat in
`
`at least one of the plurality of pixel electrode electrodes, a first interval between thefirst pixel
`
`electrode and the second pixel electrode in the first direction is equal to a second interval
`
`between the two adjacent line electrodesin thefirst direction.
`
`

`

`Application/Control Number: 16/156,790
`Art Unit: 2871
`
`Page 4
`
`However, Morishima teaches(in figures 1 and 6) providing a metal piece (11b) between
`
`a pixel electrode (13) and a commonelectrode (10), wherein the metal piece electrically
`
`connected to the commonelectrode (see figure 1 and paragraph 27), and an entirety of the metal
`
`piece overlaps with one pixel electrode in planar view (see paragraph 29 and figure 6) in order to
`
`enhancethereliability of defective pixel correction (paragraph 32).
`
`Tsurumateaches(in figures 1-2 and 25-26) forminga first interval (interval betweenleft
`
`and right pixel electrodes 14 shown asthe S2 to the right of the label L in figure 25) between a
`
`first pixel electrode (left pixel electrode 14 shownin figure 25) and the second pixel electrode
`
`(right pixel electrode 14 shownin figure 25) in the first direction to be equal to a secondinterval
`
`(interval between line electrodesof the left pixel electrode 14 shownin figure 25 and shownas
`
`the S2 to the left of the label L) between the two adjacentline electrodes (see figures and
`
`paragraph 67) in the first direction (see paragraph 137) in order to reduce flickering and prevent
`
`burn in (see paragraph 138).
`
`It would have been obvious to one of ordinary skill in the art at the time of filing to
`
`modify the device of Um to include the metal piece as suggested by Morishima and to havethe
`
`spacing as suggested by Tsuruma.
`
`The motivation to include the metal piece would have been to enhancethereliability of
`
`defective pixel correction as taught by Morishima(paragraph 32). The motivation to modify the
`
`spacing would havebeen to reduce flickering and prevent burn in as taught by Tsuruma(see
`
`paragraph 138).
`
`Asperclaim 13, Um teaches(in figure 3) that a shape ofat least one of the plurality of
`
`pixel electrodes (191a1-191a4) is different from a shape of the other pixel electrodes (191b1-
`
`191b4).
`
`

`

`Application/Control Number: 16/156,790
`Art Unit: 2871
`
`Page 5
`
`Claims 2-4, 8-10, and 20 are rejected under 35 U.S.C. 103 as being unpatentable
`
`over Um et al. (US Pub. 20070035675 and hereafter Um), Morishimaet al. (US Pub.
`
`20150153598 and hereafter Morishima), and Tsurumaet al. (US Pub. 20110211145 and
`
`hereafter Tsuruma)as applied to claim 1 aboveandin further view of Ono et al. (US Pub.
`
`20070252936 and hereafter Ono).
`
`Asperclaim 2, Um teaches(in figures 1-6) a video signal line (171) that is provided at a
`
`boundary portion between twoofthe plurality of pixels adjacent to each otherin thefirst
`
`direction and extends in a second direction; and a lead line (173) that connects the video signal
`
`line and the plurality of transistors in the at least one of the plurality of pixels, wherein the lead
`
`line includes a commonlead line (173) that extendsin the first direction from the video signal
`
`line.
`
`Um doesnotspecifically teach a plurality of first individual lead lines that are connected
`
`to the commonlead line and respective first conductive electrodes of the plurality of transistors.
`
`However, Onoteaches(in figures 10-12) that forming a lead line (shown as R1-R3 in the
`
`annotated figure below) including a commonlead line (shown as R1 in the annotated figure
`
`below) which extendsin a first direction (x direction) from a video signal line (DL) and a
`
`plurality of first individual lead lines (shown as R2 and R3in the annotated figure below) that
`
`are connected to the commonlead line and respective first conductive electrodes (portions of
`
`SD11 and SD22 overlapping the GL)of the plurality of transistors was an art recognized
`
`equivalent structure knownin theart at the time offiling to connect a video signal line to a
`
`plurality of transistors.
`
`

`

`Application/Control Number: 16/156,790
`Art Unit: 2871
`
`Page 6
`
`Therefore it would have been obvious to one of ordinary skill in the art at the time of
`
`filing to replace the lead line structure in Um with the lead line structure taught by Ono as a
`
`matter of design choice.
`
`Annotated figure from Onoetal. (US Pub. 20070252936)
`
`FIG, 10
`
`spit —£
`
` TETMarS}
`
`Asperclaim 3, Um in view of Onoteachesthatat least a part of a first individual lead
`
`line (shownas R2 in the annotated figure above) amongthe plurality offirst individual lead lines
`
`(shown as R2 and R3 in the annotated figure above) does not overlap another conductive
`
`member(pixel electrode) in planar view.
`
`Asperclaim 4, Um in view of Onoteaches that the commonlead line (shown as R1 in
`
`the annotated figure above) does not overlap the scanning line in planar view (GL in Ono
`
`corresponding to 121 in Um).
`
`

`

`Application/Control Number: 16/156,790
`Art Unit: 2871
`
`Page 7
`
`Asperclaim 8, Um doesnotteach a light shielding layer that covers the lead line and the
`
`scanningline.
`
`However, Onoteaches(in figures 2A-4 and 10-12) providing a light shielding layer (BM)
`
`that covers the lead line (shown as R1-R3in the annotated figure above) and the scanning line
`
`(GL) (see figure 3 and paragraph 106).
`
`It would have been obvious to one of ordinary skill in the art at the time offiling to
`
`include the light shielding layer from Um in the device of Ono.
`
`The motivation would have been to reduce light leakage between pixels.
`
`Asperclaim 9, Um teaches(in figures 1-6) a plurality of second individuallead lines
`
`(192b1 and 192a1) that connects each ofthe plurality of pixel electrodes (191al-191a4 and
`
`191b1-191b4) and each of second conductive electrodes (175a and 175b)of the plurality of
`
`transistors, respectively.
`
`Asperclaim 10, Um teaches(in figures 1-6) that at least a part of a second individual
`
`lead line (192b1 and 192a1) amongthe plurality of second individuallead lines does not overlap
`
`with another conductive member(124) in planar view.
`
`Asperclaim 20, Um teaches(in figures 1-6) that the plurality of second individual lead
`
`lines (192b1 and 192a1) are madeof the same material as a material of the pixel electrode
`
`(191al-191a4 and 191b1-191b4) and formed in a layer identical to that of the pixel electrode.
`
`Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Um et
`
`al. (US Pub. 20070035675 and hereafter Um), Morishimaet al. (US Pub. 20150153598 and
`
`hereafter Morishima), Tsurumaet al. (US Pub. 20110211145 and hereafter Tsuruma), and
`
`Onoet al. (US Pub. 20070252936 and hereafter Ono) as applied to claim 1 above and in
`
`further view of Saitoh et al. (US Pub. 20180204853 and hereafter Saitoh).
`
`

`

`Application/Control Number: 16/156,790
`Art Unit: 2871
`
`Page 8
`
`Asperclaim 6, Um in view of Morishima teaches a common line (125 in Um)and the
`
`metal piece (11b from Morishima).
`
`Um in view of Morishima doesnot specifically teach that the commonline is provided
`
`above the commonelectrode and extendsin the second direction wherein the metal piece is
`
`formed in a layer identical to that of the commonline.
`
`However, Saitoh teaches(in figures 8-10) teaches forming commonlines (20b) to extend
`
`in a second direction (parallel with data lines) directly on the commonelectrodes (27b) and
`
`providing a lowerinsulation layer (24) below the commonelectrode, an upper insulation layer
`
`(9) above the commonlines, and driver electrodes (36) extending in a first direction (parallel
`
`with the gate lines) in order to provide touch functionality to the display (paragraph 143).
`
`Additionally, Morishima teaches forming the metal piece (11b) directly on the common
`
`electrode (10) in a layer identical to that of a commonline (11) such that the metal piece and the
`
`commonline can be formed in the same process (paragraph 29).
`
`It would have been obvious to one of ordinary skill in the art at the time offiling to
`
`modify the common electrode and commonline and include the driver electrodes and insulation
`
`layers as suggested by Saitoh in the device of Um.
`
`The motivation to modify the commonline and include the driver electrodes and
`
`insulating layer would have been to provide touch functionality to the display.
`
`Asperclaim 7, Um in view of OnoandSaitoh teachesan insulating layer (24 from
`
`Saitoh) provided between the plurality of transistors (Q in Um as modified by Ono) and the
`
`plurality of pixel electrodes (191al-191a4 and 191b1-191b4 in Um), wherein a plurality of
`
`contact holes (185a and 185b in Um corresponding to 6p in Saitoh) are providedin the insulating
`
`layer, the plurality of transistors and the plurality of pixel electrodes are respectively connected
`
`

`

`Application/Control Number: 16/156,790
`Art Unit: 2871
`
`Page 9
`
`to each other throughthe plurality of contact holes, and a first individual lead line (shown as R2
`
`in the annotated figure above) amongtheplurality of first individual lead lines (shown as R2 and
`
`R3 in the annotated figure above) is provided between two adjacent contact holes in a planar
`
`view (185a to the right of 185b and 185a to the left of 185b).
`
`Um does not teach a laminated film having an island shapeis formed onthe insulating
`
`layer around a contact hole amongthe plurality of contact holes, the laminated film includes a
`
`first film formed in a layer identical to that of the common electrode and a secondfilm thatis
`
`laminated onthefirst film and formed in the layer identical to that of the commonline, and a
`
`first individual lead line amongthe plurality of first individual lead lines is provided between
`
`two adjacent laminated films in a planar view.
`
`However, Saitoh teaches(in figures 7-10) providing a laminated film (4) having an island
`
`shape on an insulating layer (6) around a contact hole (104), the laminated film includesa first
`
`film (27a) formed in a layer identical to that of the commonelectrode (27b) and a secondfilm
`
`(20a) that is laminated onthefirst film and formedin the layer identical to that of the common
`
`line (20b).
`
`It would have been obvious to one of ordinary skill in the art at the time offiling to
`
`include the laminated film from Saitoh for each of the transistors in Um.
`
`The motivation to include the laminated film would have been to prevent braking of the
`
`pixel electrode and an increase in contact resistance as taught by Saitoh (paragraph 127).
`
`Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Um et al. (US
`
`Pub. 20070035675 and hereafter Um), Morishimaet al. (US Pub. 20150153598 and
`
`hereafter Morishima), and Tsurumaet al. (US Pub. 20110211145 and hereafter Tsuruma)
`
`

`

`Application/Control Number: 16/156,790
`Art Unit: 2871
`
`Page 10
`
`as applied to claim 1 above anin further view of Im et al. (US Pub. 20160216549 and
`
`hereafter Im).
`
`Asperclaim 11, Um doesnot specifically teach a width of each of the plurality of pixel
`
`electrodesis less than or equal to 200 um.
`
`However, Im teaches(in figure 3) that the width of a pixel electrode (191) is between 60
`
`um to 120 um (see paragraph 112).
`
`Additionally the width of a pixel electrode is a result effective variable in that if the width
`
`is too large display resolution will be lowered and if the width is too small cost and
`
`manufacturing difficulty will increase.
`
`Therefore, It would have been obvious to one having ordinary skill in the art at the time
`
`the invention wasfiled to set the width of each ofthe plurality of pixel electrodes to be less than
`
`or equal to 200 um,since it has been held that discovering an optimum valueofa result effective
`
`variable involves only routine skill in the art. (See MPEP § 2144.05 (ID (A) and (B))
`
`Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Um et al. (US
`
`Pub. 20070035675 and hereafter Um), Morishimaet al. (US Pub. 20150153598 and
`
`hereafter Morishima), and Tsurumaet al. (US Pub. 20110211145 and hereafter Tsuruma)
`
`as applied to claim 1 above anin further view of Shin et al. (US Pub. 20080231779 and
`
`hereafter Shin).
`
`Um doesnotspecifically teach assuming that CPIX is the pixel capacitance of the pixel
`
`electrode and that Cgs is the capacitance between a gate and a sourceofthe transistor, CPIX/Cgs
`
`indicating a pixel capacitanceratio is within +10% for all of the plurality of pixel electrodes and
`
`the plurality of transistors in each of the plurality of pixels.
`
`

`

`Application/Control Number: 16/156,790
`Art Unit: 2871
`
`Page 11
`
`However, Shin teaches(in figure 5) setting CPix/Cgs for each pixel to be equal (see
`
`paragraph 72 and equation 1 in paragraph 54) by compensating for differences in pixel electrode
`
`capacitance (Clc) by changing the gate-source capacitance (Cgs) by forming pixel electrodes
`
`(130) of different sizes (paragraph 52) to have different overlapping areas of a corresponding
`
`source electrode and a corresponding gate electrode (see paragraphs 71-72) in order to ensure
`
`uniform brightness between the pixel electrodes (paragraph 53).
`
`It would have been obvious to one of ordinary skill in the art at the timeoffiling to
`
`modify the device of Um suchthat the value of Cpix/Cgsis the samefor each pixel electrode and
`
`corresponding TFT.
`
`The motivation would have been to ensure uniform brightness between the pixel
`
`electrodes as suggested by Shin (paragraph 53).
`
`Claims 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Umetal.
`
`(US Pub. 20070035675 and hereafter Um), Morishimaet al. (US Pub. 20150153598 and
`
`hereafter Morishima), and Tsurumaet al. (US Pub. 20110211145 and hereafter Tsuruma)
`
`as applied to claim 1 above andin further view of Oh et al. (US Pub. 20170192329 and
`
`hereafter Oh) and Chungetal. (US Pub. 20070126460 and hereafter Chung).
`
`Asperclaim 14, Um doesnot teach a connection piece for electrically connecting two
`
`adjacent pixel electrodes amongthe plurality of pixel electrodes.
`
`However, Chung teaches(in figures 7 and 8) forming a connection piece (74) for
`
`electrically connecting two adjacent pixel electrodes (73A and 73B).
`
`Additionally, Oh teaches (in figure 4) providing notches (OP1 and OP2) in the common
`
`electrode (CE) at locations (CNT2 and CNT1) where the metal layer (“third conductive material
`
`layer” see paragraph 119) comprising the pixel electrode (PE) is to be connected to metal layers
`
`

`

`Application/Control Number: 16/156,790
`Art Unit: 2871
`
`Page 12
`
`(“first conductive material layer” see paragraph 109 and “gate conductive layer” see paragraph
`
`107) formed below the commonelectrode in order to prevent short circuits with the common
`
`electrode (paragraph 89).
`
`It would have been obvious to one of ordinary skill in the art at the time offiling to
`
`include the connection pieces from Chung in the device of Um and provide notchesin the
`
`commonelectrode corresponding to the connection pieces as suggested by Oh.
`
`The motivation would have been to provide a meansofrepairing a pixel with a defective
`
`transistor while preventing short circuit with the commonelectrode.
`
`Asperclaim 15, Um in view of Chung and Ohteachesthat the connection piece (74
`
`from Chung) overlaps a part of each of the two adjacent pixel electrodes (see figure 7 and
`
`paragraph 91 in Chung) in planar view but does not overlap the common electrode opposed to
`
`the pixel electrode in planar view (notch in the commonelectrode taught by Oh in paragraph 89).
`
`Asperclaim 16, Um in view of Chung and Ohteachesa notch (notch in the common
`
`electrode taught by Oh in paragraph 89) is formed in the commonelectrode and overlaps the
`
`connection piece in planar view (74 from Chung).
`
`Asperclaim 17, Oh in view of Chung teaches the connection piece (74 from Chung) is
`
`formed in a layer identical to that of a first conductive electrode and a second conductive
`
`electrode (the source electrode and the drain electrode) of the transistor (see paragraph 90 in
`
`Chung).
`
`Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Um et al. (US
`
`Pub. 20070035675 and hereafter Um), Morishimaet al. (US Pub. 20150153598 and
`
`hereafter Morishima), Tsurumaet al. (US Pub. 20110211145 and hereafter Tsuruma), Ono
`
`et al. (US Pub. 20070252936 and hereafter Ono) and Saitoh et al. (US Pub. 20180204853
`
`

`

`Application/Control Number: 16/156,790
`Art Unit: 2871
`
`Page 13
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`and hereafter Saitoh) as applied to claim 7 above andin further view of Lim et al. (US Pub.
`
`20150316825 and hereafter Lim).
`
`Asperclaim 19, Um doesnot teach that the plurality of contact holes overlap with the
`
`scanning line in planar view.
`
`However, Lim teaches(in figures 4-5 and 7A-7B) forming contact holes (442a) to
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`overlap with the scanning line (410a) in planar view (paragraph 89) in order to increase the
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`openingratio of the pixel (see paragraphs 113-114).
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`It would have been obvious to one of ordinary skill in the art at the timeoffiling to
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`modify the device of Um suchthat the contact holes overlap with the scanningline.
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`The motivation would have been to increase the openingratio of the pixel.
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`Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Um et al. (US
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`Pub. 20070035675 and hereafter Um) in view of Morishimaet al. (US Pub. 20150153598
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`and hereafter Morishima).
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`Asperclaim 22, Um teaches(in figures 1-6) a liquid crystal display panel having a
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`plurality of pixels arranged in a matrix (paragraph 33), comprising: a plurality of pixel electrodes
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`(191a and 191b) and a plurality of transistors (Q forms two transistors see paragraph 86)
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`providedin one ofthe plurality of pixels (shown in figures 2 and 3); a commonelectrode (131)
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`that is opposedto the plurality of pixel electrodes (191al1-191a4 and 191b1-191b4) in theat least
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`oneofthe plurality of pixels; a plurality of scanning lines (121) extendingin a first direction
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`(horizontal direction as shownin figure 3), including a first scanning line (lower scanning line
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`121 shownin figure 3) and a second scanning line (upper scanning line 121 shownin figure 3)
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`being adjacent to the first scanning line; and a plurality of video signal lines (171) extending in a
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`second direction (vertical direction as shownin figure 3) crossing the first direction, including a
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`

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`Application/Control Number: 16/156,790
`Art Unit: 2871
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`Page 14
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`first video signal line (right video signal line 171 in figure 3) and a second videosignalline (left
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`video signal line 171 in figure 3) being adjacentto the first video signal line, wherein in each of
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`the plurality of pixels, a corresponding oneofthe plurality of scanning lines is connected to the
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`plurality of transistors, in each of the plurality of pixels a corresponding oneofthe plurality of
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`video signal lines is connected to the plurality of transistors.
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`Um doesnot specifically teach a metal piece that is provided betweenatleast one of the
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`plurality of pixel electrodes and the commonelectrodein the at least one of the plurality of
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`pixels, wherein the metal piece electrically connected to the commonelectrode, and an entirety
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`of the metal piece overlaps with one ofthe plurality of pixel electrodes in planar view.
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`However, Morishima teaches(in figures 1 and 6) providing a metal piece (11b) between
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`a pixel electrode (13) and a commonelectrode (10), wherein the metal piece electrically
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`connected to the commonelectrode (see figure 1 and paragraph 27), and an entirety of the metal
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`piece overlaps with one pixel electrode in planar view (see paragraph 29 and figure 6) in order to
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`enhancethereliability of defective pixel correction (paragraph 32).
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`It would have been obvious to one of ordinary skill in the art at the time of filing to
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`modify the device of Um to include the metal piece as suggested by Morishima.
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`The motivation to include the metal piece would have been to enhancethereliability of
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`defective pixel correction as taught by Morishima(paragraph 32).
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`Response to Arguments
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`Applicant’s arguments, with respect to the rejection of claims 1-17 and 19-21 under
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`112(b) have been fully considered and are persuasive. The rejection under 35 U.S.C. 112(b) of
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`claims 1-4, 6-17, and 19-21 has been withdrawn.
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`

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`Application/Control Number: 16/156,790
`Art Unit: 2871
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`Page 15
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`Applicant’s arguments with respectto the rejection of claim(s) 1-4, 6-17, and 19-21
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`under 35 U.S.C. 103 have been considered but are moot because the new ground ofrejection
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`does not rely on any reference applied in the prior rejection of record for any teaching or matter
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`specifically challenged in the argument.
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`Conclusion
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`Applicant's amendment necessitated the new ground(s) of rejection presented in this
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`Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP§ 706.07(a).
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`Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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`A shortened statutory period for reply to this final action is set to expire THREE
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`MONTHSfrom the mailing date of this action. In the eventa first reply is filed within TWO
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`MONTHSofthe mailing date of this final action and the advisory action is not mailed until after
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`the end of the THREE-MONTHshortened statutory period, then the shortened statutory period
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`will expire on the date the advisory action is mailed, and any extension fee pursuant to 37
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`CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event,
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`however,will the statutory period for reply expire later than SIX MONTHSfrom the date ofthis
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`final action.
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`Any inquiry concerning this communication or earlier communications from the
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`examiner should be directed to ALEXANDER P GROSS whose telephone numberis (571)272-
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`5660. The examiner can normally be reached on Monday-Friday 9am-6pm EST.
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`Examinerinterviews are available via telephone, in-person, and video conferencing using
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`a USPTO supplied web-based collaboration tool. To schedule an interview, applicantis
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`encouraged to use the USPTO Automated Interview Request (AIR)at
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`http://www.uspto.gov/interviewpractice.
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`

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`Application/Control Number: 16/156,790
`Art Unit: 2871
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`Page 16
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`If attempts to reach the examinerby telephone are unsuccessful, the examiner’s
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`supervisor, Ed Glick can be reached on (571) 272-2490. The fax phone numberfor the
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`organization wherethis application or proceedingis assigned is 571-273-8300.
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`Information regarding the status of an application may be obtained from the Patent
`
`Application Information Retrieval (PAIR) system. Status information for published applications
`
`maybe obtained from either Private PAIR or Public PAIR. Status information for unpublished
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`applications is available through Private PAIR only. For more information about the PAIR
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`system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to
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`the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-
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`free). If you would like assistance from a USPTO Customer Service Representative or access to
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`the automated information system, call 800-786-9199 (IN USA OR CANADA)or 571-272-
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`1000.
`
`/ALEXANDER P GROSS/
`Examiner, Art Unit 2871
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`