www.uspto.gov
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and TrademarkOffice
`Address; COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`
`16/172,322
`
`10/26/2018
`
`Teruhisa Nakagawa
`
`20326.0147US01
`
`7080
`
`HAY
`
`M
`
`TLER
`
`HAMRE, SCHUMANN, MUELLER & LARSON P.C.
`45 South Seventh Street
`Suite 2700
`MINNEAPOLIS, MN 55402-1683
`
`ALMEIDA, CORY A
`
`2622
`
`PAPER NUMBER
`
`NOTIFICATION DATE
`
`DELIVERY MODE
`
`04/06/2021
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
`following e-mail address(es):
`PTOMail @hsml.com
`
`PTOL-90A (Rev. 04/07)
`
`

`

`
`
`Disposition of Claims*
`1,3-4,7-10,16-20 and 22-23 is/are pending in the application.
`)
`Claim(s)
`5a) Of the above claim(s) ___ is/are withdrawn from consideration.
`C] Claim(s)__ is/are allowed.
`Claim(s) 1,3-4,7-10,16-20 and 22-23 is/are rejected.
`(1 Claim(s)__is/are objectedto.
`C} Claim(s)
`are subjectto restriction and/or election requirement
`* If any claims have been determined allowable, you maybeeligible to benefit from the Patent Prosecution Highway program at a
`participating intellectual property office for the corresponding application. For more information, please see
`http://www.uspto.gov/patents/init_events/pph/index.jsp or send an inquiry to PPHfeedback@uspto.gov.
`
`) ) ) )
`
`Application Papers
`10) The specification is objected to by the Examiner.
`11)0) The drawing(s) filedon__ is/are: a)(J accepted or b)() objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`12)1) Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d)or (f).
`Certified copies:
`c)Z None ofthe:
`b)() Some**
`a)C All
`1.2 Certified copies of the priority documents have been received.
`2.1.) Certified copies of the priority documents have been received in Application No.
`3.1.) Copies of the certified copies of the priority documents have been receivedin this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`* See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`1)
`
`Notice of References Cited (PTO-892)
`
`2) (J Information Disclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`Paper No(s)/Mail Date
`U.S. Patent and Trademark Office
`
`3) (J Interview Summary (PTO-413)
`Paper No(s)/Mail Date
`(Qj Other:
`
`4)
`
`PTOL-326 (Rev. 11-13)
`
`Office Action Summary
`
`Part of Paper No./Mail Date 20210217
`
`Application No.
`Applicant(s)
`16/172,322
`Nakagawa, Teruhisa
`
`Office Action Summary Art Unit|AIA (FITF) StatusExaminer
`CORY A ALMEIDA
`2622
`Yes
`
`
`
`-- The MAILING DATEofthis communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLYIS SET TO EXPIRE 3 MONTHS FROM THE MAILING
`DATE OF THIS COMMUNICATION.
`Extensions of time may be available underthe provisions of 37 CFR 1.136(a). In no event, however, may a reply betimely filed after SIX (6) MONTHSfrom the mailing
`date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHSfrom the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133}.
`Any reply received by the Office later than three months after the mailing date of this communication, evenif timely filed, may reduce any earned patent term
`adjustment. See 37 CFR 1.704(b).
`
`Status
`
`1) Responsive to communication(s) filed on 12/23/20.
`C} A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/werefiled on
`2a)¥) This action is FINAL.
`2b) (J This action is non-final.
`3)02 An election was madeby the applicant in responseto a restriction requirement set forth during the interview
`on
`; the restriction requirement and election have been incorporated into this action.
`4\0) Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Exparte Quayle, 1935 C.D. 11, 453 O.G. 213.
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 2
`
`DETAILED ACTION
`
`The responsefiled 12/23/20 is entered. Claims 1, 7, 10, 16, and 22 are amended.
`
`Claims 2, 5, 6, 11-15, and 21 are canceled. Claims 1, 3, 4, 7-10, 16-20, 22, and 23 are
`
`pending.
`
`Notice of Pre-AlA or AIA Status
`
`1.
`
`The present application, filed on or after March 16, 2013, is being examined
`
`under the first inventor to file provisions of the AIA.
`
`Response to Arguments
`
`2.
`
`Applicant's arguments with respect to claims 1, 3, 4, 7-10, 16-20, 22, and 23
`
`have been considered but are believed to be answered by and therefore mootin view of
`
`new grounds ofrejection, as presented below.
`
`Claim Rejections - 35 USC § 103
`
`3.
`
`In the event the determination of the status of the application as subject to AIA 35
`
`U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103)is incorrect, any
`
`correction of the statutory basis for the rejection will not be considered a new ground of
`
`rejection if the prior art relied upon, and the rationale supporting the rejection, would be
`
`the same under either status.
`
`4.
`
`The following is a quotation of 35 U.S.C. 103 which forms the basis for all
`
`obviousnessrejections setforth in this Office action:
`
`A patent for a claimed invention may not be obtained, notwithstanding that the claimed
`invention is not identically disclosed as set forth in section 102, if the differences between the
`claimed invention and the prior art are such that the claimed invention as a whole would have
`been obvious before the effective filing date of the claimed invention to a person having
`ordinary skill in the art to which the claimed invention pertains. Patentability shall not be
`negated by the manner in which the invention was made.
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 3
`
`5.
`
`Claims 1, 3, 4, 7-10, 16-20, 22, and 23 is/are rejected under 35 U.S.C. 103 as
`
`being unpatentable over Liu, US-20170206843, in view of Tsubata, US-20090046212,
`
`and in further view of Shin, US-20120154700.
`
`6.
`
`In regards to claim 1, Liu discloses a liquid crystal display device (Par. 0009-
`
`0010 display device utilizing LCD) comprising: a first display panel (Fig. 3, 03 OLED
`
`display panel) comprising a plurality offirst gate lines extending in a first direction and
`
`arranged in a second direction thatis different from the first direction in a first display
`
`region of the first display panel (Fig. 3, O83 OLED display panel; Fig. 5, gate line SL
`
`which arranged vertically but extend horizontally), and a plurality of first data lines
`
`extending in the second direction and arrangedin the first direction in the first display
`
`region (Fig. 3, 03 OLED display panel; Fig. 5, data line DL which arranged horizontally
`
`but extend vertically), a secondliquid crystal display panel
`
`(Fig. 3, 01 LCD panel)
`
`comprising a plurality of second gate lines and a plurality of second data lines ina
`
`second display region of the second liquid crystal display panel, and a second liquid
`
`crystal (Fig. 3, 01 LCD panel; Fig. 5, data line DL and gate line SL; Par. 0076first pixel
`
`units of OLED and secondpixel units of LCD are arranged in 1:1 correspondence; Par.
`
`0082 liquid crystal layer); andafirst driving circuit for one or more of the plurality offirst
`
`gate lines and the plurality of first data lines, wherein the first driving circuit comprises
`
`one or morefirst gate drivers to provide signals to the one or more of the plurality of first
`
`gate lines and one or morefirst data drivers to provide signals to the one or more of the
`
`plurality of first data lines (Fig. 3, 03 OLED panel; Fig. 5, data line DL and gate line SL;
`
`drivers for DL data lines and SL gate lines), wherein the first display panel and the
`
`secondliquid crystal display panel overlap each other in plan view (Fig. 3, 03 OLED
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 4
`
`display panel and 01 LCD display panel; Par. 0076first pixel units of OLED and second
`
`pixel units of LCD are arranged in 1:1 correspondence).
`
`Liu does not disclose expresslyafirst liquid crystal display panel andafirst liquid
`
`crystal; two or more adjacent first gate lines from the plurality of first gate lines are
`
`provided with same signal at a same instant of time from the one or morefirst gate
`
`drivers, wherein two or more adjacent first data lines from the plurality offirst data lines
`
`are provided with same signals at a same instant of time from the one or morefirst data
`
`drivers, wherein the two or more adjacent first data lines from the plurality of first data
`
`lines are electrically connected to each other by a data lead connector, and wherein the
`
`data lead connector is formed outside the first display region, and connects between the
`
`two or more adjacent first data lines and one data terminal of the one or morefirst data
`
`drivers to receive the data signals for the two or more adjacent first data lines.
`
`Tsubata discloses utilizing two stacked liquid crystal display panels (Fig. 1; Par.
`
`0023) containing liquid crystal (Fig. 1, 226 liquid crystal).
`
`Before the effective filing date of the claimed invention, it would have been
`
`obvious to one of ordinary skill in the art that the two display panels of Liu can be LCD
`
`panels in the manner Tsubata discloses. The motivation for doing so would have been
`
`to provide an improved contrast ratio (Par. 0032).
`
`Liu and Tsubata do not disclose expressly two or more adjacent first gate lines
`
`from the plurality of first gate lines are provided with same signal at a same instant of
`
`time from the one or morefirst gate drivers, wherein two or more adjacent first data
`
`lines from the plurality of first data lines are provided with same signals at a same
`
`instant of time from the one or morefirst data drivers, wherein the two or more adjacent
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 5
`
`first data lines from the plurality of first data lines are electrically connected to each
`
`other by a data lead connector, and wherein the data lead connector is formed outside
`
`the first display region, and connects between the two or more adjacent first data lines
`
`and one data terminal of the one or morefirst data drivers to receive the data signals for
`
`the two or more adjacent first data lines.
`
`Shin discloses two or more adjacentfirst gate lines from the plurality offirst gate
`
`lines are provided with same signal at a same instant of time from the one or morefirst
`
`gate drivers (Fig. 1, GL1 and GL2 are provided with the samesignal from GL at a same
`
`time), wherein the two or more adjacent first gate lines from the plurality of first gate
`
`lines are electrically connected to each other by a gate lead connector (Fig. 1, GL gate
`
`line, i.e. gate lead connector), and wherein the gate lead connector is formed outside
`
`the first display region (Fig. 1, GL is formed outside the pixel areas Clc), and connects
`
`between the two or more adjacent first gate lines and one gate terminal of the one or
`
`morefirst gate drivers to receive the gate signals for the two or more adjacent first gate
`
`lines (Fig. 1, GL gate line, i.e. gate lead connector, connected to gate driver for GL).
`
`Before the effectivefiling date of the claimed invention, it would have been
`
`obvious to one of ordinary skill in the art that the first gate lines of Liu can be providedin
`
`the manner Shin discloses providing a gate lead connector that supplies a same signal
`
`to multiple gate lines. The motivation for doing so would have been to provide a wider
`
`viewing angle and quicker liquid crystal responsetime (Shin Par. 0007).
`
`Liu, Tsubata, and Shin do notdisclose expressly two or more adjacentfirst data
`
`lines from the plurality of first data lines are provided with same signals at a same
`
`instant of time from the one or morefirst data drivers, wherein the two or more adjacent
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 6
`
`first data lines from the plurality of first data lines are electrically connected to each
`
`other by a data lead connector, and wherein the data lead connector is formed outside
`
`the first display region, and connects between the two or more adjacent first data lines
`
`and one data terminal of the one or morefirst data drivers to receive the data signals for
`
`the two or more adjacent first data lines.
`
`Shin discloses the two or more adjacentfirst gate lines from the plurality offirst
`
`data lines are electrically connected to each other by a data lead connector (Fig. 1, GL
`
`gate line, i.e. gate lead connector; as applied to the data lines), and wherein the data
`
`lead connector is formed outside the first display region (Fig. 1, GL is formed outside
`
`the pixel areas Clc; as applied to the data lines), and connects between the two or more
`
`adjacent first data lines and one data terminal of the one or morefirst data drivers to
`
`receive the gate signals for the two or more adjacentfirst data lines (Fig. 1, GL gate
`
`line, i.e. gate lead connector, connected to gate driver for GL; as applied to the data
`
`lines).
`
`Before the effective filing date of the claimed invention, it would have been
`
`obvious to one of ordinary skill in the art that the first data lines of Liu can be provided in
`
`the manner Shin discloses with respect to the gate lines by providing a data lead
`
`connector that supplies a same signal to multiple data lines. The motivation for doing so
`
`would have been to provide a wider viewing angle and quicker liquid crystal response
`
`time (Shin Par. 0007).
`
`Therefore, it would have been obvious to combine Tsubata and Shin with Liu to
`
`obtain the invention of claim 1.
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 7
`
`7.
`
`In regards to claim 10, Liu disclosesa liquid crystal display device (Par. 0009-
`
`0010 display device utilizing LCD) comprising: a first display panel (Fig. 3, 03 OLED
`
`display panel) comprising a plurality of first gate lines and a plurality of first data lines in
`
`a first display region thereof (Fig. 3, 03 OLED display panel; Fig. 5, data line DL and
`
`gate line SL), wherein two adjacentfirst gate lines from the plurality of first gate lines
`
`and two adjacent first data lines from the plurality of first data lines defineafirst pixel in
`
`the first display region (Fig. 3, O3OLED panel; Fig. 5, a pixel is defined as being
`
`between two adjacentdata lines DL and two adjacent gate lines SL); a second liquid
`
`crystal display panel (Fig. 3, 01 LCD panel) comprising a plurality of second gate lines
`
`and a plurality of second data lines in a second display region thereof (Fig. 3, 01 LCD
`
`panel; Fig. 5, data line DL and gate line SL; Par. 0076first pixel units of OLED and
`
`second pixel units of LCD are arranged in 1:1 correspondence), wherein two adjacent
`
`second gate lines from the plurality of second gate lines and two adjacent second data
`
`lines from the plurality of second data lines define a second pixel in the second display
`
`region (Fig. 3, 01LCD panel; Fig. 5, a pixel is defined as being between two adjacent
`
`data lines DL and two adjacent gate lines SL), wherein the first display panel and the
`
`second liquid crystal display panel overlap each other in plan view (Fig. 3, 083 OLED
`
`display panel and 01LCD display panel; Par. 0076first pixel units of OLED and second
`
`pixel units of LCD are arrangedin 1:1 correspondence), wherein thefirst display panel
`
`and the second liquid crystal display panel have equal densities offirst pixels and
`
`second pixels, respectively, therein (Fig. 3, 083 OLED display panel and 01LCD display
`
`panel; Par. 0076first pixel units of OLED and second pixel units of LCD are arrangedin
`
`1:1 correspondence), wherein the display panel comprises a first data driving circuit
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 8
`
`comprising one or morefirst data drivers to provide data signals to the plurality offirst
`
`data lines (Fig. 3, 08 OLED panel; Fig. 5, data line DL; drivers for DL datalines).
`
`Liu does not disclose expressly the first display panel is a liquid crystal display
`
`panel; wherein the first liquid crystal display panel displays at a lower definition as
`
`comparedto the secondliquid crystal display panel, wherein two or more adjacent first
`
`data lines from the plurality of first data lines are provided with data signals of same
`
`gray scale at the same instant of time, wherein the two or more adjacent first data lines
`
`from the plurality of first data lines are electrically connected to each other by a data
`
`lead connector, and wherein the data lead connector is formed outside the first display
`
`region, and connects between the two or more adjacent first data lines and one data
`
`terminal of the one or morefirst data drivers to receive the data signals for the two or
`
`more adjacent first data lines.
`
`Tsubata discloses utilizing two stackedliquid crystal display panels (Fig. 1; Par.
`
`0023) containing liquid crystal (Fig. 1, 226 liquid crystal).
`
`Before the effectivefiling date of the claimed invention, it would have been
`
`obvious to one of ordinary skill in the art that the two display panels of Liu can be LCD
`
`panels in the manner Tsubata discloses. The motivation for doing so would have been
`
`to provide an improved contrast ratio (Par. 0032).
`
`Liu and Tsubata do not disclose expressly wherein the first liquid crystal display
`
`panel displays at a lower definition as compared to the second liquid crystal display
`
`panel, wherein two or more adjacent first data lines from the plurality of first data lines
`
`are provided with data signals of same gray scale at the same instant of time, wherein
`
`the two or more adjacent first data lines from the plurality of first data lines are
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 9
`
`electrically connected to each other by a data lead connector, and wherein the data lead
`
`connector is formed outside the first display region, and connects between the two or
`
`more adjacent first data lines and one data terminal of the one or morefirst data drivers
`
`to receive the data signals for the two or more adjacent first data lines.
`
`Shin discloses two or more adjacentfirst gate lines from the plurality of first gate
`
`lines are provided with same signal at a same instant of time from the one or morefirst
`
`gate drivers (Fig. 1, GL1 and GL2 are provided with the same signal from GL at a same
`
`time), wherein the two or more adjacent first gate lines from the plurality of first gate
`
`lines are electrically connected to each other by a gate lead connector (Fig. 1, GL gate
`
`line, i.e. gate lead connector), and wherein the gate lead connector is formed outside
`
`the first display region (Fig. 1, GL is formed outside the pixel areas Clc), and connects
`
`between the two or more adjacent first gate lines and one gate terminal of the one or
`
`morefirst gate drivers to receive the gate signals for the two or more adjacent first gate
`
`lines (Fig. 1, GL gate line, i.e. gate lead connector, connected to gate driver for GL).
`
`Before the effective filing date of the claimed invention, it would have been
`
`obvious to one of ordinary skill in the art that the first gate lines of Liu can be providedin
`
`the manner Shin discloses providing a gate lead connector that supplies a same signal
`
`to multiple gate lines. The motivation for doing so would have been to provide a wider
`
`viewing angle and quicker liquid crystal responsetime (Par. 0007).
`
`Liu, Tsubata, and Shin do notdisclose expressly two or more adjacentfirst data
`
`lines from the plurality of first data lines are provided with same signals at a same
`
`instant of time from the one or morefirst data drivers, wherein the two or more adjacent
`
`first data lines from the plurality of first data lines are electrically connected to each
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 10
`
`other by a data lead connector, and wherein the data lead connector is formed outside
`
`the first display region, and connects between the two or more adjacent first data lines
`
`and one data terminal of the one or morefirst data drivers to receive the data signals for
`
`the two or more adjacent first data lines.
`
`Shin discloses the two or more adjacentfirst gate lines from the plurality offirst
`
`data lines are electrically connected to each other by a data lead connector (Fig. 1, GL
`
`gate line, i.e. gate lead connector; as applied to the data lines), and wherein the data
`
`lead connector is formed outside the first display region (Fig. 1, GL is formed outside
`
`the pixel areas Clc; as applied to the data lines), and connects between the two or more
`
`adjacent first data lines and one data terminal of the one or morefirst data drivers to
`
`receive the gate signals for the two or more adjacentfirst data lines (Fig. 1, GL gate
`
`line, i.e. gate lead connector, connected to gate driver for GL; as applied to the data
`
`lines).
`
`Before the effectivefiling date of the claimed invention, it would have been
`
`obvious to one of ordinary skill in the art that the first data lines of Liu can be provided in
`
`the manner Shin discloses with respect to the gate lines by providing a data lead
`
`connector that supplies a same signal to multiple data lines. This arrangement would
`
`provide the first liquid crystal display panel displays at a lower definition as compared to
`
`the second liquid crystal display panel. The motivation for doing so would have been to
`
`provide a wider viewing angle and quicker liquid crystal response time (Shin Par. 0007).
`
`Therefore, it would have been obvious to combine Tsubata and Shin with Liu to
`
`obtain the invention of claim 10.
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 11
`
`In regards to claim 3, Liu, Tsubata, and Shin, as combined above, disclose the
`
`two or more adjacent first gate lines from the plurality of first gate lines are electrically
`
`connected to each other by a gate lead connector (Shin Fig. 1, GL gate line, i.e. gate
`
`lead connector), and wherein the gate lead connector is formed outside the first display
`
`region (Shin Fig. 1, GL is formed outside the pixel areas Clc), and connects between
`
`the two or more adjacent first gate lines and one gate terminal of the one or morefirst
`
`gate drivers to receive the gate signals for the two or more adjacent first gate lines
`
`(Tsubata Fig. 7, data line DL and gate line GL; Tsubata drivers for DL data lines and GL
`
`gate lines; Tsubata all the gate lines are connected to gate driver; Shin Fig. 1, GL gate
`
`line, i.e. gate lead connector, connectedto gate driver for GL).
`
`In regards to claim 4, Liu, Tsubata, and Shin, as combined above, disclose the
`
`plurality offirst gate lines includeafirst gate line group of the two or more adjacent first
`
`gate lines and a second gate line group of the two or more adjacentfirst gate lines (Shin
`
`Fig. 1, GL1 and GL2 gate lines, wherein each connected GL providing to two gate lines
`
`is a group)the first gate line group and the second gate line group being arranged
`
`immediately adjacent to each other (Tsubata Fig. 7, data line DL and gate line GL;
`
`Tsubata drivers for DL data lines and GL gate lines; Tsubata all the gate lines are
`
`connected to gate driver; Shin Fig. 1, GL gateline, i.e. gate lead connector, connected
`
`to gate driver for GL), and wherein a first gate terminal of the one or morefirst gate
`
`drivers electrically connects to the first gate line group (Tsubata Fig. 7, data line DL and
`
`gate line GL; Tsubata drivers for DL data lines and GL gate lines; Tsubata all the gate
`
`lines are connected to gate driver; Shin Fig. 1, GL gate line, i.e. gate lead connector,
`
`connected to gate driver for GL), a second gate terminal of the one or morefirst gate
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 12
`
`drivers electrically connects to the second gate line group (Tsubata Fig. 7, data line DL
`
`and gate line GL; Tsubata drivers for DL data lines and GL gate lines; Tsubata all the
`
`gate lines are connectedto gate driver; Shin Fig. 1, GL gate line, i.e. gate lead
`
`connector, connectedto gate driver for GL).
`
`Liu, Tsubata, and Shin, do not disclose expressly a third gate terminal of the one
`
`or morefirst gate drivers located between the first gate terminal and the second gate
`
`terminal is voided.
`
`However, the examiner takes OFFICIAL NOTICE that before the effective filing
`
`date of the claimed invention it would have been obvious to one of ordinary skill in the
`
`art that as a single gate line terminal is being driven to two gate lines that the second
`
`gate line terminal would be unneeded and thus voidedasthe third gate line terminal
`
`would be used to drive gate lines three and four based on the pattern Shin discloses.
`
`The motivation for doing so would have been to properly space out the gate lines with
`
`the appropriate terminals.
`
`Therefore, it would have been obvious Liu, Tsubata, and Shin disclose the
`
`invention of claim 4.
`
`In regards to claims 7 and 16, the plurality of first data lines includeafirst data
`
`line group of the two or more adjacent first data lines and a second dataline group of
`
`the two or more adjacentfirst data lines (Shin Fig. 1, GL1 and GL2 gate lines, wherein
`
`each connected GL providing to two gate lines is a group; as applied above to the data
`
`lines) the first data line group and the second data line group being arranged
`
`immediately adjacent to each other (Tsubata Fig. 7, data line DL and gate line GL;
`
`Tsubata drivers for DL data lines and GL gate lines; Tsubata all the gate lines are
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 13
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`connected to gate driver; Shin Fig. 1, GL gateline, i.e. gate lead connector, connected
`
`to gate driver for GL; as applied above to the data lines), and whereinafirst data
`
`terminal of the one or morefirst data drivers electrically connects to the first data line
`
`group (Tsubata Fig. 7, data line DL and gate line GL; Tsubata drivers for DL data lines
`
`and GL gate lines; Tsubata all the gate lines are connected to gate driver; Shin Fig. 1,
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`GL gateline, i.e. gate lead connector, connected to gate driver for GL; as applied above
`
`to the data lines), a second data terminal of the one or morefirst data drivers electrically
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`connects to the second data line group (Tsubata Fig. 7, data line DL and gateline GL;
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`Tsubata drivers for DL data lines and GL gate lines; Tsubata all the gate lines are
`
`connected to gate driver; Shin Fig. 1, GL gateline, i.e. gate lead connector, connected
`
`to gate driver for GL; as applied above to the datalines).
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`Liu, Tsubata, and Shin, do not disclose expressly a third data terminal of the one
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`or morefirst data drivers located between the first data terminal and the second data
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`terminal is voided.
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`However, the examiner takes OFFICIAL NOTICE that before the effectivefiling
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`date of the claimed invention it would have been obvious to one of ordinary skill in the
`
`art that as a single data line terminal is being driven to two data lines that the second
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`data line terminal would be unneeded and thus voided asthe third data line terminal
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`would be usedto drive data lines three and four based on the pattern Shin discloses.
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`The motivation for doing so would have been to properly space out the data lines with
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`the appropriate terminals.
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`Therefore, it would have been obvious Liu, Tsubata, and Shin disclose the
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`invention of claims 7 and 16
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`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 14
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`In regards to claim 8, Liu, Tsubata, and Shin, as combined above, disclose the a
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`second driving circuit for one or moreof the plurality of second gate lines and the
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`plurality of second data lines (Liu Fig. 3, 01 LCD panel; Liu Fig. 5, data line DL and gate
`
`line SL; Liu drivers for DL data lines and SL gate lines), wherein the second driving
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`circuit comprises one or more second gate drivers to provide signals to the one or more
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`of the plurality of second gate lines and one or more second data drivers to provide
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`signals to the one or moreof the plurality of second data lines, wherein a number offirst
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`gate drivers are less than a number of second gate drivers, and wherein a number of
`
`first data drivers are less than a number of second data drivers (Liu Fig. 3, 01 LCD
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`panel; Liu Fig. 5, data line DL and gate line SL; Liu drivers for DL data lines and SL gate
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`lines; As combined above the number of terminals of the gate and data drivers for
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`OLED of Liu, which has been modified to an LCD, would be less than the number of
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`terminals of the gate and data drivers of the LCD of Liu; the two panels are driven
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`independently).
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`In regards to claim 9, Liu, Tsubata, and Shin, as combined above, disclose the a
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`second driving circuit for one or moreof the plurality of second gate lines and the
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`plurality of second data lines (Liu Fig. 3, 01 LCD panel; Liu Fig. 5, data line DL and gate
`
`line SL; Liu drivers for DL data lines and SL gatelines), wherein the second driving
`
`circuit comprises one or more second gate drivers to provide signals to the one or more
`
`of the plurality of second gate lines and one or more second data drivers to provide
`
`signals to the one or more of the plurality of second data lines, wherein a number of
`
`terminals in the one or morefirst gate drivers are less than a number of terminals in the
`
`one or more second gate drivers, and wherein a number of terminals in the one or more
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 15
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`first data drivers are less than a number of terminals in the one or more second data
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`drivers (Liu Fig. 3, 01 LCD panel; Liu Fig. 5, data line DL and gate line SL; Liu drivers
`
`for DL data lines and SL gate lines; As combined above the number of terminals of the
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`gate and data drivers for OLED of Liu, which has been modified to an LCD, would be
`
`less than the number of terminals of the gate and data drivers of the LCD of Liu; the two
`
`panels are driven independently).
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`8.
`
`In regards to claims 17-20, Liu, US-20170206843, Tsubata, US-20090046212,
`
`and Shin, US-20120154700, as combined above in regardsto claim 10, disclose the
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`physical structure of the claims 17-20.
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`Liu, Tsubata, and Shin, as combined above, do not disclose expressly that the
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`structure is formed using photo-masks.
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`Tsubata discloses using photo-masks for manufacturing a dual layer display
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`(Par. 0146-0149 and 0209).
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`Before the effectivefiling date of the claimed invention, it would have been
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`obvious to one of ordinary skill in the art that the dual layer display of Liu, Tsubata, and
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`Shin can be manufactured utilizing photo-masks. The motivation for doing so would
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`have been thatutilizing photo-masks are a commonly used way to manufacture displays
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`as Tsubata discloses.
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`Therefore, it would have been obvious to combine Tsubata with Liu, Tsubata,
`
`and Shin to obtain the invention of claims 17-20.
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`In regards to claim 22, Liu, Tsubata, and Shin, as combined above, disclose the
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`gate lead connector extendsin the seconddirection (Liu Fig. 3, 03 OLED display panel:
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 16
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`Liu Fig. 5, gate line SL which arranged vertically but extend horizontally; Shin Fig. 1, GL
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`gate line. i.e. gate lead connector).
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`In regards to claim 23, Liu, Tsubata, and Shin, as combined above, disclose the
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`data lead connector extendsin the first direction (Liu Fig. 3, 03 OLED display panel; Liu
`
`Fig. 5, data line DL which arranged horizontally but extend vertically; Shin Fig. 1, GL
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`gate line. i.e. gate lead connector, as applied to the data lines as modified above).
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`Conclusion
`
`Applicant's amendment necessitated the new ground(s)of rejection presented in
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`this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP
`
`§ 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37
`
`CFR 1.136(a).
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`A shortenedstatutory period for reply to this final action is set to expire THREE
`
`
`
`MONTHS from the mailing date of this action. In the eventafirst replyis filed within
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`TWO MONTHS ofthe mailing date ofthis final action and the advisory action is not
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`mailed until after the end of the THREE-MONTH shortenedstatutory period, then the
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`shortened statutory period will expire on the date the advisory action is mailed, and any
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`extension fee pursuant to 37 CFR 1.136(a) will be calculated from the