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`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and TrademarkOffice
`Address; COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`
`16/993,466
`
`08/14/2020
`
`Akihiro ITOU
`
`ISHII-63085
`
`AT11
`
`PEARNE & GORDON LLP
`1801 EAST 9TH STREET
`SUITE 1200
`
`CLEVELAND, OH 44114-3108
`
`AHMED, SHAMIM
`
`1713
`
`09/21/2021
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
`following e-mail address(es):
`
`patdocket@ pearne.com
`
`PTOL-90A (Rev. 04/07)
`
`

`

`
`
`Disposition of Claims*
`1-8 is/are pending in the application.
`)
`Claim(s)
`5a) Of the above claim(s) ___ is/are withdrawn from consideration.
`C} Claim(s)
`is/are allowed.
`Claim(s) 1-8 is/are rejected.
`(1 Claim(s)__is/are objectedto.
`Cj) Claim(s
`are subjectto restriction and/or election requirement
`S)
`* If any claims have been determined allowable, you maybeeligible to benefit from the Patent Prosecution Highway program at a
`participating intellectual property office for the corresponding application. For more information, please see
`http://www.uspto.gov/patents/init_events/pph/index.jsp or send an inquiry to PPHfeedback@uspto.gov.
`
`) ) ) )
`
`Application Papers
`10) The specification is objected to by the Examiner.
`11)0) The drawing(s) filedon__ is/are: a)(J accepted or b)() objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`12)1) Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d)or (f).
`Certified copies:
`c)Z None ofthe:
`b)() Some**
`a)C All
`1.2 Certified copies of the priority documents have been received.
`2.1.) Certified copies of the priority documents have been received in Application No.
`3.1.) Copies of the certified copies of the priority documents have been receivedin this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`* See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`1)
`
`Notice of References Cited (PTO-892)
`
`2) (J Information Disclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`Paper No(s)/Mail Date
`U.S. Patent and Trademark Office
`
`3) (J Interview Summary (PTO-413)
`Paper No(s)/Mail Date
`(Qj Other:
`
`4)
`
`PTOL-326 (Rev. 11-13)
`
`Office Action Summary
`
`Part of Paper No./Mail Date 20210916
`
`Application No.
`Applicant(s)
`16/993,466
`ITOU etal.
`
`Office Action Summary Art Unit|AIA (FITF) StatusExaminer
`SHAMIM AHMED
`1713
`Yes
`
`
`
`-- The MAILING DATEofthis communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLYIS SET TO EXPIRE 3 MONTHS FROM THE MAILING
`DATE OF THIS COMMUNICATION.
`Extensions of time may be available underthe provisions of 37 CFR 1.136(a). In no event, however, may a reply betimely filed after SIX (6) MONTHSfrom the mailing
`date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHSfrom the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133}.
`Any reply received by the Office later than three months after the mailing date of this communication, evenif timely filed, may reduce any earned patent term
`adjustment. See 37 CFR 1.704(b).
`
`Status
`
`1) Responsive to communication(s) filed on 8/13/2021.
`C} A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/werefiled on
`2a)¥) This action is FINAL.
`2b) (J This action is non-final.
`3)02 An election was madeby the applicant in responseto a restriction requirement set forth during the interview
`on
`; the restriction requirement and election have been incorporated into this action.
`4\0) Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Exparte Quayle, 1935 C.D. 11, 453 O.G. 213.
`
`

`

`Application/Control Number: 16/993,466
`Art Unit: 1713
`
`Page 2
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`DETAILED ACTION
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`Notice of Pre-AlA or AIA Status
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`1.
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`The present application, filed on or after March 16, 2013,
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`is being examined
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`under the first inventor to file provisions of the AIA.
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`Response to Arguments
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`2.
`
`Applicant's arguments with respect to claim(s) 1-4, as to the point that the
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`applied prior art fails to teach the element chip is held by a holding sheet including a
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`resin, have been considered but are moot because the new groundofrejection does not
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`rely on any reference applied in the prior rejection of record for any teaching or matter
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`specifically challenged in the argument.
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`Claim Rejections - 35 USC § 103
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`3.
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`The text of those sections of Title 35, U.S. Code not included in this action can
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`be found in a prior Office action.
`
`4.
`
`This application currently namesjoint inventors.
`
`In considering patentability of the
`
`claims the examiner presumesthat the subject matter of the various claims was
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`commonly ownedasof the effective filing date of the claimed invention(s) absent any
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`evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to
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`point out the inventor and effective filing dates of each claim that was not commonly
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`ownedasof the effective filing date of the later invention in order for the examiner to
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`consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2)
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`prior art against the later invention.
`
`

`

`Application/Control Number: 16/993,466
`Art Unit: 1713
`
`Page 3
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`5.
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`Claims 1-4, 6 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable
`
`over Applicant’s admitted prior art (AAPA, herein after) in view of Rattner et al (US
`
`2003/0211752) and Hori et al (US 2010/0093179) and in view of Yu etal (US
`
`9,159,574) and further in view of Lei et al (US 9,112,050) and Ishikawa et al (US
`
`2016/0005634).
`
`AAPA discloses a Bosch process to perform dicing method for producing
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`element chips form a substrate, wherein a plasma dicing step of repeating a cycle
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`including an etching and deposition on a dicing region to form a groove along the
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`region; and such technique provide the groove with sidewalls of scallops, which appears
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`a series of peaks and valleys (see [0005] at instant specification).
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`AAPAfails to disclose the instant process steps of sidewall cleaning, oxidation
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`and etching the sidewall after the oxidation for achieving a smoother sidewall of the
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`grooves.
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`However, Rattner et al disclose a process for smoothing a trench sidewall after a
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`deep trench silicon etch process which reduces scalloping present after a silicon trench
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`etch [0010]; wherein the process comprises:
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`The step of cleaning residue using an oxygen plasma (resemble as the claimed
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`first plasma) [0037]; Following the oxygen plasma clean-up step, a plasma generated
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`from a fluorine-containing gas is introduced into the processing chamber at a very low
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`pressure and at a low substrate bias. This very mild isotropic etch selectively smooths
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`out silicon peaks along the sidewalls of the etched trench [0038]; minimization in
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`scalloping 302 shown in FIG. 3A compared to the heavily scalloped trench sidewall 208
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`

`

`Application/Control Number: 16/993,466
`Art Unit: 1713
`
`Page 4
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`of FIG. 2. Exposure of the silicon sidewall 300 to the SF.sub.6 plasma can result in
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`sidewall porosity 304, as shown in FIG. 3A. This porosity can be removed by oxidizing
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`the sidewall 300, then removing the resulting silicon oxide using an HEF dip or by
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`exposure of the sidewall 300 to vaporous HF. The porosity actually aids in the oxidation
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`of the sidewall, because the oxygen can penetrate deeper into the sidewall in a short
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`period of time due to the presence of pores 304 [0042]; As shownin FIG. 3C, after
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`removal of oxide layer 306, the silicon trench sidewall 310 is actually smoother than the
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`silicon trench sidewall 300 prior to the performanceof the oxidation step (shownin FIG.
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`3A), because removal of the oxide layer smoothes any scalloping which may remain
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`after performance of the mild SF.sub.6 etch [0045].
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`Rattner et al disclose that a patterned photoresist layer is provided over a bare
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`silicon wafer prior to performing the trench formation steps [0014] and [0037].
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`Therefore, it would have been obvious to one of ordinary skill
`
`in the art before the
`
`effective filing date of the claimed invention to employ Rattner et al’s teaching of
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`smoothening process into AAPA’s teaching for achieving grooves or trench having
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`smoother sidewalls as required in the industries as taught by Rattner etal.
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`Unlike the instant invention, modified AAPA fails to disclose the oxidation is
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`performed by plasma (resemble as the claimed second plasma); and the removalof the
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`resulted silicon oxide layer by a plasma (resemble as the claimed third plasma).
`
`However, Hori etal disclose a semiconductor processing including the silicon
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`patterning process, wherein the silicon pattern is oxidized by performing a plasma
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`oxidation process on the silicon surface inside a process chamber of a plasma
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`processing apparatus and thereby forming a silicon oxide film on a surfaceofthe initial
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`

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`Application/Control Number: 16/993,466
`Art Unit: 1713
`
`Page 5
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`pattern; and removing thesilicon oxide film, wherein the pattern forming method is
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`arranged to repeatedly perform formation of the silicon oxide film and removal of the
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`silicon oxide film so as to form an objective pattern [0007].
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`Hori et al also disclose that the silicon oxide film may be performed by a wet
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`etching process using diluted hydrofluoric acid, a vapor etching process within a
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`hydrofluoric acid vapor atmosphere, or an atmospheric pressure plasma etching
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`process [0008].
`
`Therefore, it would have been obvious to one of ordinary skill
`
`in the art before the
`
`effective filing date of the claimed invention to employ Hori et al’s teaching of plasma
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`etching along with plasma oxidation of silicon into modified AAPA’s teaching because
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`both the vapor etching and the plasma etching to remove oxide layer are functionally
`
`equivalent as taught by Horietal.
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`In the above modified teaching, modified AAPA may not explicitly disclose that
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`the photoresist mask layer (resemble as the claimed resin film) exist during the sidewall
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`etching step.
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`However, Yu etal disclose sidewall smoothing process of a trench, wherein
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`during the formation of a protective film on the trench sidewall, such could be an oxide
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`film as the second gasincludes an oxygen and the mask layer is not removedprior to
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`scallop removal step from the sidewall (see Figure 2; col.4, lines 55-col.5, line 20).
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`Therefore, it would have been obvious to one of ordinary skill
`
`in the art before the
`
`effective filing date of the claimed invention to employ Yu et al’s teaching of keeping the
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`mask layer on top of the substrate into modified AAPA’s teaching because such
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`

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`Application/Control Number: 16/993,466
`Art Unit: 1713
`
`Page 6
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`depends on the use of the type of (different) chemistry being used has effect on the
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`etching as taught by Yu etal.
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`Additionally,
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`it would have been obvious to keep the mask layer on top of the
`
`substrate to protect the top surface of the substrate from etching, while the etching the
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`trench sidewall.
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`The above modified teaching still fails to disclose or suggest that the element
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`chip being held by a holding sheet including a resin during the processing steps, like
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`sidewall cleaning, oxidation and the etching step (as the currently amended claim 1);
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`and cooling the holding sheet during the plasma dicing step and the smoothing steps
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`(as the context of claims 6 and 8).
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`However, Lei et al disclose a cooling a substrate holding frame (304) including a
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`backing tape 302,
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`in which a wafer or substrate 306 is attached (col.6, lines 45-58;
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`Figure 3), and aforesaid backing tape 302 resemble as the claimed “holding sheet”.
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`Lei et al also disclose during plasma etching, temperature of the substrate is
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`typically controlled, wherein cooling the tape and frame during etch processing is
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`implemented in order to avoid potential tape damage/degradation (col.8, lines 44-col.9,
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`line 3).
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`Lei et al fail to explicitly disclose that the backing tape is a resin.
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`However, Ishikawa et al disclose a supporting unit of semiconductor chips
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`comprises adhesive sheet; a plurality of semiconductor chips is formed on the adhesive
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`sheet by resin-sealing the plurality of semiconductor chips; and the supporting substrate
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`and the adhesive sheet usedin the fabricating process of the semiconductor packages
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`

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`Application/Control Number: 16/993,466
`Art Unit: 1713
`
`Page 7
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`can be separated easily while preventing the breakage of the semiconductor chips.
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`Accordingly, the semiconductor packages can be fabricated easily [0010]; one surface
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`of the adhesive sheet 2, on which the adhesive layer 5 is formed, acts as a chip holding
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`surface for holding the semiconductor chips 21 [0023].
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`Therefore,
`
`it would have been obvious to one of ordinary skill in the art before
`
`the effective filing date of the claimed invention to employ Lei et al and Ishikawaetal’s
`
`teaching of cooling the backing tape (resemble as the holding sheet) and chip or
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`substrate holding sheet comprises resin, respectively,
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`into the modified AAPA’s
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`teaching for chip handling while avoiding the tape (resemble as the holding sheet)
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`damage and preventing breakage of the chips, as taught by Lei et al and Ishikawa etal,
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`respectively.
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`With regards to claims 2 and 4, Hori et al disclose above that formation of the
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`silicon oxide layer and removing the oxide layer repeated for desired or objective line
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`pattern [0007].
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`6.
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`Claims 5 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over
`
`Applicant’s admitted prior art (AAPA, herein after) in view of Rattner et al (US
`
`2003/0211752) and Hori et al (US 2010/0093179) and in view of Yu etal (US
`
`9,159,574) and further in view of Lei et al (US 9,112,050) and Ishikawa et al (US
`
`2016/0005634) as applied to claims 1 and 3 above, and further in view of Scheffer etal
`
`(US 2008/0163139).
`
`

`

`Application/Control Number: 16/993,466
`Art Unit: 1713
`
`Page 8
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`Modified AAPA discloses above except the sidewall cleaning, oxidation and the
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`sidewall etching steps are performed in a same plasma process apparatus.
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`However, Scheffer et al disclose that during chip fabrication, cleaning, etching
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`and oxidation may be performed using a processing tool comprising an automated
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`cluster semiconductor processing equipment or a semi-automated or even manual
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`stand-alone single cell processing chamber [0022],[0078].
`
`Therefore, it would have been obvious to one of ordinary skill
`
`in the art before the
`
`effective filing date of the claimed invention to employ Scheffer et al’s teaching of
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`utilizing a single processing apparatus into modified AAPA’s teaching for easily
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`performed multiple processing steps as taught by Scheffer etal.
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`Additionally, one of ordinary skill in the art would have been easily motivated to
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`do so for reducing time and cost as well as cross-contamination.
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`Conclusion
`
`7.
`
`The prior art made of record,listed in the PTO-892 and notrelied upon is
`
`considered pertinent to applicant's disclosure. ITOU et al (US 2018/0240678) disclose a
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`process of making an element chip, wherein the chip is holding on a support member3,
`
`which is resin material for ease of handling of the supporting member [0027],[0028].
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`8.
`
`Applicant's amendment necessitated the new ground(s) of rejection presented in
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`this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP
`
`§ 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37
`
`CFR 1.136(a).
`
`

`

`Application/Control Number: 16/993,466
`Art Unit: 1713
`
`Page 9
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`A shortened statutory period for reply to this final action is set to expire THREE
`
`MONTHSfrom the mailing date of this action.
`
`In the event a first reply is filed within
`
`TWO MONTHSof the mailing date of this final action and the advisory action is not
`
`mailed until after the end of the THREE-MONTHshortened statutory period, then the
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`shortened statutory period will expire on the date the advisory action is mailed, and any
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`extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of
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`the advisory action.
`
`In no event, however, will the statutory period for reply expire later
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`than SIX MONTHS from the date of this final action.
`
`9.
`
`Any inquiry concerning this communication or earlier communications from the
`
`examiner should be directed to SHAMIM AHMED whose telephone numberis (571)272-
`
`1457. The examiner can normally be reached on M-TH (8-5:30pm).
`
`Examiner interviews are available via telephone, in-person, and video
`
`conferencing using a USPTO supplied web-based collaboration tool. To schedule an
`
`interview, applicant is encouraged to use the USPTO Automated Interview Request
`
`(AIR) at S80:
`
`If attempts to reach the examiner by telephone are unsuccessful, the examiner's
`
`supervisor, Nadine G Norton can be reached on 571-272-1465. The fax phone number
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`for the organization where this application or proceeding is assigned is 571-273-8300.
`
`

`

`Application/Control Number: 16/993,466
`Art Unit: 1713
`
`Page 10
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`
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`
`SHAMIM AHMED
`Primary Examiner
`Art Unit 1713
`
`/SHAMIM AHMED/
`Primary Examiner, Art Unit 1713
`
`