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`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and TrademarkOffice
`Address; COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`
`17/026,849
`
`09/21/2020
`
`Shinji Ujita
`
`P200896US00
`
`3096
`
`WHDA, LLP
`8500 LEESBURG PIKE
`SUITE 7500
`TYSONS, VA 22182
`
`WARD, ERIC A
`
`2891
`
`PAPER NUMBER
`
`NOTIFICATION DATE
`
`DELIVERY MODE
`
`03/31/2022
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
`following e-mail address(es):
`
`patentmail @ whda.com
`
`PTOL-90A (Rev. 04/07)
`
`

`

`
`
`Disposition of Claims*
`1-7 is/are pending in the application.
`)
`Claim(s)
`5a) Of the above claim(s) ___ is/are withdrawn from consideration.
`C} Claim(s)
`is/are allowed.
`Claim(s) 1-6 is/are rejected.
`Claim(s) 7 is/are objectedto.
`C] Claim(s)
`are subjectto restriction and/or election requirement
`* If any claims have been determined allowable, you maybeeligible to benefit from the Patent Prosecution Highway program at a
`participating intellectual property office for the corresponding application. For more information, please see
`http:/Awww.uspto.gov/patents/init_events/pph/index.jsp or send an inquiry to PPHfeedback@uspto.gov.
`
`) ) ) )
`
`Application Papers
`10)2) The specification is objected to by the Examiner.
`11)M The drawing(s) filed on 09/21/2020 is/are: a)¥) accepted or b)() objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`12)[¥] Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d)or (f).
`Certified copies:
`c)() None ofthe:
`b)( Some**
`a) All
`1.4) Certified copies of the priority documents have been received.
`2.1) Certified copies of the priority documents have beenreceived in Application No.
`3.1.) Copies of the certified copies of the priority documents have been received in this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`* See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`1)
`
`Notice of References Cited (PTO-892)
`
`Information Disclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`2)
`Paper No(s)/Mail Date
`U.S. Patent and Trademark Office
`
`3) (J Interview Summary (PTO-413)
`Paper No(s)/Mail Date
`(Qj Other:
`
`4)
`
`PTOL-326 (Rev. 11-13)
`
`Office Action Summary
`
`Part of Paper No./Mail Date 20220321
`
`Application No.
`Applicant(s)
`17/026,849
`Ujita etal.
`
`Office Action Summary Art Unit|AIA (FITF) StatusExaminer
`ERIC A WARD
`2891
`Yes
`
`
`
`-- The MAILING DATEofthis communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLYIS SET TO EXPIRE 3 MONTHS FROM THE MAILING
`DATE OF THIS COMMUNICATION.
`Extensions of time may be available underthe provisions of 37 CFR 1.136(a). In no event, however, may a reply betimely filed after SIX (6) MONTHSfrom the mailing
`date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHSfrom the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133}.
`Any reply received by the Office later than three months after the mailing date of this communication, evenif timely filed, may reduce any earned patent term
`adjustment. See 37 CFR 1.704(b).
`
`Status
`
`1) Responsive to communication(s)filed on 09/21/2020 (original claims).
`C) A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/werefiled on
`
`2a)L) This action is FINAL. 2b)¥)This action is non-final.
`3)02 An election was madeby the applicant in responseto a restriction requirement set forth during the interview
`on
`; the restriction requirement and election have been incorporated into this action.
`4\0) Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Exparte Quayle, 1935 C.D. 11, 453 O.G. 213.
`
`

`

`Application/Control Number: 17/026,849
`Art Unit: 2891
`
`Page 2
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`DETAILED ACTION
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`Notice of Pre-AlA or AIA Status
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`The present application, filed on or after March 16, 2013, is being examined under the first
`
`inventor to file provisions of the AIA.
`
`Claim Rejections - 35 USC § 103
`
`The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections
`
`set forth in this Office action:
`
`A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is
`not identically disclosed as set forth in section 102, if the differences between the claimed invention
`and the prior art are such that the claimed invention as a whole would have been obvious before the
`effective filing date of the claimed invention to a person having ordinaryskill in the art to which the
`claimed invention pertains. Patentability shall not be negated by the manner in which the invention
`was made.
`
`The factual inquiries for establishing a background for determining obviousness under 35 U.S.C.
`
`103 are summarized as follows:
`
`1. Determining the scope and contents of the prior art.
`
`2. Ascertaining the differences between the prior art and the claims at issue.
`
`3. Resolving the level of ordinaryskill in the pertinentart.
`
`4. Considering objective evidence present in the application indicating obviousness or
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`nonobviousness.
`
`Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application
`
`Publication Number 2016/0079410 A1 to Yasumotcetal., “Yasumoto”, in view of U.S. Patent
`
`Application Publication Number 2018/0026099 Ai to Miyamotoetal., “Miyamoto”.
`
`Regarding claim 1, Yasumotodiscloses a nitride semiconductor device (e.g. FIG. 12), comprising:
`
`a substrate (150, 4] [0105]) having a first main surface (upwards) and a second main surface
`
`(downwards) which face in opposite directions;
`
`

`

`Application/Control Number: 17/026,849
`Art Unit: 2891
`
`Page 3
`
`a first nitride semiconductor layer (n-type GaN layer 131, 4 [0105]) of a first conductivity type
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`(n-type) provided abovethe first main surface;
`
`a second nitride semiconductor layer (p-type GaN layer 132, 4 [0105]) of a second conductivity
`
`type (p-type) provided abovethe first nitride semiconductor layer (131), the second conductivity type
`
`being different from the first conductivity type;
`
`a first opening (in direction of current flow 136) which penetrates through the second nitride
`
`semiconductor layer (132) to the first nitride semiconductor layer (131);
`
`an electron transport layer (re-growth GaN 134, 4 [0105]) and
`
`an electron supply layer (re-growth AlGaN 135, 4 [0105]) provided, in that order from a side on
`
`which the substrate is located, above the second nitride semiconductor layer (132) and on an inner
`
`surface of the first opening;
`
`a gate electrode (140, 4 [0105]) provided abovethe electron supply layer and covering the first
`
`opening;
`
`a second opening (openingfilled with source 110/111, 4 [0105]) at a position distanced from the
`
`gate electrode (140), the second opening penetrating through the electron supply layer (135) and the
`
`electron transport layer (134) to the second nitride semiconductor layer (132);
`
`a source electrode (110, 4] [0105]) provided in the second opening and connected to the second
`
`nitride semiconductor layer;
`
`a drain electrode (120, 4] [0105],[0107]) provided on a second main surface-side of the
`
`substrate.
`
`Yasumotofails to clearly teach a third opening at an outermost edge part ina plan view of the
`
`substrate, the third opening penetrating through the electron supply layer and the electron transport
`
`layer to the second nitride semiconductor layer; and a potential fixing electrode provided in the third
`
`

`

`Application/Control Number: 17/026,849
`Art Unit: 2891
`
`Page 4
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`opening, the potential fixing electrode being connected to the second nitride semiconductor layer and in
`
`contact with neither the electron transport layer nor the electron supply layer.
`
`Miyamototeaches(e.g. FIG. 1,FIG. 17,FIG. 25) a third opening (VIA) at an outermost edge partin
`
`a plan view (e.g. FIG. 11 or FIG. 25), the third opening penetrating through an electron supply layer (5S,
`
`{| [0076]) and an electron transport layer (4S, {| [0075]) and into a second nitride semiconductor layer
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`(2S p-type, {| [0073]), and a potential fixing electrode (voltage clamp 4E, 4] [0082],[0083]) in the third
`
`opening, the potential fixing electrode being connected to the second nitride semiconductor layer (2S)
`
`and in contact with neither the electron transport layer (4S) nor the electron supply layer (5S, due to
`
`isolation ISO, 4] [0078]). More generally, Miyamoto teaches a voltage clamp opposite the gate.
`
`It would have been obvious before the effective filing date of the claimed invention to one
`
`having ordinaryskill in the art to have formed the device of Yasumoto with a voltage clamp and
`
`associated potential fixing electrode as exemplified by Miyamotoin order to desirably control and/or
`
`increase the threshold (on/off voltages) of the transistor (Wiyamoto Abstract, 4] [0007]-
`
`[0009],[0012],[0081],[0085],[0114]-[0122]).
`
`Regarding claim 2, Yasumoto in view of Miyamotoyields the nitride semiconductor device
`
`according to claim 1, and Miyamotofurther teaches wherein in a plan view (FIG. 25, 4 [0141]-[0143]) of
`
`the substrate, the third opening (opening VIA filled with 4E) has an annular shape (rectangular
`
`surrounding ring) extending along an entirety of the outermost edge part.
`
`Regarding claim 3, Yasumoto in view of Miyamotoyields the nitride semiconductor device
`
`according to claim 2, and Miyamotofurther teaches wherein in a plan view of the substrate (FIG. 25, 4]
`
`[0141]-[0143]), the potential fixing electrode (4E) has an annular shape extending along an entirety of
`
`the outermost edge part.
`
`

`

`Application/Control Number: 17/026,849
`Art Unit: 2891
`
`Page 5
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`Claims 1 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent
`
`Application Publication Number 2016/0079410 A1 to Yasumotoetal., “Yasumoto”, in view of U.S.
`
`Patent Application Publication Number 2017/0250274 A1 to Nakayamaetal., “Nakayama”.
`
`Regarding claim 1, Yasumotodiscloses a nitride semiconductor device (e.g. FIG. 12), comprising:
`
`a substrate (150, 4] [0105]) having a first main surface (upwards) and a second main surface
`
`(downwards) which face in opposite directions;
`
`a first nitride semiconductor layer (n-type GaN layer 131, 4 [0105]) of a first conductivity type
`
`(n-type) provided abovethe first main surface;
`
`a second nitride semiconductor layer (p-type GaN layer 132, 4 [0105]) of a second conductivity
`
`type (p-type) provided abovethe first nitride semiconductor layer (131), the second conductivity type
`
`being different from the first conductivity type;
`
`a first opening (in direction of current flow 136) which penetrates through the second nitride
`
`semiconductor layer (132) to the first nitride semiconductor layer (131);
`
`an electron transport layer (re-growth GaN 134, 4 [0105]) and
`
`an electron supply layer (re-growth AlGaN 135, 4 [0105]) provided, in that order from a side on
`
`which the substrate is located, above the second nitride semiconductor layer (132) and on an inner
`
`surface of the first opening;
`
`a gate electrode (140, 4 [0105]) provided abovethe electron supply layer and covering the first
`
`opening;
`
`a second opening (openingfilled with source 110/111, 4 [0105]) at a position distanced from the
`
`gate electrode (140), the second opening penetrating through the electron supply layer (135) and the
`
`electron transport layer (134) to the second nitride semiconductor layer (132);
`
`a source electrode (110, 4] [0105]) provided in the second opening and connected to the second
`
`nitride semiconductor layer;
`
`

`

`Application/Control Number: 17/026,849
`Art Unit: 2891
`
`Page 6
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`a drain electrode (120, 4] [0105],[0107]) provided on a second main surface-side of the
`
`substrate.
`
`Yasumotofails to clearly teach a third opening at an outermost edge part ina plan view of the
`
`substrate, the third opening penetrating through the electron supply layer and the electron transport
`
`layer to the second nitride semiconductor layer; and a potential fixing electrode provided in the third
`
`opening, the potential fixing electrode being connected to the second nitride semiconductor layer and in
`
`contact with neither the electron transport layer nor the electron supply layer.
`
`Nakayamateaches(e.g. FIG. 1) a third opening(filled with ISO and VIA) at an outermost edge
`
`part in a plan view of the substrate (e.g. FIG. 5), the third opening penetrating through an electron
`
`supply layer (barrier BA, {| [0070]) and an electron transport layer (channel CH, §] [0070]) to a second
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`nitride semiconductor (CDn, 4 [0068],[0069]), and a potential fixing electrode (VIA, 4 [0080],[0081])
`
`provided in the third opening, the potential fixing electrode being connected (as pictured) to the second
`
`nitride semiconductor layer (CDn) and in contact with neither the electron transport layer (CH) nor the
`
`electron supply layer (BA).
`
`It would have been obvious before the effective filing date of the claimed invention to one
`
`having ordinary skill in the art to have formed the device of Yasumoto with a potential fixing electrode
`
`as taught by Nakayama in order to form a lower voltage biasing structure which allows for reducing the
`
`ON resistance (Nakayama 4 [0081]).
`
`Regarding claim 5, Yasumotoin view of Nakayama yields the nitride semiconductor device
`
`according to claim 1, and Nakayama further teaches (FIG. 33) wherein the potential fixing electrode
`
`(VIA) is electrically connected (as pictured) to the source electrode (SE) via a conductive wiring layer ({
`
`[0215]).
`
`

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`Application/Control Number: 17/026,849
`Art Unit: 2891
`
`Page 7
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`Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application
`
`Publication Number 2016/0079410 Al to Yasumoteetal., “Yasumoto”, in view of U.S. Patent
`
`Application Publication Number 2018/0026099 A1 to Miyamotoetal., “Miyamoto”, further in view of
`
`U.S. Patent Number 5,977,609 to Soderbarg et al., “Soderbarg”.
`
`Yasumotoin view of Miyamotoyields the nitride semiconductor device according to claim 1, and
`
`Miyamoto further teaches wherein a planar shape of the substrate is a quadrangle (FIG. 25).
`
`Miyamotofails to clearly teach wherein the potential fixing electrode is provided as a plurality of
`
`island shapes, each located on a corresponding one ofsides of the substrate in a plan view of the
`
`substrate. Miyamoto teaches, however, that the potential fixing electrode trench (FIG. 25 VIA/4E) is at
`
`the edge of the chip, the effects of cracks(i.e. stress defects) may be reduced (Miyamoto q [0143]).
`
`Soderbarg teaches improving on a trench formed as a continuous trench (FIG. 1a trench walls 5,
`
`column 2 lines 26-46) by instead forming a trench as a plurality of islands (FIG. 2a islands 4,4’, column 2
`
`line 47 to column 3 line 16), located on all sides of the substrate in plan view.
`
`It would have been obvious before the effective filing date of the claimed invention to one
`
`having ordinary skill in the art to have formed the device of Yasumoto in view of Miyamoto with the
`
`potential fixing electrode trench as island structures rather than a continuous trench as taught by
`
`Soderbarg in order to provide multiple paths for the relief of stresses which reducesthe risk of stress
`
`damage (e.g. cracks) (Soderbarg column 4 lines 44-47, column 1 lines 24-42, 58-60) and/or reduce the
`
`risk of foreign particles (Soderbarg FIG. 2a particles 8’,8’’) causing shorts (Soderbarg column 1 lines 24-
`
`42, 45-57).
`
`Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application
`
`Publication Number 2016/0079410 A1 to Yasumotoetal., “Yasumoto”, in view of U.S. Patent
`
`Application Publication Number 2018/0026099 A1 to Miyamotoetal., “Miyamoto”, as applied to
`
`

`

`Application/Control Number: 17/026,849
`Art Unit: 2891
`
`Page 8
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`claim 1 above, and furtherin view of U.S. Patent Application Publication Number 2012/0153300 A1 to
`
`Lidowetal., “Lidow”.
`
`Although Yasumoto in view of Miyamotoyields the nitride semiconductor device according to
`
`claim 1, Yasumoto and Miyamotofail to clearly teach a fourth opening provided in the outermost edge
`
`part outward of the potential fixing electrode and penetrating through the second nitride
`
`semiconductor layerto the first nitride semiconductor layer.
`
`Lidow teaches(e.g. FIG. 7A) a fourth opening(filled with isolation 70, {| [0067]) provided at the
`
`outermost edge part past a potential fixing electrode (50) and penetrating all of the semiconductor
`
`layers (54,53,71,79,78).
`
`It would have been obvious before the effective filing date of the claimed invention to one
`
`having ordinaryskill in the art to have formed the device of Yasumoto in view of Miyamoto with a fourth
`
`opening forming an edgeisolation structure as taught by Lidow in orderto provide isolation between
`
`neighboring semiconductor devices (Lidow 4] [0067]).
`
`Allowable Subject Matter
`
`Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if
`
`rewritten in independent form including all of the limitations of the base claim and anyintervening
`
`claims.
`
`Conclusion
`
`Any inquiry concerning this communication or earlier communications from the examiner
`
`should be directed to ERIC A WARD whose telephone numberis (571)270-3406. The examiner can
`
`normally be reached M-F 10-6 ET.
`
`

`

`Application/Control Number: 17/026,849
`Art Unit: 2891
`
`Page 9
`
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`If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor,
`
`Matthew Landau can be reached on (571)272-1731. The fax phone number for the organization where
`
`this application or proceeding is assigned is 571-273-8300.
`
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`
`/Eric A. Ward/
`Primary Examiner, Art Unit 2891
`
`