www.uspto.gov
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`
`17/322,960
`
`05/18/2021
`
`YOSHIHIRO SATO
`
`083710-3366
`
`6051
`
`Rimon PC - Pansonic Corporation
`8300 Greensboro Dr.
`Suite 500
`McLean, VA 22102
`
`WIEGAND, TYLERJ
`
`2812
`
`PAPER NUMBER
`
`NOTIFICATION DATE
`
`DELIVERY MODE
`
`01/25/2024
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
`following e-mail address(es):
`USPTOmail@rimonlaw.com
`
`PTOL-90A (Rev. 04/07)
`
`

`

`
`
`Disposition of Claims*
`1-20 is/are pending in the application.
`)
`Claim(s)
`5a) Of the above claim(s) 11-20 is/are withdrawn from consideration.
`[] Claim(s)__ is/are allowed.
`Claim(s) 1-10 is/are rejected.
`[) Claim(s)__ is/are objectedto.
`C] Claim(s
`are subjectto restriction and/or election requirement
`)
`* If any claims have been determined allowable, you maybeeligible to benefit from the Patent Prosecution Highway program at a
`participating intellectual property office for the corresponding application. For more information, please see
`http:/Awww.uspto.gov/patents/init_events/pph/index.jsp or send an inquiry to PPHfeedback@uspto.gov.
`
`) ) ) )
`
`Application Papers
`10) The specification is objected to by the Examiner.
`11) The drawing(s) filed on 18 May 2021 is/are: a)() accepted or b) objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121(d).
`
`Priority under 35 U.S.C. § 119
`12)(¥) Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d)or (f).
`Certified copies:
`c)() None ofthe:
`b)( Some**
`a) All
`1.@) Certified copies of the priority documents have been received.
`2.1.) Certified copies of the priority documents have been received in Application No.
`3.1.) Copies of the certified copies of the priority documents have been receivedin this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`*“ See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`1)
`
`Notice of References Cited (PTO-892)
`
`Information Disclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`2)
`Paper No(s)/Mail Date
`U.S. Patent and Trademark Office
`
`3)
`
`4)
`
`(LJ Interview Summary (PTO-413)
`Paper No(s)/Mail Date
`(Qj Other:
`
`PTOL-326 (Rev. 11-13)
`
`Office Action Summary
`
`Part of Paper No./Mail Date 20240112TJW
`
`Application No.
`Applicant(s)
`17/322,960
`SATOet al.
`
`Office Action Summary Art Unit|AIA (FITF)StatusExaminer
`TYLER J WIEGAND
`2812
`Yes
`
`
`
`-- The MAILING DATEof this communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`A SHORTENED STATUTORYPERIOD FOR REPLYIS SET TO EXPIRE 3 MONTHS FROM THE MAILING
`DATE OF THIS COMMUNICATION.
`Extensionsof time may be available underthe provisions of 37 CFR 1.136(a). In no event, however, may a reply betimely filed after SIX (6) MONTHSfrom the mailing
`date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHSfrom the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, evenif timely filed, may reduce any earned patent term
`adjustment. See 37 CFR 1.704(b).
`
`Status
`
`1) Responsive to communication(s) filed on 26 December 2023.
`C) A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/werefiled on
`
`2a)() This action is FINAL. 2b)¥)This action is non-final.
`3) An election was madeby the applicant in responseto a restriction requirement set forth during the interview
`on
`; the restriction requirement and election have been incorporated into this action.
`4)(2) Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Exparte Quayle, 1935 C.D. 11, 453 O.G. 213.
`
`

`

`Application/Control Number: 17/322,960
`Art Unit: 2812
`
`Page 2
`
`Notice of Pre-AlA or AIA Status
`
`1.
`
`The presentapplication, filed on or after March 16, 2013,
`
`is being examined underthe
`
`first inventor to file provisions of the AIA.
`
`Election/Restrictions
`
`2.
`
`Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as
`
`being drawn to a nonelected species, there being no allowable generic or linking claim. Election
`
`was made withouttraversein the reply filed on 12/26/2023.
`
`Priority
`
`3.
`
`Acknowledgmentis made of applicant's claim for foreign priority based on an
`
`application filed in Japan on 02/22/2019.
`
`Information Disclosure Statement
`
`4.
`
`The information disclosure statement (IDS) submitted on 05/18/2021 has been
`
`considered by the examiner.
`
`Specification
`
`5.
`
`The title of the invention is not descriptive. A new title is required thatis clearly
`
`indicative of the invention to which the claims are directed.
`
`

`

`Application/Control Number: 17/322,960
`Art Unit: 2812
`
`Page 3
`
`6.
`
`The disclosure is objected to because of the following informalities where prop osed
`
`corrections are bolded and underlined:
`
`e
`
`[0103],
`
`line 6, “p-type impurity region 28[[p]]a can have”;
`
`Appropriate correction is required.
`
`7.
`
`The lengthy specification has not been checked to the extent necessary to determine
`
`the presence ofall possible minor errors. Applicant’s cooperation is requested in correcting any
`
`errors of which applicant may become awarein the specification.
`
`Drawings
`
`8.
`
`The drawings are objected to because Figures 4A, 6A and 6Ball include an element
`
`#67bn with no corresponding description in the specification. It is believed by the examiner that
`
`these elements should all be #68bn based on [0087] and [0091] -[0093].
`
`9.
`
`The drawingsare further objected to because in Figure 10B, element#28b is shaded as
`
`p-type based on the provided legend butis descried in [0105] as being n-type.
`
`10.
`
`The drawingsare further objected to under 37 CFR 1.83(a). The drawings must show
`
`every feature of the invention specifiedin the claims. Therefore, the limitation in claim 7 that
`
`“the first impurity region is not electrically connected to the second impurity region” must be
`
`shown or the feature(s) canceled from the claim(s). No new matter should be entered.
`
`

`

`Application/Control Number: 17/322,960
`Art Unit: 2812
`
`Page 4
`
`11.
`
`Currently, [0021] and [0033] both state that “the first impurity region need not be
`
`electrically connected to the second impurity region” but no further explanation is provided. In
`
`all presented drawings as far as the examinercan tell, there is an electrical connection between
`
`#67n (interpreted to be the “first impurity region” based on [0069] and [0105]) and #68bn,
`
`#68cn, and #68dn (interpreted to be the “second impurity region” based on [0077] and [0105]).
`
`e
`
`Inthe first embodiment(Figure 3B), first embodiment second modification (Figure 8B), and
`
`first embodiment second modification (Figures 10A and 10B) thereis at least an electrical
`
`connection made through p-type semiconductor regions #66p and #65p.
`
`e
`
`Inthe circuit diagrams of Figures 2, 11, and 13, #67n is part of charge accumulation node
`
`FD (see [0072]) and #68bn, #68cn, and #68dn are part of transistors #22 and #24 (see
`
`[0078]). FD and transistors #22 and #24 are electrically connectedto each other in Figures 2,
`
`11, and 13.
`
`12.
`
`Corrected drawing sheetsin compliance with 37 CFR 1.121(d) are required in reply to
`
`the Office action to avoid abandonmentofthe application. Any amended replacement drawing
`
`sheet should include all of the figures appearing on the immediate prior version of the sheet,
`
`even if only one figure is being amended. The figure or figure number of an amended drawing
`
`should not be labeled as “amended.”If a drawing figure is to be canceled, the appropriate
`
`figure must be removed from the replacement sheet, and where necessary, the remaining
`
`figures must be renumbered and appropriate changes made to the brief description of the
`
`several views of the drawings for consistency. Additional replacement sheets may be necessary
`
`to show the renumbering of the remaining figures. Each drawing sheet submitted after the
`
`

`

`Application/Control Number: 17/322,960
`Art Unit: 2812
`
`Page5S
`
`filing date of an application must be labeled in the top margin as either “Replacement Sheet” or
`
`“New Sheet” pursuant to 37 CFR 1.121(d).
`
`If the changes are not accepted by the examiner, the
`
`applicant will be notified and informed of any required corrective action in the next Office
`
`action. The objection to the drawingswill not be held in abeyance.
`
`Claim Rejections - 35 USC § 112
`
`13.
`
`The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
`
`(a) INGENERAL. —The specification shall contain a written description of the
`invention, and of the manner and process of making and usingit, in such full, clear,
`concise, and exact terms as to enable any person skilled in the art to which it pertains,
`or with which it is most nearly connected, to make and use the same, and shall set forth
`the best mode contemplated by the inventororjoint inventor of carrying out the
`invention.
`
`14.
`
`Claim 7 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AlA), first paragraph,
`
`because the specification, while being enabling for the first impurity region is electrically
`
`connected to the second impurity region, does not reasonably provide enablementfor the first
`
`impurity region is not electrically connected to the second impurity region. The specification
`
`does not enable any person skilled in the art to which it pertains, or with which it is most nearly
`
`connected, to make and use the invention commensurate in scope with these claims.
`
`15.
`
`There are many factors to be considered when determining whether thereis sufficient
`
`evidence to support a determination that a disclosure does not satisfy the enablement
`
`requirement and whether any necessary experimentation is "undue." These factors include, but
`
`are not limited to:
`
`

`

`Application/Control Number: 17/322,960
`Art Unit: 2812
`
`Page 6
`
`(A) The breadth of the claims: Claim 7 recites “the first impurity region is not electrically
`
`connected to the second impurity region”. This claim is narrow in defining that there is no
`
`ability for any electron transfer from the first impurity region to the second impurity region
`
`based on the limitation that they are “not electrically connected”.
`
`(B) The nature of the invention: The invention is a semiconductor imaging device in
`
`which a plurality of semiconductor structures (both doped and undoped) are formed with
`
`overlapping structures. Both doped and undoped semiconductor structures may conduct
`
`electrons such that an electrical connection is inherent between neighboring features within
`
`the structure so long as there is aclear traceable pathway, unimpeded byan insulator or
`
`dielectric material, through doped or undoped semiconductor material.
`
`(C) The state of the prior art and (D) the level of predictability in the art: The
`
`incorporation of PN-junctions in doped semiconductors wherein surrounding regions are doped
`
`with an opposingspecies (i.e. P vs. N type doping) in an attemptto electrically isolate structures
`
`is well known for its ability to mitigate leakage current. However,this structure does not
`
`completely inhibit the transport of charges as evidenced by known leakage current whichis
`
`inherent in a PN-junction diode.
`
`(E) The level of one of ordinary skill: One of ordinary skill in the art would clearly
`
`understand how to interpret this claim as there being no ability for any electrons to be
`
`transported from the first impurity region to the second impurity region based on the limitation
`
`that they are “not electrically connected”.
`
`(F) The amountof direction provided by the inventor and (G) The existence of
`
`working examples: In all presented drawings as far as the examinercan tell, there is an
`
`

`

`Application/Control Number: 17/322,960
`Art Unit: 2812
`
`Page 7
`
`electrical connection between #67n(interpreted to be the “first impurity region” based on
`
`[0069] and [0105]) and #68bn, #68cn, and #68dn (interpreted to be the “second impurity
`
`region” based on [0077] and [0105]).
`
`e
`
`Inthe first embodiment(Figure 3B), first embodiment second modification (Figure 8B), and
`
`first embodiment second modification (Figures 10A and 10B) thereis at least an electrical
`
`connection made through p-type semiconductor regions #66p and #65p.
`
`e
`
`Inthe circuit diagrams of Figures 2, 11, and 13, #67n is part of charge accumulation node
`
`FD (see [0072]) and #68bn, #68cn, and #68dn are part of transistors #22 and #24 (see
`
`[0078]). FD and transistors #22 and #24 are electrically connected to each other in Figures 2,
`
`11, and 13.
`
`(H) The quantity of experimentation neededto makeor use the invention based on
`
`the content of the disclosure: Currently, [0021] and [0033] both state that “the first impurity
`
`region need not be electrically connected to the second impurity region” but no further
`
`explanation is provided such thatsignificant experimentation would be necessary to modify
`
`provided examples in order to maintain functionality while obtaining the claimed limitation.
`
`16.
`
`Since the applicant has not provided anyinstruction for how “the first impurity region is
`
`not electrically connected to the second impurity region” (see (H)) and all of the provided
`
`working examples show an observable pathwayfor an electrical connection between the first
`
`and second impurity regions (see (F) and (G)) through at least doped semiconductor regions
`
`which are known to conductelectricity even when dopant types are in opposition (see (B), (C),
`
`

`

`Application/Control Number: 17/322,960
`Art Unit: 2812
`
`Page 8
`
`and (D), applicant has not reasonably provided enablementfor the first impurity region is not
`
`electrically connected to the second impurity region, Claim 7 is rejected under 35 U.S.C. 112(a).
`
`Claim Rejections - 35 USC § 102
`
`17.
`
`The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form
`
`the basis for the rejections under this section made in this Office action:
`
`A person shall be entitled to a patent unless —
`(a)(1) the claimed invention was patented, described in a printed publication, or
`in public use, on sale, or otherwise available to the public before the effective
`filing date of the claimed invention.
`
`(a)(2) the claimed invention was describedin a patent issued under section 151,
`or in an application for patent published or deemed published under section
`122(b), in which the patent or application, as the case may be, names another
`inventor and was effectively filed before the effective filing date of the claimed
`invention.
`
`18.
`
`Claim(s) 1-6 and 8-10 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated
`
`by US 2016/0211292 A1; Shimizu etal.; 07/2016;
`
`(“292”).
`
`19.
`
`Regarding Claim 1,
`
`292 discloses an imaging device (#10, Figure 1; [0023]-[0024],
`
`image pickup apparatus
`
`comprising a plurality of pixels #101 where Figure 2 is a single pixel #101 circuit [0028], Figure 4
`
`showsa schematic view of four pixels #101 [0044], Figure 5 is a cross-sectional view of Figure 4
`
`[0046], and Figures 6-10 are the method of making the device [0052] -[0086]) comprising:
`
`a semiconductor substrate (#299, Figure 6A; [0054], semiconductor substrate whichis
`
`not numbered in Figure 5A but is described in [0057] to be the combination of #301 and #307);
`
`

`

`Application/Control Number: 17/322,960
`Art Unit: 2812
`
`Page 9
`
`a photoelectric converter that converts incident light into a charge (#102, Figure 2,
`
`[0031], photoelectric conversion unit);
`
`a first impurity region (#310c, Figure 4; [0050], N-type semiconductor region) located in
`
`the semiconductor substrate (Figure 5A, #310c is in #307), the first impurity region
`
`accumulating the charge ([0050], #310c constitutes the FD (“floating diffusion”) which is where
`
`electrons from #102 are transferredto according to [0032]), the first impurity region containing
`
`impurities of a first conductivity type ([0050], #310c is N-type);
`
`a secondimpurity region (#310a and #310b, Figure 4; [0048], N-type semiconductor
`
`regions) located in the semiconductor substrate (Figure 5A, #310a and #310b are in #307), the
`
`second impurity region containing impurities of the first conductivity type ([0048], #310a and
`
`#310b are N-type), the second impurity region being different from the first impurity region
`
`(Figure 4, #310a and #310b are different from #310c);
`
`a third impurity region (#305 and #316, Figure 5A; [0047]-[0048], P-type semiconductor
`
`regions) located in the semiconductor substrate (Figure 5A, #305 and #316are in #307),
`
`between the first impurity region and the second impurity region in plan view ([0047], #305 and
`
`#316 are under all of #306 based on Figures 5a and 5B and [0047], #306 is shown in Figure 4 to
`
`extend between #310c and #310a/b in plan view in the boxed region #100A of the annotated
`
`Figure 4 below such that #305 and #316 are between #310c and #310a/b), the third impurity
`
`region containing impurities of asecond conductivity type ([0047], #305 is P-type) that differs
`
`from the first conductivity type; and
`
`a first contact (#322, #318, and #315, Figure 5A; [0047]-[0048], the combination of
`
`contact plug #322 and P-type semiconductor regions #315 and #318 constitute a contact)
`
`

`

`Application/Control Number: 17/322,960
`Art Unit: 2812
`
`Page 10
`
`located on the semiconductor substrate (Figure 5A, #322, #318, and #315 are on #307) the first
`
`contact being electrically connected to the third impurity region (Figure 5A, #322, #318, and
`
`#315 are electrically connected to #305 and #316 through direct physical contact between #316
`
`and #315), the first contact including a semiconductor containing impurities of the second
`
`conductivity type ([0048], #315 and #318 are P-type semiconductor regions).
`
`FHS..4
`
`Annotated by
`Examiner
`
`
`
`20.
`
`Regarding Claim 2,
`
`292 discloses the imaging device according to claim 1, wherein an impurity
`
`concentration of the second conductivity type (P-type) in the first contact (#322, #318, and
`
`#315) is higher than an impurity concentration of the second conductivity type (P-type) ina
`
`portion of the third impurity region (#305 and #316) located below a surface of the
`
`semiconductor substrate (#315 has a higher impurity concentration than #316 according to
`
`[0048)]).
`
`21,
`
`Regarding Claim 3 (103),
`
`292 discloses the imaging device according to claim 1, further comprising:
`
`

`

`Application/Control Number: 17/322,960
`Art Unit: 2812
`
`Page 11
`
`a voltage supply circuit that supplies a voltage to the first contact ([0048], a
`
`predetermined voltage is supplied to #322 which necessarily requires a voltage supply
`
`circuit to supply the voltage); and
`
`a well region (#307, Figure 5A; [0047], p-type well) located in the semiconductor
`
`substrate ([0057], #307 is in the substrate), the well region containing impurities of the second
`
`conductivity type ([0057], #307 is p-type),
`
`wherein the first impurity region (#310c), the second impurity region (#310a and
`
`#310b), and the third impurity region (#305 and #316) are located in the well region (Figure 5A,
`
`#310c, #310a, #310b, #305, and #316 areall in #307).
`
`22.
`
`Regarding Claim 4,
`
`The imaging device according to claim 1, furthercomprising:
`
`a first pixel (top right pixel of Figure 4 whichis a 2x2 pixel layout according to
`
`[0044]),
`
`wherein the first pixel includes the first impurity region, the second impurity
`
`region, the third impurity region, and the first contact (the top right pixel of Figure 4
`
`shown inaside view in Figure 5A includes #310c, #310a, #310b, #305 and #306 in
`
`annotated region #100A, and #322 and #315).
`
`23.
`
`Regarding Claim 5,
`
`292 discloses the imaging device according to claim 1, further comprising:
`
`

`

`Application/Control Number: 17/322,960
`Art Unit: 2812
`
`Page 12
`
`a first pixel (top right pixel of Figure 4 whichis a 2x2 pixel layout according to
`
`[0044]); and
`
`a second pixel that differs from the first pixel (bottom right pixel of Figure 4
`
`which is a 2x2 pixel layout according to [0044]), wherein
`
`the first pixel includes the first impurity region (Figure 4, the top right pixel
`
`includes #310c), and
`
`the second pixel includes the second impurity region (Figure 4, the bottom right
`
`pixel includes #310a and #310b).
`
`24.
`
`Regarding Claim 6,
`
`292 discloses the imaging device according to claim 1, further comprising:
`
`a first pixel (top right pixel of Figure 4 whichis a 2x2 pixel layout according to
`
`[0044]); and
`
`a second pixel that differs from the first pixel (bottom right pixel of Figure 4
`
`which is a 2x2 pixel layout according to [0044]), wherein
`
`the first pixel includes (see second annotated Figure 4 below) the first impurity
`
`region (Figure 4 annotated, 15‘), the second impurity region (Figure 4 annotated, 2"9),
`
`the third impurity region (Figure 4 annotated, 3"), and the first contact (Figure 4
`
`annotated, Contact 1),
`
`the second pixel includes a fourth impurity region (Figure 4 annotated, 4"), a
`
`fifth impurity region (Figure 4 annotated, 5%"), and a second contact (Figure 4 annotated,
`
`Contact 2),
`
`

`

`Application/Control Number: 17/322,960
`Art Unit: 2812
`
`Page 13
`
`the fourth impurity region is located in the semiconductor substrate and
`
`contains impurities of the first conductivity type (4° in Figure 4 annotated is a repeated
`
`configuration of #310a and#310b whichis in the substrate and is N-type as explained in
`
`Claim 1),
`
`the fifth impurity region is located in the semiconductor substrate (5in Figure 4
`
`annotated is a repeated configuration of 34 whichis in the substrate as explained in
`
`Claim 1), between the first impurity region and the fourth impurity region in plan view
`
`(Figure 4 annotated, 5" is between 4" and 1° in plan view), and the fifth impurity region
`
`contains impurities of the second conductivity type (5in Figure 4 annotated is a
`
`repeated configuration of 34 which is P-type as explained in Claim 1 region #100A), and
`
`the second contact is located on the semiconductor substrate and is electrically
`
`connected to the fifth impurity region, and the second contact includes a semiconductor
`
`containing impurities of the second conductivity type (Contact 2 in Figure 4 annotated is
`
`a repeated configuration of Contact 1 which was explained in Claim 1 to be in the
`
`substrate, Contact 1 was electrically connected to 34 such that contact 2 is electrically
`
`connected to 5, and both contacts contain P-type impurities as explained in claim 1).
`
`25.
`
`Regarding Claim 8,
`
`292 discloses the imaging device according to claim 1, further comprising:
`
`a transistor (#105, Figure 3B; [0034], amplifying transistor) having the second
`
`impurity region as one of a source and a drain ofthe transistor ([0042], active region
`
`#202 in Figure 3B is the full second impurity region which becomes #310a and #310b
`
`

`

`Application/Control Number: 17/322,960
`Art Unit: 2812
`
`Page 14
`
`amongother impurity regions in Figure 4 and each of the source regions and the drain
`
`regions of the amplifying transistor 105 are disposed in the active region 202),
`
`wherein the transistor detects a signal in accordance with a potential of the first
`
`impurity region ([0033], the amplifying transistor #105 is connected to the FD #104 ata
`
`gate and #310 is the FD per Claim 1.).
`
`26.
`
`Regarding Claim 9,
`
`292 discloses the imaging device according to claim 8, wherein the transistor includes a
`
`gate electrode electrically connected to the first impurity region ((0033], Figure 3B, the
`
`amplifying transistor #105 is connected to the FD #104 at a gate and #310is the FD per Claim
`
`1.).
`
`27.
`
`Regarding Claim 10,
`
`292 discloses the imaging device according to claim 1, wherein the third impurity region
`
`(#305 and #316) is in contact with a surface of the semiconductor substrate (Figure 5A and 5B,
`
`#305 and #316 are in contact with a surface of the substrate, #307).
`
`Conclusion
`
`Any inquiry concerning this communication or earlier communications from the
`
`examiner should be directed to TYLER JAMES WIEGAND whosetelephone numberis (571)270-
`
`0096. The examinercan normally be reached Mon-Fri. 8AM-SPM.
`
`

`

`Application/Control Number: 17/322,960
`Art Unit: 2812
`
`Page 15
`
`Examiner interviewsare available via telephone, in-person, and video conferencing
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`/TYLER J WIEGAND/
`Examiner, Art Unit 2812
`/STEVEN M CHRISTOPHER/
`Examiner, Art Unit 2812
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`