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`(19) United States
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`(12) Patent Application Publication (10) Pub. No.: US 2006/0232533 A1
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` Mi azawa (43) Pub. Date: Oct. 19 2006
`9
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`US 20060232533A1
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`(54) DISPLAY DEVICE EMPLOYING
`TIME-DIVISION-MULTIPLEXED DRIVING
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`0F DRIVER CIRCUITS
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`(30)
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`Foreign Application Priority Data
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`Dec. 11, 2001
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`(JP) ...................................... 2001-376587
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`(75)
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`Inventor: Toshio Miyazawa, Chiba (JP)
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`Correspondence Address:
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`REED SMITH LLP
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`3110 FAIRVIEW PARK DRIVE, SUITE 1400
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`FALLS CHURCH, VA 22042 (US)
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`(73) Assignee: Renesas Technology Corp.
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`A 1. N .:
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`Filed:
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`Publication Classification
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`(51)
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`Int. Cl.
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`(2006.01)
`G09G 3/36
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`(52) US. Cl.
`................................................................ 345/88
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`ABSTRACT
`(57)
`lural
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`device includes a dis la
`A dis la
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`pixels each provided with a thin film transistor and arranged
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`in a matrix configuration in its display area, and a drain
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`driver for supplying video signals to the plural pixels. The
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`drain driver supplies video signals to the plural pixels in a
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`time-division-multiplex fashion based upon the kind of the
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`video signals to be displayed, or based upon the location of
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`plural display blocks forming the display area.
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`21
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`11/453 040
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`Jun. 15, 2006
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`Related US. Application Data
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`(62) Division of application No. 10/308,002, filed on Dec.
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`3, 2002, now Pat. No. 7,088,350.
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`PNL
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`Page 1 of 36
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`Tianma Exhibit 1008
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`Tianma Exhibit 1008
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`Patent Application Publication Oct. 19, 2006 Sheet 1 0f 17
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`US 2006/0232533 A1
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`FIG.
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`PNL
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`Patent Application Publication Oct. 19, 2006 Sheet 2 0f 17
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`US 2006/0232533 A1
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`FIG. 2
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`Page 3 of 36
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`Patent Application Publication Oct. 19, 2006 Sheet 3 of 17
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`Patent Application Publication Oct. 19, 2006 Sheet 4 0f 17
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`FIG. 4
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`US 2006/0232533 A1
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`PNL
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`Patent Application Publication Oct. 19, 2006 Sheet 5 0f 17
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`US 2006/0232533 A1
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`FIG. 5
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`Patent Application Publication Oct. 19, 2006 Sheet 6 0f 17
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`FIG. 6
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`Patent Application Publication Oct. 19, 2006 Sheet 7 0f 17
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`FIG. 7
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`Patent Application Publication Oct. 19, 2006 Sheet 8 0f 17
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`FIG. 8
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`Patent Application Publication Oct. 19, 2006 Sheet 9 0f 17
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`Patent Application Publication Oct. 19, 2006 Sheet 10 0f 17
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`Patent Application Publication Oct. 19, 2006 Sheet 11 0f 17
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`Patent Application Publication Oct. 19, 2006 Sheet 12 0f 17
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`FIG. 12
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`Patent Application Publication Oct. 19, 2006 Sheet 13 0f 17
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`Patent Application Publication Oct. 19, 2006 Sheet 14 0f 17
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`Patent Application Publication Oct. 19, 2006 Sheet 15 of 17
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`Patent Application Publication Oct. 19, 2006 Sheet 16 0f 17
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`Patent Application Publication Oct. 19, 2006 Sheet 17 of 17
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`US 2006/0232533 A1
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`Oct. 19, 2006
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`DISPLAY DEVICE EMPLOYING
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`TIME-DIVISION-MULTIPLEXED DRIVING 0F
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`DRIVER CIRCUITS
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`CROSS-REFERENCE TO RELATED
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`APPLICATION
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`[0001] This application is a Divisional application of US.
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`application Ser. No. 10/308,002 filed Dec. 3, 2002. The
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`present application claims priority from U.S. application
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`Ser. No. 10/308,002 filed Dec. 3, 2002, which claims
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`priority from Japanese application 2001-376587 filed on
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`Dec. 11, 2001, the content of which is hereby incorporated
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`by reference into this application.
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`BACKGROUND OF THE INVENTION
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`[0002] The present invention relates to a display device
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`using thin film transistors. Among display devices having
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`pixels provided with a thin film transistor and arranged in a
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`matrix configuration, there are liquid crystal display devices
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`using liquid crystal, and display devices of the EL type using
`electroluminescence.
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`[0003] FIG. 16 shows a first conventional liquid crystal
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`display device using thin film transistors. In this liquid
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`crystal display device, thin film transistors are arranged in an
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`array on one of two opposing transparent glass substrates
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`(not shown), and a transparent counter electrode is disposed
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`on the other of the two opposing transparent glass substrate.
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`The liquid crystal display device needs polarizers and a
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`backlight as its constituent parts in addition to a display
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`panel formed of the two opposing transparent substrates, but
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`those constituent parts are not directly related to the present
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`invention, and therefore in the subsequent explanation, the
`one of the two substrates formed with the thin film transis-
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`tors is referred to as the display panel.
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`[0004]
`In FIG. 16, fabricated on the display panel LCP are
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`a plurality of scanning lines GL extending horizontally and
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`a plurality of drain lines DL extending vertically. Thin film
`transistors TFT are fabricated in the vicinities of intersec-
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`tions of the scanning lines GL and the drain lines DL. A gate
`of each of the thin film transistors is connected to a corre-
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`sponding one of the scanning lines GL, and one of a drain
`and a source of each of the thin film transistors is connected
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`to a corresponding one of the drain lines DL, and the other
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`of the drain and the source is connected to a pixel electrode.
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`A plurality of pixels each having the thin film transistor TFT
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`and the pixel electrode are arranged in a matrix configura-
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`tion on the crystal display panel LCP. Shown in FIG. 16 are
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`pixels PXR for displaying red images, pixels PXG for
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`displaying green images, and pixels PXB for displaying blue
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`images coupled to respective scanning lines GL, among the
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`pixels arranged in the matrix configuration. A trio of the
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`pixel PXR, the pixel PXG and the pixel PXB forms a picture
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`dot. In an actual display area DPA, the trios are formed in a
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`repeating configuration.
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`[0005]
`In operation of displaying, video signals supplied
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`to the drain lines DL are applied to the pixel electrodes by
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`selecting one of the scanning lines GL, and thereby turning
`on the thin film transistors TFT connected to the selected
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`scanning line GL. As a result, a liquid crystal composition
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`sandwiched between the pixel electrodes and the counter
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`electrode is driven, and thereby light transmission between
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`Page 19 of 36
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`the pixel electrodes and the counter electrode is controlled,
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`and consequently, a display is produced.
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`[0006] The scanning lines GL extends outside of the
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`display area DPA formed with the pixels arranged in a
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`matrix configuration, and are coupled to gate drivers VSR
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`outside of the left and right sides of the display area DPA.
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`The drain lines DL also extend outside of the display area
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`DPA. In this liquid crystal display device, the drain lines DL
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`coupled to pixels for displaying red, green, and blue images
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`are connected to one terminal of switches SWR, SWG, and
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`SWB, respectively. The other terminals of the three switches
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`SWR, SWG, and SWB connected to the drain lines DL for
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`a red (R) signal, a green (G) signal and a blue (B) signal,
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`respectively, are connected together and connected to one of
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`video signal input terminals VIDEOIN formed on the dis-
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`play panel LCP.
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`[0007] The switches SWR associated with the pixels PXR
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`for displaying red images are controlled by a signal (1)1, the
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`switches SWG associated with the pixels PXG for display-
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`ing green images are controlled by a signal (1)2, and the
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`switches SWB associated with the pixels PXB for displaying
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`blue images are controlled by a signal (1)3. All the drain lines
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`DL coupled to the pixels PXR for displaying red in the
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`display area DPA are coupled to corresponding ones of the
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`video signal input terminals VIDEOIN via the respective
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`switches SWR controlled by the signal (1)1, all the drain lines
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`DL coupled to the pixels PXG for displaying green in the
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`display area DPA are coupled to corresponding ones of the
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`video signal input terminals VIDEOIN via the respective
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`switches SWG controlled by the signal (1)2, and all the drain
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`lines DL coupled to the pixels PXB for displaying blue in the
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`display area DPA are coupled to corresponding ones of the
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`video signal input terminals VIDEOIN via the respective
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`switches SWB controlled by the signal (1)3. In other words,
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`each of the video signal
`input
`terminals VIDEOIN is
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`coupled to the three drain lines DL coupled to the three
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`pixels for displaying red (R) signals, green (G) signals and
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`blue (B) signals via the three switches SWR, SWG, SWB
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`controlled by the three signals (1)1,
`(1)2 and (1)3, respectively.
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`[0008] The video signal input terminals VIDEOIN formed
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`on the display panel LCP are connected to terminals of tape
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`carrier packages TCP1, TCP2 and TCP3, and are connected
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`to drain drivers DRV1, DRV2 and DRV3 (numerical suffixes
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`1, 2, 3,
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`confusion can hardly arise) mounted on the tape carrier
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`packages TCP1, TCP2 and TCP3 via wiring thereon. In
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`FIG. 16, the video signal input terminals VIDEOIN and the
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`terminals of the terminals of the tape carrier packages TCP1,
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`TCP2 and TCP3 are separated from each other, but
`in
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`practice they are connected to each other as by anisotropic
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`conductive sheets. The three signals (1)1,
`(1)2 and (1)3 for
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`controlling the switches SWR, SWG and SWB formed on
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`the display panel LCP are supplied from an external control
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`circuit TCON external to the display panel LCP.
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`[0009] FIG. 15 shows an internal structure of the drain
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`driver DRV. The drain driver includes an input latch I-LTC
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`for holding video data in digital form supplied from an
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`external circuit, an output latch P-LTC for receiving the
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`video data from the input latch I-LTC, and digital-to analog
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`converters DAC for converting the video data held in the
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`output latch P-LTC into analog signals for the purpose of
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`supplying video signals to the video signal input terminals
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`VIDEOIN of the display panel LCP.
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`Page 19 of 36
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`US 2006/0232533 A1
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`Oct. 19, 2006
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`[0010]
`In this display device explained above, during a
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`period when a given one of the scanning lines GL is selected,
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`first a first kind of video signals supplied from the drain
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`drivers DRV1, DRV2, DRV3 are written into the red-
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`displaying pixels PXR via the switches SWR by turning the
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`signal (1)1 into an ON state, then during the same period when
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`the given one of the scanning lines GL is selected, a second
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`kind of video signals supplied from the drain drivers DRV1,
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`DRV2, DRV3 are written into the green-displaying pixels
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`PXG via the switches SWG by turning the signal (1)2 into an
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`ON state, and then during the same period when the given
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`one of the scanning lines GL is selected, a third kind of video
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`signals supplied from the drain drivers DRV1, DRV2, DRV3
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`are written into the blue-displaying pixels PXB via the
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`switches SWB by turning the signal (1)3 into an ON state. In
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`other words, during a period when a given one of the
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`scanning lines GL is selected, the drain drivers DRV output
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`video signals for the red-displaying pixels PXR, video
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`signals for the green-displaying pixels PXG, and video
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`signals for the blue-displaying pixels PXB sequentially, in a
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`time-division-multiplexed
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`makes it possible to reduce the number of the drain drivers
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`DRV to one third of the number of drain drivers required in
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`a conventional display device.
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`[0011] FIG. 13 shows a second conventional liquid crystal
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`display device. This liquid crystal display device also
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`includes a plurality of scanning lines GL, a plurality of drain
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`lines DL, and a plurality of pixels each provided with a thin
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`film transistor and a pixel electrode, and the scanning lines
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`GL are connected to two gate drivers VSR. This second
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`conventional liquid crystal display device differs from the
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`above-explained first conventional
`liquid crystal display
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`device in that the display area LCP of the second conven-
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`tional liquid crystal display device is divided into a plurality
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`of display blocks.
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`[0012]
`In the second conventional liquid crystal display
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`device, each of the display blocks has a plurality of drain
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`lines DL, each of which is connected to one terminal of a
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`corresponding one of a plurality of switches outside of the
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`display area DPA. The other terminal of each of the switches
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`is connected to a corresponding one of a plurality of drain
`bus conductors. The switches connected to the drain lines
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`DL in the same display block are controlled by a common
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`signal.
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`In the second conventional liquid crystal display
`[0013]
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`device, the display area DPA is divided into three display
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`blocks BK1, BK2 and BK3, in each of which 11 picture dots
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`are coupled to each of the scanning lines GL.
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`[0014]
`In a first display block BK1 shown in FIG. 13,
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`there are red-displaying pixels PR1, PR2,
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`green-displaying pixels PG1, PG2,
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`displaying pixels PB1, PB2,
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`coupled to the same one of the scanning lines GL. The drain
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`lines DL coupled to the red-displaying pixels, the green-
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`displaying pixels, and the blue-displaying pixels are coupled
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`to bus conductors BR1, BR2, BRn, bus conductors BG1,
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`BG2, .
`, BGn, and bus conductors BB1, BB2, .
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`of a drain bus, via switching elements SR1, SR2, .
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`switching elements SG1, SG2,
`, SGn, and switching
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`elements SB1, SB2, .
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`display area DPA.
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`[0015]
`In a second display block BK2 shown in FIG. 13,
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`there are red-displaying pixels PRn+l, PRn+2, .
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`green-displaying pixels PGn+l, PGn+2,
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`blue-displaying pixels PBn+l, PBn+2,
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`which are coupled to the same one of the scanning lines GL
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`as in the first display block BK1. The drain lines DL coupled
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`to the red-displaying pixels, the green-displaying pixels, and
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`the blue-displaying pixels are coupled to the bus conductors
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`BR1, BR2, .
`, BRn, the bus conductors BG1, BG2, .
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`BGn, and the bus conductors BB1, BB2, .
`, BBn, of the
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`drain bus, via switching elements SRn+l, SRn+2,
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`SR2n, switching elements SGn+l, SGn+2, .
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`, SG2n, and
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`switching elements SBn+l, SBn+2, .
`, SB2n, respectively,
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`outside of the display area DPA.
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`[0016]
`In a third display block BK3 shown in FIG. 13,
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`there are red-displaying pixels PR2n+l, PR2n+2, .
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`, PR3n,
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`green-displaying pixels PG2n+l, PG2n+2, .
`, PG3n, and
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`blue-displaying pixels PB2n+l, PB2n+2, .
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`, PB3n, all of
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`which are coupled to the same one of the scanning lines GL
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`as in the first display block BK1. The drain lines DL coupled
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`to the red-displaying pixels, the green-displaying pixels, and
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`the blue-displaying pixels are coupled to the bus conductors
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`BR1, BR2, .
`, BRn, the bus conductors BG1, BG2, .
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`BGn, and the bus conductors BB1, BB2, .
`, BBn, of the
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`drain bus, via switching elements SR2n+l, SR2n+2,
`.
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`SR3n, switching elements SG2n+l, SG2n+2,
`, SG3n,
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`and switching elements SB2n+l, SB2n+2,
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`, SB3n,
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`respectively, outside of the display area DPA.
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`[0017] As explained above, since there are 11 bus conduc-
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`tors for red signals, 11 bus conductors for green signals, and
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`11 bus conductors for blue signals, a total of 3n bus conduc-
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`tors are formed outside of the display area DPA. The
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`respective bus conductors of the drain bus are connected to
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`corresponding ones of output terminals of the drain drivers.
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`[0018] On-or-olf control of the plural switches SR1, SG1,
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`SB1, SR2, SG2, SB2, .
`, SRn, SGn, SBn coupled between
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`the drain lines in the first display block BK1 and the drain
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`bus is performed by a signal (1)1, on—or-olf control of the
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`plural switches SRn+l, SGn+l, SBn+l, SRn+2, SGn+2,
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`SBn+2, .
`, SR2n, SG2n, SB2n coupled between the drain
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`lines in the second display block BK2 and the drain bus is
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`performed by a signal (1)2, and on-or-olf control of the plural
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`switches SR2n+l, SG2n+l, SB2n+l, SR2n+2, SG2n+2,
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`SB2n+2, .
`, SR3n, SG3n, SB3n coupled between the drain
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`lines in the third display block BK3 and the drain bus is
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`performed by a signal (1)3. The signals (1)1,
`(1)2 and (1)3 are
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`supplied by an external control circuit TCON. The drain
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`lines DL in each of the display blocks, the switches coupled
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`between the drain lines DL and the drain bus, the drain bus
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`conductors, and the output terminals of the drain drivers
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`DRV are equal in number. The display blocks BK1, BK2, .
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`. and the control signals (1)1, (1)2,
`. are equal in number.
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`[0019]
`In this liquid crystal display device explained
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`above, during a period when a given one of the scanning
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`lines GL is selected, initially a first group of video signals
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`supplied from the drain driver DRV to the drain bus are
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`written into pixels of the first display block BK1 via the
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`switches SR1, SG1, SB1, SR2, SG2, SB2, .
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`, SRn, SGn,
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`SBn coupled to the drain lines DL in the first display block
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`BK1 by turning the signal (1)1 into an ON state, then, during
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`the period when the given one of the scanning lines GL is
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`selected, a second group of video signals supplied from the
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`drain driver DRV to the drain bus are written into pixels of
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`the second display block BK2 via the switches SRn+l,
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`Page 20 of 36
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`

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`US 2006/0232533 A1
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`Oct. 19, 2006
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`, SR2n, SG2n,
`SGn+l, SBn+l, SRn+2, SGn+2, SBn+2, .
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`SB2n coupled to the drain lines DL in the second display
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`block BK2 by turning the signal (b2 into an ON state, and
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`then, during the period when the given one of the scanning
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`lines GL is selected, a third group of Video signals supplied
`from the drain driver DRV to the drain bus are written into
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`pixels of the third display block BK3 Via the switches
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`SR2n+l, SG2n+l, SB2n+l, SR2n+2, SG2n+2, SB2n+2, .
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`, SR3n, SG3n, SB3n coupled to the drain lines DL in the
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`third display block BK3 by turning the signal (b3 into an ON
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`state. In this liquid crystal display device, during a period
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`when a given one of the scanning lines GL is selected, the
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`drain driver DRV outputs the a first group of video signals
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`for the first display block BK1, a second group of video
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`signals for the second display group BK2, and a third group
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`of video signals for the third display block BK3 sequentially,
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`in a time-division-multiplexed fashion. This configuration
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`makes it possible to reduce the number of the drain drivers
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`DRV to one third of the number of drain drivers required in
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`a conventional display device.
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`[0020]
`In the above-explained two liquid crystal display
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`devices, the display area is divided into a plurality of groups,
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`and during one horizontal scanning period in which one of
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`the scanning lines GL, the driver writes video signals into
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`pixels of respective ones of the plural groups sequentially in
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`a time-division-multiplexed fashion. Consequently, it makes
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`possible to drive the drain lines DL larger in number than
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`output terminals of the drain driver DRV
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`[0021]
`Specifically, the first conventional display device
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`divides the video signal lines into three groups of a red (R)
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`signal group, a green (G) signal group and a blue (B) signal
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`group, and thereby its drain driver DRV is capable of driving
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`drain lines DL three times as many as the number of its
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`output terminals. The second conventional display device
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`divides the display area DPA into three parts, and thereby its
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`drain driver DRV is capable of driving drain lines DL three
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`times as many as the number of its output terminals.
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`SUMMARY OF THE INVENTION
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`[0022] FIG. 17 is a timing chart illustrating signals such
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`as video signal for the first conventional
`liquid crystal
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`display device. The following explains problems with the
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`first conventional liquid crystal display device by reference
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`to FIGS. 16 and 17. Generally,
`liquid crystal display
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`devices receive 6-bit digital data I-R for displaying 64-gray-
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`scale red, 6-bit digital data I-G for displaying 64-gray-scale
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`green, and 6-bit digital data I-B for displaying 64-gray-scale
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`blue, in parallel, that is, 18 bits in parallel, from external
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`equipment such as a computer.
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`[0023]
`In FIG. 17, the video data I-R corresponding to 3n
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`pixels associated with a given one of the scanning lines GL
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`are supplied to the liquid crystal display device sequentially
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`in the order of R1, R2,
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`, R2n,
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`R2n+l, .
`, R3n, and the video data I-G corresponding to
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`3n pixels associated with the given scanning line GL and I-B
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`corresponding to 3n pixels associated with the given scan-
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`ning line GL are supplied to the liquid crystal display device
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`sequentially in the same manner. Here, the video data I-R,
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`I-G and I-B corresponding to 3n pixels associated with a
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`next one of the scanning lines GL immediately after the
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`above-mentioned given scanning line GL are identified with
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`an added prime notation C), as R'1, .
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`, R'3n, G'1, .
`, G'3n,
`.
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`.
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`B'1, .
`, B'3n, respectively, and the video data I-R, I-G and
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`I-B corresponding to 3n pixels associated with one of the
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`scanning lines GL immediately after the above-mentioned
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`next scanning line GL are identified with an added double-
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`prime notation (") , as R"1, .
`, R"3n, G"1, .
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`, G"3n, B"1,
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`, B"3n, respectively.
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`[0024]
`In the liquid crystal display device employing a
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`drain driver having one input latch I-LTC system and one
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`digital-to-analog converter DAC system only, it is necessary
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`to incorp