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`(19) United States
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`(12) Patent Application Publication (10) Pub. No.: US 2006/0118786 A1
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`(43) Pub. Date: Jun. 8, 2006
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`Kim et al.
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`US 20060118786A1
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`(54) THIN FILM TRANSISTOR, METHOD OF
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`MANUFACTURING THE SAME, DISPLAY
`APPARATUS HAVING THE SAME AND
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`METHOD OF MANUFACTURING THE
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`DISPLAY APPARATUS
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`Publication Classification
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`(51)
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`Int. Cl.
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`(2006.01)
`H01L 29/04
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`(52) use. ................................................................ 257/59
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`(75)
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`(57)
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`ABSTRACT
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`Inventors: Sang-Gab Kim, Seoul (KR); Shi--Yul
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`Kim, Yongin-si (KR); Hong-Sick Park,
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`Suwon—si (KR); Hee-Hwan Choe,
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`lncheon (KR); Hong-Kee Chin,
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`Suwon—si (KR); Min-Seok Oh,
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`Yongin-si (KR)
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`Correspondence Address:
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`DLA PIPER RUDNICK GRAY CARY US, LLP
`2000 UNIVERSITY AVENUE
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`E. PALO ALTO, CA 94303-2248 (US)
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`(73) Assignee: Samsung Electronics Co., Ltd.
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`(21) Appl. No.:
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`(22)
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`Filed:
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`11/232,306
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`Sep. 20, 2005
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`(30)
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`Foreign Application Priority Data
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`Dec. 8, 2004
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`(KR) .............................. 10-2004-103221
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`A thin film transistor includes a gate electrode on a substrate,
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`a gate insulating layer on the substrate, a channel pattern, a
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`source electrode and a drain electrode. The channel pattern
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`includes a semiconductor pattern formed on the gate elec-
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`trode and overlaying the gate electrode as well as first and
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`second conductive adhesive patterns formed on the semi-
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`conductor pattern and spaced apart from each other. The
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`source electrode includes a first barrier pattern, a source
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`pattern and a first capping pattern sequentially formed on the
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`first conductive adhesive pattern. The drain electrode
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`includes a second barrier pattern, a drain pattern and a
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`second capping pattern sequentially formed on the second
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`conductive adhesive pattern. Etched portions of the first and
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`second conductive adhesive patterns have a substantially
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`vertical profile to prevent the exposure of the source and
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`drain electrodes, thereby improving the characteristics of the
`thin film transistor.
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`1 05
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`f%\\\m3...-..rn m”-
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`f/IAIIII'--——
`ll.—
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`||\‘I
`II|III
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`131
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`110
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`127a 122 12713141 143 145
`133 135115
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`H4 H4
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`120
`140
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`100
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`Page 1 of 26
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`Tianma Exhibit 1009
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`Tianma Exhibit 1009
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`Patent Application Publication
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`Jun. 8, 2006 Sheet 1 0f 15
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`US 2006/0118786 A1
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`FIG.
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`1
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`170
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`DL
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`Patent Application Publication
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`Jun. 8, 2006 Sheet 2 0f 15
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`FIG. 2
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`US 2006/0118786 A1
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`II.lllllllllllllllll'lllIIIIIIIIIIIIUI'I’IIIIIIIIIIII'III”IIII.'-II'll'llo‘ll'l"'-IIIII
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`I.I'lIl-IollII'IIIIIIIIIIIIIIIIFIIl..llllllirll.lllIII'IIJIII‘IU"l---"‘|llllll|‘fl|l"
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`--------—
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`I
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`GL
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`Page 3 of 26
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`Patent Application Publication
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`Jun. 8, 2006 Sheet 3 0f 15
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`US 2006/0118786 A1
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`FIG. 3
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`A\\\\
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`““““““-N\\\
`5
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`21qu‘iia“\\\
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`105
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`135 115
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`127a 122 127b141 143 145
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`FIG. 4
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`AflifilililliliIF'A
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`Patent Application Publication
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`Jun. 8, 2006 Sheet 4 0f 15
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`US 2006/0118786 A1
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`FIG. 5
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` Mil/4
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`FIG. 6
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`Patent Application Publication
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`Jun. 8, 2006 Sheet 5 0f 15
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`US 2006/0118786 A1
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`FIG. 7
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`105
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`Patent Application Publication
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`Jun. 8, 2006 Sheet 6 0f 15
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`FIG. 9
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`US 2006/0118786 A1
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`3/5.:myl‘h=-———.
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`II|IIII||\‘i
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`131
`127a 122 127b141 143 145
`133 135115
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`%._J E—J
`H——’
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`120
`140
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`100
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`Patent Application Publication
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`Jun. 8, 2006 Sheet 7 0f 15
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`FIG.
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`US 2006/0118786 A1
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`IIIIIIIIIIIIIIII
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` Alliili'flii'idh
`iiiiIIiMi
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`133 135115
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`127a 122 127D 141 143 145
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`FIG. 12
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`Patent Application Publication
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`Jun. 8, 2006 Sheet 8 of 15
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`US 2006/0118786 A1
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`FIG.
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`13
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`.00".’Ill'llllllllllIlllllllll'll’IUIUIIIIIIIIIII‘IIIIIIIIIIIIIIIIIIOC'IIIIIIIIIII
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`2
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`I‘-
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`165
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`GL
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`IIII‘IIIIIIIIIIIIIIIIll
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`Page 9 of 26
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`45*“
`30122127 110 14FIIIIIIUIIIIIIIIIIIIIIIIIIII
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`0
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`Patent Application Publication
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`9
`Jun. 8
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`2006 Sheet 9 0f 15
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`US 2006/0118786 A1
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`lllla—I—IE—I
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`llllll.§\L‘\\\\\\III
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`Page 10 of 26
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` 91.DE.09‘
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`\‘fJ\Ilj}m3.9:.SlangNNFmum?o:9;.mm_.mm_.5—.
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`Jun. 8, 2006 Sheet 10 0f 15
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`US 2006/0118786 A1
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`FIG. 15
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`Ill/[III]
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`105
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`FIG. 16
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`(ll/It’ll;
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`Jun. 8, 2006 Sheet 11 0f 15
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`US 2006/0118786 A1
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`FIG.
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`. -m-......-.-—u—. - --~__..-..—._‘-- ..
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`”III/[IA -=
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`115
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`121
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`126
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`‘\\\\\\\\\\\\\\\\\
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`-...... ..
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`\.
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`Jun. 8, 2006 Sheet 12 0f 15
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`US 2006/0118786 A1
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`FIG. 20
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`Jun. 8, 2006 Sheet 13 0f 15
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`FIG. 21
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`US 2006/0118786 A1
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`127a 122 127b141 143 145
`135 115
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`W—J W W
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`F l G. 22
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`fi\ii-
`IIIII—
`IIIIIIIIIIIIAlliflli'lilli'i.
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`_aIIIIIINIINIINNIIIlIIIIIIIIIIIIIIIIIIINIIEIIIIJIIIIIIIE>
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`127a 122 127b141 143 145
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`Jun. 8, 2006 Sheet 14 0f 15
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`205
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`FIG.23
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`Jun. 8, 2006 Sheet 15 0f 15
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`m22OSO:
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`on
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`\IKJ1.{J1?)m3m3GER;«3mm:o:m:mm?mm?a:
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`US 2006/0118786 A1
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`Jun. 8, 2006
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`THIN FILM TRANSISTOR, METHOD OF
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`MANUFACTURING THE SAME, DISPLAY
`APPARATUS HAVING THE SAME AND METHOD
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`OF MANUFACTURING THE DISPLAY APPARATUS
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`CROSS-REFERENCE TO RELATED
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`APPLICATIONS
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`[0001] This application relies for priority upon Korean
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`Patent Application No. 2004-103221 filed on Dec. 8, 2004,
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`the content of which is herein incorporated by reference in
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`its entirety.
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`BACKGROUND OF THE INVENTION
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`[0002]
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`1. Field of the Invention
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`[0003] The present invention relates to a thin film transis-
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`tor, a method of manufacturing the same, a display apparatus
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`having the same and a method of manufacturing the display
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`apparatus. More particularly, the present invention relates to
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`a thin film transistor for an array substrate of a display
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`apparatus, a method of manufacturing the thin film transis-
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`tor, a display apparatus having the thin film transistor and a
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`method of manufacturing the display apparatus.
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`2. Description of the Related Art
`[0004]
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`[0005]
`In general, a liquid crystal display apparatus
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`includes an array substrate and a color filter substrate. The
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`array substrate includes a thin film transistor acting as a
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`switching device and a pixel electrode electrically connected
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`to the thin film transistor to receive a pixel voltage. The color
`filter substrate includes a common electrode.
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`[0006] The thin film transistor includes a gate line formed
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`with a gate electrode, a gate insulating layer for the gate line,
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`a channel pattern on the gate insulating layer, a data line
`formed with a source electrode and a drain electrode.
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`[0007] Recently, signal lines such as the gate line, the data
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`line, etc., have become longer due to an increase in the size
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`of the liquid crystal display apparatus. As a result of the
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`signal lines being longer, signals applied to the signal lines
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`are delayed or distorted. In order to prevent the delay and
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`distortion of the signals, the signal
`lines include a low-
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`resistance metal such as aluminum (Al), aluminum alloy and
`the like.
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`[0008] However, an undesirable irregularity forms on the
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`low-resistance metal (e.g., aluminum) when heat is applied.
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`More specifically, when the aluminum is heated to a high
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`temperature of about 180 degrees, concave-convex portions
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`are formed on a surface of the aluminum due to compressive
`stress between aluminum atoms of the aluminum. Where the
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`data line includes aluminum, the aluminum makes contact
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`with a conductive adhesive layer (which may be an N+
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`doped amorphous silicon layer under the data line) that
`enhances the contact resistance between the aluminum and
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`the conductive adhesive layer. The enhanced contact resis-
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`tance causes the aluminum to disperse into the conductive
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`adhesive layer under high temperature, forming the irregu-
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`larity.
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`[0009] Further, when the conductive adhesive layer is
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`etched to form a channel layer, the conductive adhesive layer
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`pattern is exposed outside the source electrode, the drain
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`electrode or the data line. As a result, an undesirable
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`after-image occurs on the liquid crystal display apparatus.
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`Page 17 of 26
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`[0010] A method of forming a display apparatus without
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`the above problems is desired.
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`SUMMARY OF THE INVENTION
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`[0011] The present invention provides a thin film transistor
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`for a display apparatus.
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`[0012] The present invention also provides a method suit-
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`able for manufacturing the above thin film transistor.
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`[0013] The present invention also provides a display appa-
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`ratus having the above thin film transistor.
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`[0014] The present invention also provides a method suit-
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`able for manufacturing the above display apparatus.
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`[0015]
`In one aspect of the present invention, a thin film
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`transistor includes a gate electrode on a substrate, a gate
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`insulating layer on the substrate to insulate the gate elec-
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`trode, a channel pattern, a source electrode and a drain
`electrode.
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`[0016] The channel pattern includes a semiconductor pat-
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`tern on the gate electrode such that
`the semiconductor
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`pattern overlays the gate electrode, a first conductive adhe-
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`sive pattern on the semiconductor pattern, and a second
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`conductive adhesive pattern formed on the semiconductor
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`pattern and spaced apart from the first conductive adhesive
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`pattern. The source electrode includes a first barrier pattern,
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`a source pattern and a first capping pattern sequentially
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`formed on the first conductive adhesive pattern. The drain
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`electrode includes a second barrier pattern, a drain pattern
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`and a second capping pattern sequentially formed on the
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`second conductive adhesive pattern.
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`[0017]
`invention, a
`In another aspect of the present
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`method of manufacturing a thin film transistor is provided as
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`follows. A gate electrode and a gate insulating layer are
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`sequentially formed on a substrate. A semiconductor layer
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`and a conductive adhesive layer are formed on the gate
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`insulating layer such that the semiconductor layer and the
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`conductive adhesive layer overlay the gate electrode. A
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`barrier layer, a conductive thin layer and a capping layer are
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`deposited over the substrate. The capping layer and the
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`conductive thin layer are partially etched to form a first
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`capping pattern, a second capping pattern spaced apart from
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`the first capping pattern, a source pattern and a drain pattern
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`spaced apart from the source pattern on the gate electrode.
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`The barrier layer and the conductive adhesive layer are
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`partially etched to form a first barrier pattern, a second
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`barrier pattern spaced apart from the first barrier pattern, a
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`first conductive adhesive pattern and a second adhesive
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`pattern spaced apart from the first conductive adhesive
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`pattern on the gate electrode.
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`[0018]
`In still another aspect of the present invention, a
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`display apparatus includes a first display substrate having a
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`thin film transistor and a pixel electrode electrically con-
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`nected to the drain electrode, a second display substrate and
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`a liquid crystal layer between the first and second substrates.
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`[0019] The thin film transistor includes a gate electrode on
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`a first substrate, a gate insulating layer on the first substrate
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`to insulate the gate electrode, a channel pattern, a source
`electrode and a drain electrode.
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`[0020] The channel pattern includes a semiconductor pat-
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`tern on the gate electrode such that
`the semiconductor
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`Page 17 of 26
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`

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`US 2006/0118786 A1
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`Jun. 8, 2006
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`pattern overlays the gate electrode, a first conductive adhe-
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`sive pattern on the semiconductor pattern, and a second
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`conductive adhesive pattern spaced apart from the first
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`conductive adhesive pattern on the semiconductor pattern.
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`The source electrode includes a first barrier pattern, a source
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`pattern and a first capping pattern sequentially formed on the
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`first conductive adhesive pattern. The drain electrode
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`includes a second barrier pattern on the second barrier
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`pattern, a drain pattern and a second capping pattern sequen-
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`tially formed on the second conductive adhesive pattern.
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`[0021] The second display substrate includes a second
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`substrate facing the first substrate and a common electrode
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`facing the pixel electrode.
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`[0022]
`In further still another aspect of the present inven-
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`tion, a method of manufacturing a display apparatus is
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`provided as follows. A gate electrode and a gate insulating
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`layer are sequentially formed on a first substrate. A semi-
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`conductor layer, a conductive adhesive layer, a barrier layer,
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`a conductive thin layer and a capping layer are sequentially
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`formed on the gate insulating layer. The capping layer and
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`the conductive thin layer are partially etched to form a first
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`capping pattern, a second capping pattern spaced apart from
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`the first capping pattern, a source pattern and a drain pattern
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`spaced apart from the source pattern on the gate electrode.
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`The barrier layer and the conductive adhesive layer are
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`partially etched to form a first barrier pattern, a second
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`barrier pattern spaced apart from the first barrier pattern, a
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`first conductive adhesive pattern and a second conductive
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`adhesive pattern spaced apart from the first conductive
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`pattern on the gate electrode. The pixel electrode is electri-
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`cally connected to the drain electrode. A common electrode
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`is formed on a second substrate facing the first substrate. A
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`liquid crystal layer is formed between the first and second
`substrates.
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`[0023] According to the above, the barrier pattern and the
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`conductive adhesive pattern are formed by the dry etching
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`so that
`the display apparatus may prevent
`process,
`the
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`residues of the conductive adhesive pattern around the
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`source and drain electrodes and improve the display quality
`thereof.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`[0024] The above and other advantages of the present
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`invention will become readily apparent by reference to the
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`following detailed description when considered in conjunc-
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`tion with the accompanying drawings wherein:
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`[0025] FIG. 1 is a schematic circuit diagram showing a
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`thin film transistor according to an exemplary embodiment
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`of the present invention;
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`[0026] FIG. 2 is a plan view showing the thin film
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`transistor in FIG. 1;
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`[0027] FIG. 3 is a cross-sectional view taken along a line
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`I 1'12 showing the thin film transistor in FIG. 2;
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`[0028] FIGS. 4 to 11 are cross-sectional views illustrating
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`a manufacturing method of the thin film transistor in FIG.
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`3;
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`[0029] FIG. 12 is an equivalent circuit diagram showing
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`a display apparatus according to an exemplary embodiment
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`of the present invention;
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`Page 18 of 26
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`[0030] FIG. 13 is a plan view showing the display appa-
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`ratus having the thin film transistor in FIG. 3;
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`[0031] FIG. 14 is a cross-sectional view taken along a line
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`II l-II2 showing the display apparatus in FIG. 13; and
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`[0032] FIGS. 15 to 24 are cross-sectional views illustrat-
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`ing a manufacturing method of the display apparatus shown
`in FIG. 14.
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`DESCRIPTION OF THE EMBODIMENTS
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`[0033]
`It will be understood that when an element or layer
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`is referred to as being “on”, “connected to” or “coupled to”
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`another element or layer, it can be directly on, connected or
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`coupled to the other element or layer or intervening elements
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`or layers may be present. In contrast, when an element is
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`referred to as being “directly on,”“directly connected to” or
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`“directly coupled to” another element or layer, there are no
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`intervening elements or layers present. Like numbers refer to
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`like elements throughout. As used herein, the term “and/or”
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`includes any and all combinations of one or more of the
`associated listed items.
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`[0034]
`It will be understood that, although the terms first,
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`second, etc. may be used herein to describe various ele-
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`ments, components, regions, layers and/or sections, these
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`elements, components,
`regions,
`layers and/or
`sections
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`should not be limited by these terms. These terms are only
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`used to distinguish one element, component, region, layer or
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`section from another region, layer or section. Thus, a first
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`element, component,
`region,
`layer or section discussed
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`below could be termed a second element, component,
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`region, layer or section without departing from the teachings
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`of the present invention.
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`“beneath”,
`such as
`[0035]
`Spatially relative terms,
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`“below”, “lower”, “above”, “upper” and the like, may be
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`used herein for ease of description to describe one element
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`or feature’s relationship to another element(s) or feature(s)
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`as illustrated in the figures. It will be understood that the
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`spatially relative terms are intended to encompass different
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`orientations of the device in use or operation in addition to
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`the orientation depicted in the figures. For example, if the
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`device in the figures is turned over, elements described as
`“below” or “beneath” other elements or features would then
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`be oriented “above” the other elements or features. Thus, the
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`exemplary term “below” can encompass both an orientation
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`of above and below. The device may be otherwise oriented
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`(rotated 90 degrees or at other orientations) and the spatially
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`relative descriptors used herein interpreted accordingly.
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`[0036] The terminology used herein is for the purpose of
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`describing particular embodiments only and is not intended
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`to be a limitation of the invention. As used herein,
`the
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`singular forms, “a”, “an” and “the” are intended to include
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`the plural forms as well, unless the context clearly indicates
`otherwise.
`It will be further understood that
`the terms
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`“includes” and/or “including”, when used in this specifica-
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`tion, specify the presence of stated features, integers, steps,
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`operations, elements, and/or components, but do not pre-
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`clude the presence or addition of one or more other features,
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`integers, steps, operations, elements, components, and/or
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`groups thereof.
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`[0037] Unless otherwise defined, all terms (including tech-
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`nical and scientific terms) used herein have the same mean-
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`ing as commonly understood by one of ordinary skill in the
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`Page 18 of 26
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`

`

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`US 2006/0118786 A1
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`Jun. 8, 2006
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`art
`It will be further
`to which this invention belongs.
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`understood that terms, such as those defined in commonly
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`used dictionaries, should be interpreted as having a meaning
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`that is consistent with their meaning in the context of the
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`relevant art and will not be interpreted in an idealized or
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`overly formal sense unless expressly so defined herein.
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`[0038] Hereinafter, the present invention will be explained
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`in detail with reference to the accompanying drawings.
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`[0039] FIG. 1 is a schematic circuit diagram showing a
`
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`
`
`thin film transistor according to an exemplary embodiment
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`of the present invention. FIG. 2 is a plan view of the thin
`film transistor in FIG. 1. FIG. 3 is a cross-sectional view
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`taken along a line 11-12 shown in FIG. 2.
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`[0040] Referring to FIG. 1, a thin film transistor TFT
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`includes a gate line GL from which a gate electrode 110 is
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`branched, a data line DL from which a source electrode 130
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`is branched and a drain electrode 140 spaced apart from the
`source electrode 130.
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`[0041] The gate line GL has a stripe shape and is formed
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`on a substrate. The gate line GL transmits a gate signal
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`externally provided to the gate electrode 110.
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`[0042] The data line DL is also formed on the substrate.
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`The data line DL is substantially perpendicular to the gate
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`line GL and electrically insulated from the gate line GL. The
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`data line DL transmits a data signal to the source electrode
`130.
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`[0043] When a gate voltage that is higher than a threshold
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`voltage of the thin film transistor TFT is applied to the gate
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`electrode 110 through the gate line GL, an electrical char-
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`acteristic of a channel
`layer formed inside the thin film
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`transistor TFT is changed from an insulator to a conductor
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`such that the data signal applied to the source electrode 130
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`is applied to the drain electrode 140 through the channel
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`layer.
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`[0044] Referring to FIGS. 2 and 3, the thin film transistor
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`TFT includes the gate electrode 110, a gate insulating layer
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`115, a channel pattern 120, the source electrode 130 and the
`drain electrode 140.
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`[0045] The gate electrode 110 is branched from the gate
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`line GL formed on the substrate. The gate electrode 110
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`includes a metal material or a metal alloy, such as molyb-
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`denum (Mo), aluminum (Al), chromium (Cr), copper (Cu),
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`neodymium (Nd) and so on. In the present embodiment, the
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`gate electrode 110 may be formed as a single-layer or a
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`double-layer structure containing aluminum-neodymium
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`(AliNd) and molybdenum (Mo).
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`[0046] When a gate voltage that is higher than the thresh-
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`old voltage of the thin film transistor TFT is applied to the
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`gate electrode 110 through the gate line GL, a channel is
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`formed at the channel pattern 120 electrically connected to
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`the source electrode 130 and the drain electrode 140. Thus,
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`the data signal applied to the data line DL is transmitted to
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`the drain electrode 140 through the source electrode 130. On
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`the contrary, when the gate voltage that has a lower voltage
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`level than the threshold voltage of the thin film transistor
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`TFT is applied to the gate electrode 110 through the gate line
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`GL, the channel is not formed at the channel pattern 120
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`electrically connected to the source and drain electrodes 130
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`and 140. Thus, the data signal applied to the data line DL is
`not transmitted to the drain electrode 140.
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`Page 19 of 26
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`[0047] The gate insulating layer 115 is formed on the
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`substrate on which the gate electrode 110 is formed, and
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`electrically insulates the gate electrode 110 from the channel
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`pattern 120. The gate insulating layer 115 may include
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`silicon nitride (SiNx) or silicon oxide (SiOx).
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`[0048] The channel pattern 120 is formed on the gate
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`insulating layer 115 corresponding to the gate electrode 110.
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`The channel pattern 120 may include a semiconductor
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`pattern 122, a first conductive adhesive pattern 127a and a
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`second conductive adhesive pattern 127b.
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`[0049] The semiconductor pattern 122 may include amor-
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`phous silicon. When the gate voltage that is applied to the
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`gate electrode 110 is higher than the threshold voltage of the
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`thin film transistor TFT, a channel forms inside the channel
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`pattern 120, thereby electrically connecting the source elec-
`trode 130 and the drain electrode 140. The level of the
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`threshold voltage depends upon a width and a length of the
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`channel pattern 120, and the semiconductor pattern 122 has
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`a thickness from about 2000 to about 2500 angstroms.
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`[0050] The semiconductor pattern 122 includes a recess
`formed thereon. The recess is formed on the semiconductor
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`pattern 122 corresponding to the gate electrode 110. The part
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`of the semiconductor pattern 122 that forms the recess has
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`a thickness of about 500 angstroms. However, in order to
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`prevent damaging the semiconductor pattern 122 due to the
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`recess while the source electrode 130, the drain electrode
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`140 and the channel pattern 120 are formed by an etching
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`process, the semiconductor pattern 122 is formed to have a
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`total thickness from about 2000 to about 2500 angstroms.
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`[0051] The first and second conductive adhesive patterns
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`127a and 12719 are formed on the semiconductor pattern 122
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`and spaced apart from each other. The first and second
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`conductive adhesive patterns 127a and 12719 include N+
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`doped amorphous silicon. The first and second adhesive
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`conductive patterns 127a and 12719 reduce contact resistance
`between the semiconductor 122 and the source and drain
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`electrodes 130 and 140. In the present embodiment, the first
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`and second conductive adhesive patterns 127a and 1271)
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`have a thickness of about 200 angstroms.
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`[0052] The source electrode 130 includes a first barrier
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`pattern 131, a source pattern 133, and a first capping pattern
`135. The drain electrode 140 includes a second barrier
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`pattern 141, a drain pattern 143, and a second capping
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`pattern 145.
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`[0053] The first and second barrier patterns 131 and 141
`are formed on the first and second conductive adhesive
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`patterns 127a and 127b, respectively. The first and second
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`barrier patterns 131 and 141 prevent dispersion of a con-
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`ductive metal of the source and drain patterns 133 and 143,
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`respectively.
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`[0054] The first and second barrier patterns 131 and 141
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`may be used as an etch-stop layer during the formation of the
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`source and drain patterns 133 and 143 and the first and
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`second capping patterns 135 and 145. The first and second
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`barrier patterns 131 and 141 have an etch selectivity with
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`respect to the source and drain patterns 133 and 143 and the
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`first and second capping patterns 135 and 145. The first and
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`second barrier patterns 131 and 141 include titanium (Ti),
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`tantalum (Ta), tungsten (W), chromium (Cr) and so on.
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`[0055] The source and drain patterns 133 and 143 apply
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`the data signal to the data line DL. In order to prevent signal
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`Page 19 of 26
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`US 2006/0118786 A1
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`Jun. 8, 2006
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`delay and signal distortion due to elongation of th