`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria1 Virginia 22313- 1450
`www.uspto.gov
`
`APPLICATION NO.
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`
`
`
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` F ING DATE
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`FIRST NAMED INVENTOR
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`ATTORNEY DOCKET NO.
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`
`
`
`
`CONF {MATION NO.
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`11/502,458
`
`08/11/2006
`
`Ryutaro Oke
`
`HITA—0864
`
`8301
`
`7590
`08’0““
`JuancaflosAMmq —
`
`
`TUNG, DAV )
`c/o Stites & Harbison PLLC
`
`1199 North Fairfax Street
`9119999
`Alexandria, VA 223 14- 1437
`
`EEEEEEEEEEE
`
`2694
`
`
`
`
`NOT *ICATION DATE
`
`DELIVERY MODE
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`08/06/2013
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`ELECTRONIC
`
`Please find below and/0r attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above—indicated "Notification Date" to the
`following e—mail address(es):
`
`iplaw @ stites.com
`
`PTOL—90A (Rev. 04/07)
`
`

`

`
`
`Applicant(s)
`Application No.
` 11/502,458 OKE ET AL.
`
`
`AIA (First Inventorto File)
`Art Unit
`Examiner
`Office Action Summary
`
`
`DAVID TUNG first“ 2694
`-- The MAILING DA TE of this communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`
`
`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE 3 MONTH(S) OR THIRTY (30) DAYS,
`WHICHEVER IS LONGER, FROM THE MAILING DATE OF THIS COMMUNICATION.
`Extensions of time may be available under the provisions of 37 CFR 1.136(a).
`In no event however may a reply be timely filed
`after SIX () MONTHS from the mailing date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any
`earned patent term adjustment. See 37 CFR 1.704(b).
`
`-
`-
`
`Status
`
`1)IXI Responsive to communication(s) filed on 19 December 2012.
`[I A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/were filed on
`
`2b)lX| This action is non-final.
`a)I:| This action is FINAL.
`3)I:I An election was made by the applicant in response to a restriction requirement set forth during the interview on
`
`
`; the restriction requirement and election have been incorporated into this action.
`
`4)|:I Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under EX parte Quay/e, 1935 CD. 11, 453 O.G. 213.
`
`Disposition of Claims
`
`5)|XI Claim(s) 1-35 10 1213 and 15 is/are pending in the application.
`5a) Of the above claim(s)
`is/are withdrawn from consideration.
`6)|:l Claim(s) _ is/are allowed.
`
`7)IZ| Claim(s) 1-35 10 12 13 and 15is/are rejected.
`8)I:I Claim(s) _ is/are objected to.
`
`9)|:l Claim((s)
`are subject to restriction and/or election requirement.
`* If any claims have been determined allowable, you may be eligible to benefit from the Patent Prosecution Highway program at a
`
`participating intellectual property office for the corresponding application. For more information, please see
`htt
`://www.usoto. ov/ atents/init events"
`
`
`
`h/index.‘s or send an inquiry to PF"I-Ifeedback{<‘buspto.qov.
`
`Application Papers
`
`10)I:I The specification is objected to by the Examiner.
`11)|:I The drawing(s) filed on _ is/are: a)I:I accepted or b)I:I objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`12)IZI Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
`Certified copies:
`
`b)I:I Some * c)I:I None of the:
`a)le All
`1.|ZI Certified copies of the priority documents have been received.
`2.|:| Certified copies of the priority documents have been received in Application No.
`3.|:I Copies of the certified copies of the priority documents have been received in this National Stage
`
`application from the International Bureau (PCT Rule 17.2(a)).
`* See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`1) D Notice of References Cited (PTO-892)
`
`3) I] Interview Summary (PTO-413)
`
`Paper NOISI/Ma” Date —
`PTO/SB/08
`t
`St t
`I
`D'
`t'
`f
`2 I:l I
`)
`4) I:I Other:
`a emen (s)(
`Isc osure
`n orma Ion
`)
`Paper No(s)/Mai| Date
`US. Patent and Trademark Office
`PTOL-326 (Rev. 05-13)
`
`Part of Paper No./Mai| Date 20130625
`
`Office Action Summary
`
`

`

`Application/Control Number: 11/502,458
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`Page 2
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`Art Unit: 2694
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`DETAILED ACTION
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`Continued Examination Under 37 CFR 1. 114
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`1.
`
`A request for continued examination under 37 CFR 1.114, including the fee set
`
`forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this
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`application is eligible for continued examination under 37 CFR 1.114, and the fee set
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`forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action
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`has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on
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`12/19/2012 has been entered.
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`2.
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`Applicant's arguments filed 10/31/2012 have been fully considered.
`
`Response to Arguments
`
`Regarding the rejection of claim 1, the Applicant argues [Remarks: pg. 6, 2nd
`
`para. - pg. 7, 3rd para.], Yun does not teach “a third set of dummy pixels that are not
`
`provided with TFT elements is arranged between the first set of dummy pixels or
`
`between the second set of dummy pixels”, as claimed in claim 1.
`
`The Office respectfully disagrees.
`
`Applicant’s interpretation of Yun is incorrect.
`
`Please refer to paragraph 206 and figure 26. The claims require that the dummy
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`pixels be located outside an effective display region.
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`In paragraph 206, it is specifically
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`described that the dummy pixels are provided in a left non display area, when
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`

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`Application/Control Number: 11/502,458
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`Page 3
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`Art Unit: 2694
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`connected to d1 and a right non-display area when connected to d|m+1. Thus the
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`dummy pixels are located in the perimeter of the display, outside the display area in the
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`non-display area.
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`In addition, the effective display region is from data line Dl2 to data line Dlm since
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`image data is always provided to data lines Dl2 to Dlm.
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`Therefore, Yun teaches the claim limitation.
`
`Regarding the rejection of claim 1, the Applicant argues [Remarks: pg. 7, 4th
`
`para. - pg. 8, 3rd para], “Moreover, even were the assertion by the Examiner that, in
`
`Figure 26 of Yun, "the effective display region is from DL2 to DLm and GL2 to GLn-f
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`first set is DLI dummy pixels, second set is DLm+1 dummy pixels" to actually be
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`accurate, Applicants note that claim 1 further requires that the first drain electrode line
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`be "adjacent to the first end portion of the effective display region" and that the second
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`drain electrode line be "adjacent to the third end portion of the effective display region."
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`In this regard, Applicants note that the Examiner, on pages 3-5 of the Final Office
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`Action, cites the data lines DLI and DLm+1 as respectively teaching the first and second
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`drain electrode lines required by claim 1.
`
`If the effective display region of the liquid
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`crystal display panel 252 in Figure 26 of Yun were to extend only from DL2 to DLm as
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`asserted by the Examiner, however, the data lines DL1 and DLm+1 would very clearly
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`not be adjacent to respective end portions of the effective display region of the liquid
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`crystal display panel 252. Rather, the data lines DL1 and DLm+1 would clearly be
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`separated from the respective end portions of the effective display region of the liquid
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`

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`Application/Control Number: 11/502,458
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`Page 4
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`Art Unit: 2694
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`crystal display panel 252 by the liquid crystal cells illustrated as being connected to the
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`data line DL1 and the liquid crystal cells illustrated as being connected to the data line
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`DLm+1.
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`Accordingly, it is clear that Yun fails to teach or suggest that "a third set of
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`dummy pixels...is arranged between the first set of dummy pixels or between the
`
`second set of dummy pixels" are required by claim 1. Likewise, each of AAPA,
`
`Kageyama, and Lee fails to include any mention or suggestion of this required limitation
`
`of claim 1.”
`
`The Office respectfully disagrees.
`
`The Applicant has not specifically claimed the first set of dummy pixels, the
`
`second set of dummy pixels, and the third set of dummy pixels.
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`By having the perimeter of the effective display region [effective display region is
`
`between Dl2 and Dlm] be dummy pixels, one can group it such that the third is between
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`the first set of dummy pixels or the second set of dummy pixels.
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`In addition, DH and Dlm+1 define the adjacent boundary between the effective
`
`display region [from Dl2 and Dlm].
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`Thus, DH and Dlm+1 are adjacent to the first end portion and third end portion
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`respectively.
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`Therefore, Yun teaches the claim limitation.
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`

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`Application/Control Number: 11/502,458
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`Page 5
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`Art Unit: 2694
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`Regarding the rejection of claim 1, the Applicant argues [Remarks: pg. 8, 4th
`
`para. - pg. 10, 3rd para], Park does not teach “a third set of dummy pixels that are not
`
`provided with TFT elements is arranged between the first set of dummy pixels or
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`between the second set of dummy pixels”, as claimed in claim 1.
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`The Office respectfully disagrees.
`
`In response to applicant's arguments against the references individually, one
`
`cannot show nonobviousness by attacking references individually where the rejections
`
`are based on combinations of references. See In re Keller, 642 F.2d 413, 208
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`USPQ 871 (CCPA 1981); In re Merck& CO., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir.
`
`1986).
`
`Please see response above.
`
`As to amended claim limitation of claim 1, please refer to office action below.
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`Claim Rejections - 35 USC § 103
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`3.
`
`The text of those sections of Title 35, U.S. Code not included in this action can
`
`be found in a prior Office action.
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`4.
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`Claims 1-3, 5, 12, 13 and 15 are rejected under pre-AlA 35 U.S.C. 103(a) as
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`being unpatentable over Yun (US 20030197672), in view of the Applicant's Admitted
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`Prior Art (AAPA) and Park (us 20060120160).
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`

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`Application/Control Number: 11/502,458
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`Page 6
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`Art Unit: 2694
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`Regarding Claim 1, Yun A display device including a display panel having a first
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`substrate and a second substrate (Yun, Fig. 14 and 26 element 132 paragraph [0007]),
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`the first substrate including a plurality of drain electrode lines (Yun, Figs. 14 and 18
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`DLn), a plurality of gate electrode lines (Yun, Figs. 14 and 26 GLn) and a plurality of
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`pixels (Yun, Figs. 14 and 26 element 131 and 133), each pixel of the plurality of pixels
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`having a respective TFT element (Yun, Figs. 14 and 26 element 131 ), a respective
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`pixel electrode, and a respective counter electrode arranged therein (Yun, Figs. 14 and
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`26, TFTs 131 and pixel electrodes 133 and counter electrodes not shown), wherein
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`the first substrate includes a first set of dummy pixels and a second set of
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`dummy pixels (Yun, Figs. 14 and 26 display region is the rectangular region without
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`the dummy pixels, dummy pixels are 151 153 and 161 163 but in Fig. 26 they are all of
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`the perimeter pixels meaning that the effective display region is from DL2 to DLm and
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`GL2 to GLn-1 first set is DL1 dummy pixels, second set is DLm+1 dummy pixels),
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`the first set of dummy pixels has at least TFT elements located outside a first end
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`portion of the effective display region in an extending direction of the gate electrode
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`lines out of the first end portion of the effective display region along a first drain
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`electrode line adjacent to the first end portion of the effective display region (Yun, Figs.
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`26 dummy pixels attached to DL1 and even gate lines), and
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`the TFT elements of the first set of dummy pixels are connected with even
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`numbered gate electrode lines of the gate electrode lines as counted from a second end
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`

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`Application/Control Number: 11/502,458
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`Page 7
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`Art Unit: 2694
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`portion of the effective display region in an extending direction of the drain electrode
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`lines (Yun, Figs. 26 dummy pixels attached to DL1 even gate lines),
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`the second set of dummy pixels has at least TFT elements located outside a third
`
`end portion of the effective display region in the extending direction of the gate
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`electrode lines out of the third end portion of the effective display region along a second
`
`drain electrode line adjacent to the third end portion of the effective display region (Yun,
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`Fig. 26 dummy pixels attached to DLm+1 odd gate lines),
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`the TFT elements of the second set of dummy pixels are connected with odd
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`number gate electrode lines of the gate electrode lines as counted from the second end
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`portion of the effective display region in the extending direction of the drain electrode
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`lines (Yun, Fig. 26 dummy pixels attached to DLm+1 odd gate lines),
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`the respective TFT elements arranged in the pixels that are arranged on both
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`sides of each drain electrode line are alternately connected with the drain electrode line
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`along the extending direction of the drain electrode lines (Yun, Fig. 26 alternately
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`connected TFT in the drain electrode line extending direction),
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`each of the first and second drain electrode lines is connected with a plurality of
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`TFT elements that are arranged within the effective display region (Yun, Fig. 26 DL1
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`and Dlm+1 connected to) and a respective plurality of dummy pixels of one of the first
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`and second sets of dummy pixels that are arranged outside of the effective display
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`region such that the dummy pixels of the respective plurality of dummy pixels are
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`

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`Application/Control Number: 11/502,458
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`Page 8
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`Art Unit: 2694
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`alternately connected with the corresponding drain electrode line along the extending
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`direction of the drain electrode line (Yun, Fig. 18 and 21 the left and right most data
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`lines are connected to both dummy and display region pixels),
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`a third set of dummy pixel is arranged between the first set of dummy pixels or
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`between the second set of dummy pixels (Yun, Fig. 26 additional third dummy pixels are
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`located between the second set of dummy pixels connected to Dm+1 and the even gate
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`lines),
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`the third dummy pixel has a dummy electrode layer on a same conductive layer
`
`as the pixel electrodes of the first and second sets of dummy pixels (Yun, Fig. 26 the
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`dummy pixels have exact same structure as the normal pixels).
`
`Yun fails to teach wherein the first substrate includes a plurality of common
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`signal lines as claimed, but instead teaches that the common signals are provided from
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`the second substrate.
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`AAPA teaches where the common signal lines are provided on the first
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`substrate (AAPA, Fig. 31 element CL),
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`a common potential conductive layer is formed parallel to and outside of one of
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`the first and second drain electrode lines located at an end portion of the extending
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`direction of the gate electrode lines (AAPA, Fig. 31 element CL has vertical lines formed
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`parallel to the drain electrode lines), and
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`

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`Application/Control Number: 11/502,458
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`Page 9
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`Art Unit: 2694
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`the common potential conductive layer is connected to the plurality of common
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`signal lines in a region adjacent to the respective plurality of dummy pixels that are
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`connected to the drain electrode line of which the common potential conductive layer is
`
`formed outside (AAPA, Fig. 31 CL has the conductive layer formed on the perimeter of
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`the display and is connected to all the common lines extending across the display in the
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`horizontal direction).
`
`It would have been obvious to one of ordinary skill in the art at the time of the
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`invention to use the first substrate to hold the common electrodes, as taught by AAPA,
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`instead of the second so that all the driving circuitry can be located on the first substrate
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`and easily attached to all the electrode supply lines, as one of ordinary skill in the art
`
`would appreciate.
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`Yun in view of the AAPA further teaches wherein the dummy electrode layer of
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`the third set of dummy pixels is electrically connected to the common potential
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`conductive layer (Yun, Figs. 14, 18 and 26, dummy pixel construction can be the same
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`as normal pixel construction so the dummy electrode layer is also connected to the
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`common potential just like other pixels, AAPA Fig. 31 CL).
`
`Yun in view of the AAPA fails to teach wherein the third set of dummy pixels is
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`not provided with TFT elements.
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`Park teaches wherein the TFTs can be omitted for dummy pixels (Park, Fig. 3 L1
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`L2, paragraph [0050] Qs are the connectors, and can be omitted for dummy lines).
`
`

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`Application/Control Number: 11/502,458
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`Page 10
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`Art Unit: 2694
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`It would have been obvious to one of ordinary skill in the art at the time of the
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`invention to modify the third dummy pixels of the display device of Yun as modified by
`
`AAPA, such that the TFTs of the third dummy pixels are omitted, as taught by Park, in
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`order to save cost and reduce manufacturing complexity, as one of ordinary skill in the
`
`art would appreciate.
`
`Regarding Claim 2, Yun further teaches wherein the end portion of the effective
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`display region on which the first set of dummy pixels are arranged constitutes an input
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`end side of the gate electrode lines (Yun, Figs. 18 and 26).
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`Regarding Claim 3, Yun further teaches wherein the first and the second sets of
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`dummy pixels have a same constitution as the pixels within the effective display region
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`(Yun, Figs. 18 and 21 dummy pixels are physically the same as the regular pixels).
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`Regarding Claim 5, Yun further teaches wherein a dummy drain electrode line is
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`provided outside the first or the second sets of dummy pixels (Yun, Figs. 18 and 21
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`dummy DL lines are clearly provided outside of the dummy pixels).
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`Regarding Claim 12, Yun further teaches wherein a signal of the same polarity is
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`applied to the drain electrode line during one frame period Yun, Figs. 20A and 20B).
`
`Regarding Claim 13, Yun further teaches wherein signals having polarities
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`opposite to each other are applied to two neighboring drain electrode lines (Yun, Figs.
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`18 and 21, 1x1 polarity inversion).
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`

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`Application/Control Number: 11/502,458
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`Page 11
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`Art Unit: 2694
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`Regarding Claim 15, Yun in view of the AAPA further teaches wherein the
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`common potential conductive layer is formed in a same layer as the pixel electrodes,
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`and the common signal lines are formed in a same layer as the gate electrode lines
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`(AAPA, Fig. 31 element CL).
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`Yun in view of the AAPA also inherently teaches wherein the common potential
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`conductive layer is connected to the common signal lines via a through hole. According
`
`to the diagram detailed by Fig. 31 since all common buses are located on the first
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`substrate and the counter electrodes are located on the opposing substrate there must
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`inherent/y exist because that is the only way to extend electrodes from the first
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`substrate to the second substrate.
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`5.
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`Claim 10 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over
`
`Yun in view of the AAPA and Park, and further in view of Lee (US 7271868).
`
`Regarding Claim 10, Yun further teaches a TFT region is arranged outside the
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`effective display region each time the drain electrode line traverses two gate electrode
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`lines (Yun, Figs. 26 drain electrodes outside of the display region forms TFTs every two
`
`gate lines) but fails to teach that the TFT elements are shielded from light as claimed.
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`Lee teaches wherein a region where the TFT element is arranged each time the
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`drain electrode line traverses two gate electrode lines is shielded from light (Col. 5 lines
`
`

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`Application/Control Number: 11/502,458
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`Page 12
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`Art Unit: 2694
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`14-24 light shielding layer shields light leaked from the TFT element which in turn is also
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`shielded from light).
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`It would have been obvious to one of ordinary skill in the art at the time of the
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`invention to add a light shielding layer as taught by Lee to the display device of Yun in
`
`order to prevent light leakage.
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`Conclusion
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`6.
`
`Any inquiry concerning this communication or earlier communications from the
`
`examiner should be directed to DAVID TUNG whose telephone number is (571 )270-
`
`3385. The examiner can normally be reached on Monday - Friday; 9:00AM - 5:00PM.
`
`If attempts to reach the examiner by telephone are unsuccessful, the examiner’s
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`supervisor, Sumati Lefkowitz can be reached on (571)272-3638. The fax phone
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`number for the organization where this application or proceeding is assigned is 571 -
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`273-8300.
`
`

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`Application/Control Number: 11/502,458
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`Page 13
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`Art Unit: 2694
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`Information regarding the status of an application may be obtained from the
`
`Patent Application Information Retrieval (PAIR) system. Status information for
`
`published applications may be obtained from either Private PAIR or Public PAIR.
`
`Status information for unpublished applications is available through Private PAIR only.
`
`For more information about the PAIR system, see http://pair-direct.uspto.gov. Should
`
`you have questions on access to the Private PAIR system, contact the Electronic
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`Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a
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`
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`
`/David Tung/
`Examiner, Art Unit 2694
`7/30/2013
`
`/Seokyun Moon/
`Primary Examiner, Art Unit 2694
`
`