`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`www.uspto.gov
`
`APPLICATION NO.
`
`
`
`
` FILING DATE
`
`
`FIRST NAMED INVENTOR
`
`ATTORNEY DOCKET NO.
`
`
`
`
`CONFIRMATIONNO.
`
`
`11/965,819
`
`12/28/2007
`
`Yasuhiro Tanaka
`
`1497 .48334X00
`
`4135
`
`20457
`
`7590
`
`06/18/2013
`
`ANTONELLI, TERRY, STOUT & KRAUS, LLP
`1300 NORTH SEVENTEENTH STREET
`SUITE 1800
`ARLINGTON,VA 22209-3873
`
`BRAY, STEPHEN A
`
`2691
`
`MAIL DATE
`
`06/18/2013
`
`DELIVERY MODE
`
`PAPER
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`PTOL-90A (Rev. 04/07)
`
`

`

`
`Application No.
`Applicant(s)
`
` 11/965,819 TANAKAET AL.
`Office Action Summary
`Examiner
`Art Unit
`AIA (First Inventor toFile)
`
`
`2691STEPHEN BRAY No
`-- The MAILING DATEof this communication appears on the cover sheet with the correspondence address--
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLYIS SET TO EXPIRE 3 MONTH(S) OR THIRTY(30) DAYS,
`WHICHEVER IS LONGER, FROM THE MAILING DATE OF THIS COMMUNICATION.
`Extensions of time may be available under the provisions of 37 CFR 1.136(a).
`In no event, however, may a reply be timely filed
`after SIX (6) MONTHS from the mailing date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, evenif timely filed, may reduce any
`earned patent term adjustment. See 37 CFR 1.704(b).
`
`-
`-
`
`Status
`1)] Responsive to communication(s) filed on1February2013.
`L] A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/were filedon___
`2a)L] This action is FINAL.
`2b)X] This action is non-final.
`3)L] An election was made bythe applicant in responseto a restriction requirementset forth during the interview on
`
`; the restriction requirement and election have been incorporated into this action.
`4)L] Sincethis application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordancewith the practice under Ex parte Quayle, 1935 C.D. 11, 453 O.G. 213.
`
`
`
`Disposition of Claims
`5) Claim(s) 1-17 and 13-20 is/are pending in the application.
`
`5a) Of the above claim(s)
`is/are withdrawn from consideration.
`
`6)L] Claim(s)
`is/are allowed.
`7) Claim(s) 1-17 and 13-20 is/are rejected.
`8)L] Claim(s)___ is/are objectedto.
`
`9)L] Claim(s)
`are subjectto restriction and/or election requirement.
`* If any claims have been determined allowable, you may be eligible to benefit from the Patent Prosecution Highway program at a
`participating intellectual property office for the corresponding application. For more information, please see
`
`nite://www.usoto.dov/patenis/init events/oph/index.isp
`
`or send an inquiry to PPHieedback@uspte.dov.
`
`Application Papers
`10) The specification is objected to by the Examiner.
`
`11) The drawing(s) filed on
`is/are: a)[_] accepted or b)[_] objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`12)L] Acknowledgment is made ofa claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
`Certified copies:
`a)LJ All
`b)L] Some* c)L] None ofthe:
`1.) Certified copies of the priority documents have been received.
`2.L] Certified copies of the priority documents have been received in Application No.
`3.L] Copies of the certified copies of the priority documents have been receivedin this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`“ See the attached detailed Office action for a list of the certified copies not received.
`Interim copies:
`a)LI All
`b)LJ Some
`
`Interim copies of the priority documents have been received.
`
`c)L) None of the:
`
`Attachment(s)
`3) TC Interview Summary (PTO-413)
`1) X Notice of References Cited (PTO-892)
`Paper No(s)/Mail Date.
`;
`;
`oO Other
`2) CT] Information Disclosure Statement(s) (PTO/SB/08)
`Paper No(s)/Mail Date
`U.S. Patent and Trademark Office
`PTOL-326 (Rev. 03-13)
`
`Office Action Summary
`
`Part of Paper No./Mail Date 20130613
`
`

`

`Application/Control Number: 11/965,819
`Art Unit: 2691
`
`Page 2
`
`Continued Examination Under 37 CFR 1.114
`
`1.
`
`A requestfor continued examination under 37 CFR 1.114, including the fee set
`
`forth in 37 CFR 1.17(e), wasfiled in this application after final rejection. Since this
`
`application is eligible for continued examination under 37 CFR 1.114, and the fee set
`
`forth in 37 CFR 1.17(e) has beentimely paid, the finality of the previous Office action
`
`has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on
`
`2/01/2013 has been entered.
`
`Responseto Arguments
`
`2.
`
`Applicant’s arguments with respect to claim 1 have been considered but are
`
`moot because the arguments do not apply to any of the references being used in the
`
`current rejection.
`
`3.
`
`Applicant’s arguments, see Pages 9-11 of the Applicant’s submission, filed
`
`2/01/2013, with respectto the rejection(s) of claim(s) 15-20 under 35 U.S.C. § 103(a)
`
`have beenfully considered and are persuasive. Therefore, the rejection has been
`
`withdrawn. However, upon further consideration, a new ground(s) of rejection is made
`
`in view of Reznik et al (US 2006/012631 7).
`
`Figures 1-2 and Paragraphs [0032] — [0038] of Reznik et al disclose a printed
`
`circuit board 6 with an integrated circuit (IC) chip 1, whereafirst pattern 7 and a second
`
`pattern 61 are formed on the printed circuit board 6 such that they overlap and form a
`
`decoupling capacitor 30, wherethefirst pattern 7 is supplied with an operating voltage
`
`

`

`Application/Control Number: 11/965,819
`Art Unit: 2691
`
`Page 3
`
`Vcc and the second pattern 61 is supplied with a ground voltage GND. Therefore
`
`Reznik et al discloses the newly added subject matter of Claim 15.
`
`Claim Objections
`
`4.
`
`Claim 13 is objected to becauseof the following informalities:
`
`Claim 13 currently states that it is dependent upon Claim 12, whichis listed as
`
`being canceledin the set of claims received 2/01/2013. The Examinerbelieves that
`
`Claim 13 should be dependent upon Claim 1, as the subject matter of Claim 12 was
`
`incorporatedinto Claim 1.
`
`Appropriate correction is required.
`
`Claim Rejections - 35 USC § 103
`
`5.
`
`This application currently namesjoint inventors.
`
`In considering patentability of
`
`the claims under 35 U.S.C. 103(a), the examiner presumesthat the subject matter of
`
`the various claims was commonly ownedat the time any inventions covered therein
`
`were made absent any evidenceto the contrary. Applicant is advised of the obligation
`
`under 37 CFR 1.56 to point out the inventor and invention dates of each claim that was
`
`not commonly ownedatthe time a later invention was madein orderfor the examinerto
`
`considerthe applicability of 35 U.S.C. 103(c) and potential 35 U.S.C. 102(e), (f) or (g)
`
`prior art under 35 U.S.C. 103(a).
`
`6.
`
`The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all
`
`obviousnessrejections setforth in this Office action:
`
`

`

`Application/Control Number: 11/965,819
`Art Unit: 2691
`
`Page 4
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`(a) A patent may not be obtained though the invention is not identically disclosed or described as set
`forth in section 102 of thistitle, if the differences between the subject matter sought to be patented and
`the prior art are such that the subject matter as a whole would have been obvious at the time the
`invention was made to a person having ordinary skill in the art to which said subject matter pertains.
`Patentability shall not be negatived by the manner in which the invention was made.
`
`7.
`
`Claims 1-2 are rejected under 35 U.S.C. 103(a) as being unpatentable over Saito
`
`et al (US 6,617,521) in view of Koya (US 6,335,862) and Reznik et al (US
`
`2006/0126317).
`
`Regarding claim 1, Saito et a/ discloses a display device (Figure 6 of Saito et al
`
`discloses a display 10.) comprising:
`
`an insulation substrate (Figure 3 of Saito et al discloses having an insulation
`
`substrate 200.);
`
`a flexible board which is connected to the insulation substrate (Figures 1-3 of
`
`Saito et al disclose attaching a flexible printed circuit board 400 to an insulation
`
`substrate 200.); and
`
`a semiconductor chip which is mounted on the flexible board (Figures 1-2 of
`
`Saito et al disclose a semiconductor chip 450 mounted on the flexible printed circuit
`
`board 400.), wherein
`
`the semiconductor chip includesa first long side and a secondlong side (Figures
`
`1-2 of Saito et al disclose that the semiconductor chip 450 hasa first long side anda
`
`second long side.),
`
`first bumps are formed on the semiconductor chip along the first long side and
`
`second bumpsare formed on the semiconductor chip along the second long side
`
`(Figures 1-2 of Saito et al disclose that the semiconductor chip 450 hasfirst bumps
`
`

`

`Application/Control Number: 11/965,819
`Art Unit: 2691
`
`Page 5
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`450a formed along the first long side and second bumps 450b formed on the second
`
`long side.),
`
`the first bumps and the second bumpsare connectedto a plurality of lines
`
`formed onthe flexible board (Figures 1-2 of Saito et al disclose thatthe first bumps
`
`450a and the second bumps 450b are connected to input wiring 420a and output wiring
`
`420b which are formed on the flexible circuit board 400.), and
`
`a pattern formed of a metal layer is formed on the flexible board betweenthe first
`
`bumps and the second bumps(Figures 1-2 and Figures 13-15 of Saito et al disclose
`
`having a dummywiring pattern 422, 23A, 23B, 23C formed on the same layer as the
`
`input wiring and the output wiring, where the dummywiring 422, 23A, 23B, 23C is
`
`formed _on the flexible printed circuit board between the first bumps and the second
`
`bumps.).
`
`Saito et al fails to teach wherein the pattern includesafirst pattern and a second
`
`pattern, the first pattern and second pattern at least partially overlap with each other at a
`
`position below the semiconductor in plan view.
`
`Koya discloses wherein the pattern includesa first pattern and a secondpattern,
`
`the first pattern and second pattern at least partially overlap with each other at a
`
`position below the semiconductor in plan view (Figures 1-2 of Koya disclose forming a
`
`first pattern 84 and a second pattern 88 which partially overlap each other at a position
`
`below an integrated circuit 81.).
`
`

`

`Application/Control Number: 11/965,819
`Art Unit: 2691
`
`Page 6
`
`Therefore it would have been obvious to oneof ordinary skill in the art at the time
`
`the invention was madeto modify the circuit board taught by Saito et a/ with the
`
`teachings of Koya in orderto form a circuit board in which heat dissipation from a
`
`semiconductor device mounted on the circuit board can be improved.
`
`Saito et alas modified abovefails to teach wherein the first pattern and the
`
`second pattern form a capacitance; and
`
`a first voltage is supplied to the first pattern and a second voltage whichis
`
`different from the first voltage is supplied to the second pattern.
`
`Reznik et al discloses wherein the first pattern and the second pattern form a
`
`capacitance (Figures 1-2 and Paragraphs [0032] — [0038] of Reznik et al disclose
`
`forming a capacitance 30 betweenafirst pattern 7 and a second pattern 61.); and
`
`a first voltage is supplied to the first pattern and a second voltage whichis
`
`different from the first voltage is supplied to the second pattern (Figures 1-2 and
`
`Paragraphs [0032] — [0038] of Reznik et al disclose that the first pattern 7 is supplied
`
`with the operating voltage Vcc(i.e. the first voltage.), and the second pattern 61 is
`
`supplied with the ground voltage GND (i.e. the second voltage.).).
`
`Therefore it would have been obvious to oneof ordinary skill in the art at the time
`
`the invention was madeto further modify the circuit board taught by Saito et a/ with the
`
`teachings of Reznik et al such that a printed circuit board containing an Integrated
`
`Circuit has a simple and efficient way to provide low-impedance DC decoupling
`
`between the ground terminal and the supply voltage terminal of the Integrated Circuit.
`
`

`

`Application/Control Number: 11/965,819
`Art Unit: 2691
`
`Page 7
`
`Regarding claim 2, Saito et alas modified above discloses a display device
`
`according to claim 1, wherein the first pattern and the second pattern are separate from
`
`the plurality of lines which are connectedto thefirst and second bumps(Figures 1-2 of
`
`Koya disclose that the first pattern 88 and the second pattern (can be either planar
`
`conductor 84 or through holes 83) are formed separate from the mounting pads 93.
`
`Figures 13-15 of Saito et al also disclose that the dummywiring pattern 422, 23A, 23B,
`
`23C is separate from the input wiring and the output wiring connectedto the first and
`
`second bumps.).
`
`8.
`
`Claims 3-4 and 8-10 are rejected under 35 U.S.C. 103(a) as being unpatentable
`
`over Saito et al (US 6,617,521) and Koya (US 6,335,862) and Reznik et al (US
`
`2006/0126317) as applied to claim 1 above, and further in view of Sasaki et al (US
`
`2007/0126090).
`
`Regarding claim 3, Saito et alas modified above discloses a display device
`
`according to claim 1.
`
`Saito et alas modified abovefails to teach wherein the pattern is at least partially
`
`formed on the flexible board in a state that the pattern extends from a portion of the
`
`flexible board where the semiconductor chip is mounted to a portion of the flexible board
`
`where the semiconductor chip is not mounted.
`
`Sasaki et al discloses wherein the pattern is at least partially formed on the
`
`flexible board in a state that the pattern extends from a portion of the flexible board
`
`

`

`Application/Control Number: 11/965,819
`Art Unit: 2691
`
`Page 8
`
`where the semiconductor chip is mounted to a portion of the flexible board where the
`
`semiconductor chip is not mounted (Figures 1-4 of Sasaki et al disclose that the heat
`
`dissipation patterns, which are formed on a tape base 28 of the tape carrier 20, extend
`
`from the portion of the tape carrier 20 where the semiconductor device 10 is mounted to
`
`a portion of the tape carrier 20 where the semiconductor device 10 is not mounted.),
`
`and the pattern is formed betweenthe flexible board and a protectivefilm in the portion
`
`of the flexible board where the semiconductor chip is not mounted (Paragraph [0072] of
`
`sasaki et al discloses forming the heat dissipation patterns betweenthe tape base 28
`
`and_an insulating layer 29 (i.e. a protective film).).
`
`Therefore it would have been obvious to one of ordinary skill in the art at the time
`
`the invention was madeto further modify the circuit board taught by Saito et a/ with the
`
`teachings of Sasaki et alin order to form a circuit board in which improved heat
`
`dissipation can be achieved from a semiconductor device with a multichannel
`
`configuration and narrowerpitches.
`
`Regarding claim 4, Saito et alas modified above discloses a display device
`
`according to claim 1, wherein the semiconductor chip includesa first short side and a
`
`second short side which are arranged orthogonalto thefirst long side, and the pattern is
`
`formedin a state that the pattern extends from a portion of the flexible board where the
`
`semiconductor chip is mountedto a portion of the flexible board where the
`
`semiconductor chip is not mounted betweenthe first short side and the flexible board
`
`(Figures 1-4 of Sasaki et al disclose that the semiconductor chip 10 has a first short side
`
`

`

`Application/Control Number: 11/965,819
`Art Unit: 2691
`
`Page 9
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`and a second short side which are orthogonalto the first long side, where the heat
`
`dissipation patterns 25 and 26 extend from a portion of the tape carrier 20 where the
`
`semiconductor device 10 is mounted to a portion of the tape carrier 20 where the
`
`semiconductor device 10 is not mounted, where the heat dissipation patterns extend in
`
`a direction away from the first short side of the semiconductor device 10.).
`
`Regarding claim 8, Saito et alas modified above discloses a display device
`
`according to claim 1, wherein an opening is formed in a portion of a region ofthe flexible
`
`board wherethe pattern is partially formed (Figures 2-4 of Sasaki et al disclose forming
`
`a hole 28a in a portion of the tape carrier 20 where heat dissipation pattern 25 is
`
`formed, as is shown in Figure 3.).
`
`Regarding claim 9, Saito et alas modified above discloses a display device
`
`according to claim 8, wherein the opening formedin the flexible board includes an
`
`opening formed in a portion of the pattern (Figures 2-4 of Sasaki et al disclose that the
`
`hole 28a in the tape carrier 20 includes a portion of the heat dissipation pattern 25, as is
`
`shownin Figure 3.).
`
`Regarding claim 10, Saito et alas modified above discloses a display device
`
`according to claim 8, wherein the opening formedin the flexible board is formed in a
`
`portion of the flexible board where the semiconductor chip is mounted (Figure 3 and
`
`Paragraph [0072] of Sasaki et al disclose that an opening 28a is formed in the tape
`
`base 28 where the semiconductor device 10 is located.).
`
`

`

`Application/Control Number: 11/965,819
`Art Unit: 2691
`
`Page 10
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`9.
`
`Claims 5-7 and 14 are rejected under 35 U.S.C. 103(a) as being unpatentable
`
`over Saito et al (US 6,617,521) and Koya (US 6,335,862) and Reznik et al (US
`
`2006/0126317) as applied to claim 1 above, and furtherin view of Sasaki et al (US
`
`2007/0126090) and Amin et al (US 2008/01 16567).
`
`Regarding claim 5, Saito et alas modified above discloses a display device
`
`according to claim 1.
`
`Saito et alas modified abovefails to teach wherein third bumps are formed on
`
`the semiconductor chip, and the pattern and third bumps are connected with each other.
`
`Sasaki et al discloses wherein third bumps are formed on the semiconductor
`
`chip, and the pattern and third bumps are connected with each other (Figures 1-4 of
`
`sasaki et al disclose forming a third bump consisting of an electrode pattern 15 and
`
`bump 30 on the semiconductor device 10, where the third bump connects the heat
`
`dissipation pattern 25 to the semiconductor device 10. Paragraph [0078] of Sasaki et al
`
`discloses that the heat dissipation pattern 25 can be formed on either surface of the
`
`tape base 28.).
`
`Therefore it would have been obvious to one ofordinary skill in the art at the time
`
`the invention was madeto further modify the circuit board taught by Saito et a/ with the
`
`teachings of Sasaki et alin order to form a circuit board in which improved heat
`
`dissipation can be achieved from a semiconductor device with a multichannel
`
`configuration and narrowerpitches.
`
`

`

`Application/Control Number: 11/965,819
`Art Unit: 2691
`
`Page 11
`
`Saito et alas modified abovefails to teach wherein third bumps are formed on
`
`the semiconductor chip betweenthefirst bumps and the second bumps.
`
`Amin et al discloses wherein third bumps are formed on the semiconductor chip
`
`betweenthe first bumps and the second bumps(Figures 2A - 2B of Amin et al disclose
`
`having a plurality of thermal solder bumps 295 formed on the IC chip 210 betweenfirst
`
`and second bumps 250, where the thermal solder bumps 295 connect the IC chip 210
`
`to_a stiffener 240, wherethe stiffener 240 is made of a metallic material.).
`
`Therefore it would have been obvious to oneof ordinary skill in the art at the time
`
`the invention was madeto further modify the circuit substrate taught by Saito et al with
`
`the teachings of Amin et alin order to form a circuit substrate which has enhanced heat
`
`dissipation.
`
`Regarding claim 6, Saito et alas modified above discloses a display device
`
`according to claim 5, wherein a plurality of third bumpsis formed in parallel to the first
`
`long side (Figure 2A of Amin et al discloses that the plurality of thermal solder bumps
`
`295 are formed in parallel to the sides of the IC chip 210. Figure 1 of Saito et al also
`
`discloses having the dummywiring pattern 422 formed in parallel to the first long side of
`
`the IC chip 450.).
`
`Regarding claim 7, Saito et alas modified above discloses a display device
`
`according to claim 5, wherein an areaof the third bump is set larger than an area of the
`
`first bump and an area of the second bump (Figure 2A of Amin et al discloses that the
`
`

`

`Application/Control Number: 11/965,819
`Art Unit: 2691
`
`Page 12
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`area of each thermal solder bump 295is set to be larger than the areaofthe first and
`
`second bumps 250.).
`
`Regarding claim 14, Saito et alas modified above discloses a display device
`
`according to claim 5, wherein a back-surface pattern is formed on a surfaceof the
`
`flexible board opposite to a surface of the flexible board where the semiconductor chip
`
`is mounted (Figures 2A — 2B of Amin et al disclose forming a back surface pattern 240
`
`on a flexible circuit 230, where the back surface pattern 240 is formed on one side of
`
`the flexible circuit 230 and an IC chip 210 is formed on the otherside of the flexible
`
`circuit 230.),
`
`the pattern is connected to some third bumps (Figures 1
`
`- 4 of Sasaki et al
`
`disclose that the heat dissipation pattern 25, which can be formed on the upper surface
`
`of the tape base 28 of the tape carrier 20 upon which semiconductor device 10 is
`
`located, is connected to some third bumps consisting of an electrode pattern 15 and
`
`bump 30.), and
`
`the back-surface pattern is connected with some other third bumps whichdiffer
`
`from the some third bumps (Figures 2A — 2B of Amin et al disclose having the back-
`
`surface pattern 240 connected with some third bumps 295.).
`
`10.
`
`Claim 11 is rejected under 35 U.S.C. 103(a) as being unpatentable over Saito et
`
`al (US 6,617,521) and Koya (US 6,335,862) and Reznik et al (US 2006/0126317) and
`
`

`

`Application/Control Number: 11/965,819
`Art Unit: 2691
`
`Page 13
`
`Sasaki et al (US 2007/0126090) as applied to claim 8 above, and further in view of
`
`Murayama et al (US 6,184,965).
`
`Regarding claim 11, Saito et alas modified above discloses a display device
`
`according to claim 8.
`
`Saito et al as modified abovefails to teach wherein the opening formedin the
`
`flexible board is formed in a portion of the flexible board where the semiconductor chip
`
`is not mounted.
`
`Murayamaet al discloses wherein the opening formedin the flexible board is
`
`formed in a portion of the flexible board where the semiconductor chip is not mounted
`
`(Figures 8-9 of Murayama etal disclose forming an opening 3b in a region of the tape
`
`carrier package 3 containing a conductive pattern 8 for dissipating heat, where the
`
`opening 3b is formed in a portion of the tape carrier package 3 wherethe driver IC 2 is
`
`not mounted.).
`
`Therefore it would have been obvious to oneof ordinary skill in the art at the time
`
`the invention was madeto further modify the circuit substrate taught by Saito et a/ with
`
`the teachings of Murayamaetalin orderto form a circuit substrate which can more
`
`effectively dissipate heat evolved in an integrated circuit and a tape carrier package.
`
`11.
`
`Claim 13 is rejected under 35 U.S.C. 103(a) as being unpatentable over Saito et
`
`al (US 6,617,521) and Koya (US 6,335,862) and Reznik et al (US 2006/012631 7) as
`
`applied to claim 1 above, and further in view of Sasaki et al (US 2007/0126090).
`
`

`

`Application/Control Number: 11/965,819
`Art Unit: 2691
`
`Page 14
`
`Regarding claim 13, Saito et alas modified above discloses a display device
`
`according to claim 12, wherein the second pattern is formed betweenthefirst pattern
`
`and the semiconductor chip, and an insulation layer is formed betweenthe first pattern
`
`and the second pattern (Figures 1-2 of Koya disclose that the forming the second
`
`pattern 88 betweenthe first pattern 84 and the integrated circuit 81 (i.e. a
`
`semiconductor chip), where an insulating
`
`layer 82 is formed between the first
`
`pattern 84
`
`and the second pattern 88.).
`
`Saito et alas modified abovefails to teach wherein the first pattern is formed
`
`betweenthe flexible board and the semiconductor chip
`
`Sasaki et al discloses wherein the first pattern is formed betweentheflexible
`
`board and the semiconductor chip (Figures 1-4 and Paragraph [0078] of Sasaki et al
`
`disclose that the first conductive pattern (i.e. heat dissipation pattern 25) can be formed
`
`between the surface of tape base 28 and the semiconductor device 10.),
`
`Therefore it would have been obvious to oneof ordinary skill in the art at the time
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`the invention was madeto further modify the circuit board taught by Saito et a/ with the
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`teachings of Sasaki et alin order to form a circuit board in which improved heat
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`dissipation can be achieved from a semiconductor device with a multichannel
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`configuration and narrowerpitches.
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`12.
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`Claim 15 is rejected under 35 U.S.C. 103(a) as being unpatentable over Saito et
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`al (US 6,617,521) in view of Sasaki et al (US 2007/0126090) and Reznik et al (US
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`2006/0126317).
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`

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`Application/Control Number: 11/965,819
`Art Unit: 2691
`
`Page 15
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`Regarding claim 15, Saito et al discloses a display device comprising:
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`an insulation substrate (Figure 3 of Saito et al discloses having an insulation
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`substrate 200.);
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`a flexible board which is connected to the insulation substrate (Figures 1-3 of
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`Saito et al disclose attaching a flexible printed circuit board 400 to an insulation
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`substrate 200.); and
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`a semiconductor chip which is mounted on the flexible board (Figures 1-2 of
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`Saito et al disclose a semiconductor chip 450 mounted on the flexible printed circuit
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`board 400.), wherein
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`the semiconductor chip includesa first long side and a secondlong side (Figures
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`1-2 of Saito et al disclose that the semiconductor chip 450 hasa first long side anda
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`second long side.),
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`first bumps are formed on the semiconductor chip along the first long side and
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`second bumpsare formed on the semiconductor chip along the second long side
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`(Figures 1-2 of Saito et al disclose that the semiconductor chip 450 hasfirst bumps
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`450a formed along the first long side and second bumps 450b formed on the second
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`long side.).
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`Saito et al fails to teach a plurality of third bumps andaplurality of fourth bumps
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`are formed betweenthefirst bumps and the second bumps, and
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`

`

`Application/Control Number: 11/965,819
`Art Unit: 2691
`
`Page 16
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`a first pattern which is connected in commonto theplurality of third bumps and a
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`second pattern which is connected in commonto the plurality of fourth bumps are
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`formed on the flexible board.
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`Sasaki et al discloses a plurality of third bumps andaplurality of fourth bumps
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`are formed betweenthefirst bumps and the second bumps(Figures 3-4 of Sasaki et al
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`disclose forming a plurality of third bumps consisting of electrode pattern 15 and bump
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`30, and a plurality of fourth bumps consisting of electrode pattern 16 and a bump 30,
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`wherethe plurality of third and fourth bumps are located betweenthefirst bumps and
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`the second bumps.), and
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`a first pattern which is connected in commonto the plurality of third bumps and a
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`second pattern which is connected in common to the plurality of fourth bumps are
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`formed onthe flexible board (Figures 1-4 of Sasaki et al disclose having a first pattern
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`25 which is connectedto the plurality of third bumps and a second pattern 26 whichis
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`connectedto the plurality of fourth bumps which are formed on tape carrier 20 (i.e. a
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`flexible board.).).
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`Therefore it would have been obvious to oneof ordinary skill in the art at the time
`
`the invention was madeto modify the circuit board taught by Saito et a/ with the
`
`teachings of Sasaki et alin order to form a circuit board in which improved heat
`
`dissipation can be achieved from a semiconductor device with a multichannel
`
`configuration and narrowerpitches.
`
`

`

`Application/Control Number: 11/965,819
`Art Unit: 2691
`
`Page 17
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`Saito et alas modified abovefails to teach wherein the first pattern and the
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`second pattern are not electrically connected with each other, and thefirst pattern and
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`the second pattern form a capacitance, and
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`a first voltage is supplied to the first pattern and a second voltage whichis
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`different from the first voltage is supplied to the second pattern.
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`Reznik et al discloses wherein the first pattern and the second pattern are not
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`electrically connected with each other, and thefirst pattern and the second pattern form
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`a capacitance (Figures 1-2 and Paragraphs [0032] — [0038] of Reznik et al disclose
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`forming a capacitance 30 betweena first pattern 7 and a second pattern 61, where the
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`first pattern 7 and the second pattern 61 are notelectrically connected with each other.);
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`and
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`a first voltage is supplied to the first pattern and a second voltage whichis
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`different from the first voltage is supplied to the second pattern (Figures 1-2 and
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`Paragraphs [0032] — [0038] of Reznik et al disclose that the first pattern 7 is supplied
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`with an operating voltage Vcc(i.e. the first voltage), and the second pattern 61 is
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`supplied with a ground voltage GND (i.e. the second voltage.).).
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`Therefore it would have been obvious to oneof ordinary skill in the art at the time
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`the invention was madeto further modify the circuit board taught by Saito et a/ with the
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`teachings of Reznik et al such that a printed circuit board containing an Integrated
`
`Circuit has a simple and efficient way to provide low-impedance DC decoupling
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`between the ground terminal and the supply voltage terminal of the Integrated Circuit.
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`

`

`Application/Control Number: 11/965,819
`Art Unit: 2691
`
`Page 18
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`13.
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`Claims 16-18 and 20 are rejected under 35 U.S.C. 103(a) as being unpatentable
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`over Saito et al (US 6,617,521) and Sasaki et al (US 2007/0126090) and Reznik etal
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`(US 2006/0126317) as applied to claim 15 above, and further in view of Murayama etal
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`(US 6,184,965).
`
`Regarding claim 16, Saito et alas modified above discloses a display device
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`according to claim 15.
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`Saito et alas modified abovefails to teach wherein the first pattern and the
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`second pattern are formed between the semiconductor chip and the flexible board
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`Murayamaet al discloses wherein the first pattern and the second pattern are
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`formed between the semiconductor chip andthe flexible board (Figure 9 of Murayama
`
`et al discloses having a first conductive pattern 8 and a second conductive pattern 12,
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`wherean insulating protective film 11 is disposed betweenthe first conductive pattern 8
`
`and the second conductive pattern 12. Therefore, a capacitance would be formed
`
`betweenthe first conductive pattern 8 and the second conductive pattern 12.).
`
`Therefore it would have been obvious to oneof ordinary skill in the art at the time
`
`the invention was madeto further modify the circuit substrate taught by Saito et a/ with
`
`the teachings of Murayamaet alin order to form a circuit substrate which can more
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`effectively dissipate heat evolved in an integrated circuit and a tape carrier package.
`
`Regarding claim 17, Saito et alas modified above discloses a display device
`
`according to claim 15, wherein the first pattern is formed between the semiconductor
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`chip and the flexible board (Figures 1-4 and Paragraph [0078] of Sasaki et al disclose
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`

`

`Application/Control Number: 11/965,819
`Art Unit: 2691
`
`Page 19
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`that the first conductive pattern (i.e. heat dissipation pattern 25) can be formed between
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`the surface of tape base 28 and the semiconductor device 10.), and the second pattern
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`is formed betweenthe first pattern and the semiconductor chip (Figure 9 of Murayama
`
`et al discloses forming a second conductive pattern 12 betweenafirst conductive
`
`pattern 8 and a driving IC 2, where an insulating protective film 11 is formed between
`
`the first conductive pattern 8 and the second conductive pattern 12.).
`
`Regarding claim 18, Saito et alas modified above discloses a display device
`
`according to claim 15, wherein the first pattern and the second pattern form a
`
`capacitance ona portion of the flexible board where the semiconductor chip is not
`
`mounted (Figure 9 of Murayama et al discloses having a first conductive pattern 8 anda
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`second conductive pattern 12, where an insulating protective film 11 is disposed
`
`betweenthe first conductive pattern 8 and the second conductive pattern 12.
`
`Therefore, a capacitance would be formed betweenthe first conductive pattern 8 and
`
`the second conductive pattern 12, and the capacitance would be formed on a portion of
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`the tape carrier package 3 where the driver IC 2 is not mounted. ).
`
`Regarding claim 20, Saito et alas modified above discloses a display device
`
`according to claim 15, wherein the first volta