`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`www.uspto.gov
`
`APPLICATION NO.
`
`12/212,691
`
`20457
`
`
`
`
` FILING DATE
`
`
`09/18/2008
`
`7590
`
`02/28/2013
`
`FIRST NAMED INVENTOR
`
`ATTORNEY DOCKET NO.
`
`
`
`
`CONFIRMATIONNO.
`
`
`Hajime Akimoto
`
`1497.49206X00
`
`1796
`
`ANTONELLI, TERRY,STOUT & KRAUS, LLP
`1300 NORTH SEVENTEENTH STREET
`SUITE 1800
`ARLINGTON,VA 22209-3873
`
`REGN, MARK W
`
`2697
`
`MAIL DATE
`
`02/28/2013
`
`DELIVERY MODE
`
`PAPER
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`PTOL-90A (Rev. 04/07)
`
`

`

`
`Application No.
`Applicant(s)
`
`Office Action Summary
`
`12/212,691
`Examiner
`MARK REGN
`
`AKIMOTO ETAL.
`Art Unit
`2697
`
`-- The MAILING DATEof this communication appears on the cover sheet with the correspondence address--
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLYIS SET TO EXPIRE 3 MONTH(S) OR THIRTY(30) DAYS,
`WHICHEVER IS LONGER, FROM THE MAILING DATE OF THIS COMMUNICATION.
`Extensions of time may be available underthe provisions of 37 CFR 1.136(a).
`In no event, however, may a reply be timely filed
`after SIX (6) MONTHS from the mailing date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Anyreply received by the Office later than three months after the mailing date of this communication, evenif timely filed, may reduce any
`earned patent term adjustment. See 37 CFR 1.704(b).
`
`Status
`
`1)X] Responsive to communication(s)filed on 14 May 2012.
`2a)L] This action is FINAL.
`2b)X] This action is non-final.
`3)L] An election was made bythe applicant in response to a restriction requirement set forth during the interview on
`
`; the restriction requirement and election have been incorporated into this action.
`4)_] Sincethis application is in condition for allowance exceptfor formal matters, prosecution as to the merits is
`closed in accordance with the practice under Ex parte Quayle, 1935 C.D. 11, 453 O.G. 213.
`
`Disposition of Claims
`
`5)X] Claim(s) 1,2 and 6-14 is/are pending in the application.
`
`5a) Of the above claim(s)
`is/are withdrawn from consideration.
`
`6)L] Claim(s)
`is/are allowed.
`7)X] Claim(s) 1,2 and 6-14 is/are rejected.
`8)L] Claim(s) ___is/are objectedto.
`
`9)L] Claim(s)
`are subject to restriction and/or election requirement.
`
`* If any claims have been determined allowable, you maybeeligible to benefit from the Patent Prosecution Highway
`program at a participating intellectual property office for the corresponding application. For more information, please see
`htto//Awww.uspto.gov/patenis/init events/ooh/index.jiso or send an inquiry to PPHieedback@usopio.qov.
`
`Application Papers
`
`10)L] The specification is objected to by the Examiner.
`
`11) The drawing(s) filed on
`is/are: a)[_] accepted or b)[_] objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121(d).
`
`Priority under 35 U.S.C. § 119
`
`12)[] Acknowledgmentis made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
`a)L] All
`)LJ Some * c)L] None of:
`1..] Certified copies of the priority documents have been received.
`2.L] Certified copies of the priority documents have been received in Application No.
`3.L] Copiesof the certified copies of the priority documents have been receivedin this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`* See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`1) C] Notice of References Cited (PTO-892)
`
`2) Xx] Information Disclosure Statement(s) (PTO/SB/08)
`Paper No(s)/Mail Date
`U.S. Patent and Trademark Office
`
`3) CT] Interview Summary (PTO-413)
`Paper No(s)/Mail Date.
`4) | Other:
`
`PTOL-326 (Rev. 09-12)
`
`Office Action Summary
`
`Part of Paper No./Mail Date 20130201
`
`
`
`

`

`Application/Control Number: 12/212,691
`Art Unit: 2697
`
`Page 2
`
`DETAILED ACTION
`
`Continued Examination Under 37 CFR 1.114
`
`A requestfor continued examination under 37 CFR 1.114, including the fee set
`
`forth in 37 CFR 1.17(e), wasfiled in this application after final rejection. Since this
`
`application is eligible for continued examination under 37 CFR 1.114, and the fee set
`
`forth in 37 CFR 1.17(e) has beentimely paid, the finality of the previous Office action
`
`has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 14,
`
`2012 has been entered.
`
`Information Disclosure Statement
`
`The information disclosure statement (IDS) submitted on January 3, 2013 is
`
`hereby acknowledged. All references have been considered by the examiner.
`
`Initialed
`
`copies of the PTO-1449 are includedin this correspondence.
`
`Claim Rejections - 35 USC § 102
`
`The following is a quotation of the appropriate paragraphsof 35 U.S.C. 102 that
`
`form the basis for the rejections underthis section madein this Office action:
`
`A person shall be entitled to a patent unless —
`
`

`

`Application/Control Number: 12/212,691
`Art Unit: 2697
`
`Page 3
`
`(6) the invention was patented or described in a printed publication in this or a foreign country or
`in public use or on sale in this country, more than one yearprior to the date of application for
`patent in the United States.
`
`Claim 6 is rejected under 35 U.S.C. 102(b) as being anticipate by Marx (WO
`
`2005/109389; supplied with applicant’s IDS).
`
`1.
`
`With regard to claim 6, Marx discloses an image display device (Fig. 12),
`
`comprising:
`
`plural pixels (Fig. 12, #101) each including a current-drive type light emitting
`
`element (Figs. 1-10, #8);
`
`plural signal lines (Fig. 12, #’s S_n through S_n+2) inputting image voltage to
`
`respective pixels (Figs. 4-10, #S);
`
`a signalline drive circuit supplying image voltage to the plural signallines (Fig.
`
`13); and
`
`a pixel selection circuit for selecting pixels into which the image voltage is written
`
`through the plural signal lines from the plural pixels (Fig. 12, #102),
`
`wherein each pixel includes a drive transistor, a first electrode of which is
`
`connected to a powersourceline (Figs. 1-10, #4), a capacitor element connected
`
`betweena gate electrode of the drive transistor and a corresponding signalline of the
`
`plural signal lines (Figs. 2-10, #6),
`
`wherein one frameperiod includes a writing period in which the scanning lines
`
`are selected sequentially for writing the image voltage to respective pixels (Claim 12,
`
`“... a first operating mode ... includes ... closing the first switching means (10) at the
`
`

`

`Application/Control Number: 12/212,691
`Art Unit: 2697
`
`Page 4
`
`beginning of a cycle; applying a control signal ... to the current control means (4) via the
`
`control line (S), the control signal corresponding to a desired luminous flux ...”), a light
`
`emitting period for driving the light emitting elements (Claim 3, “... a signal holding
`
`means (6) is connected to the control electrode of the current control means (4) in such
`
`a mannerthat the control signal is heldif the first switching means (10) interrupts the
`
`connection betweenthe control line (S) and the control electrode of the control means
`
`(4)”) and a detection period (Claim 15, “... a second operating mode, electrical
`
`parametersof the light-emitting means (8) being measured ...”) in which the detection
`
`gate lines are selected (Claim 15, “... closing the second switching means (12),
`
`connecting the control line (S) to means for measuring the voltage ...”), sequentially
`
`(Claim 19, “... the lines or columns are actuated sequentially”);
`
`wherein the capacitor of each pixel is written with the image voltage during the
`
`writing period (Claim 3, “... a signal holding means (6) is connected to the control
`
`electrode of the current control means (4) in such a mannerthat the control signalis
`
`heldif the first switching means (10) interrupts the connection betweenthe control line
`
`(s) and the control electrode of the control means (4)”),
`
`wherein the light emitting element of each pixel emits light during the light
`
`emitting period (page 2, L19-24, “... a signal holding means 6 has been added to the
`
`circuit ... This makes it possible to extend the active period of time during which the
`
`light-emitting element 8 radiates light”),
`
`wherein the signalline drive circuit includes an image voltage generating circuit
`
`for generating the image voltage (Fig. 13, #201), a detection circuit (Fig. 13, #209 &
`
`

`

`Application/Control Number: 12/212,691
`Art Unit: 2697
`
`Page 5
`
`page 12, L32-39) and a switching circuit A connected to one end of eachsignalline
`
`(Fig. 13, #’s 207 & 208),
`
`wherein the switching circuit A supplies an image signal outputted from the
`
`image voltage generating circuit to each signal line during the writing period (Fig. 13 &
`
`page 12, L 22-31, “Control lines ... are connected to means for measuring the current
`
`and for applying a control signal 201 ... In the first operating mode a data value is
`
`converted to a voltage value by means of a digital/analog converter 206 ... and is
`
`supplied to the control lines via the operational amplifiers 202 and the current-limiting
`
`means 203”) and inputs a voltage betweenterminals of the light emitting element to the
`
`detection circuit during the detection period (Fig. 10, #18; page 11, L10-11, “The control
`
`line S is connected to a means 18 for measuring electrical voltages”; Fig. 13 & page 12,
`
`L32-39, “In another operating mode, it is possible to measure the current through the
`
`control lines S_n... If only the switching means 208 is closed and one input of the
`
`analog/digital converter is connected to a reference potential
`
`it is possible to measure
`
`the voltage of the controlline”).
`
`Claim Rejections - 35 USC § 103
`
`The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all
`
`obviousnessrejections setforth in this Office action:
`
`(a) A patent may not be obtained though the invention is not identically disclosed or described as
`set forth in section 102 of this title, if the differences between the subject matter sought to be
`patented and the prior art are such that the subject matter as a whole would have been obvious
`at the time the invention was made to a person having ordinary skill in the art to which said
`
`

`

`Application/Control Number: 12/212,691
`Art Unit: 2697
`
`Page 6
`
`subject matter pertains. Patentability shall not be negatived by the manner in which the invention
`was made.
`
`Claim 14 is rejected under 35 U.S.C. 103(a) as being unpatentable over Marx.
`
`2.
`
`With regard to claim 14, Marx discloses almost the entire period of one frame
`
`period is allocated to the writing period and the light emitting period (page 2, L23-25).
`
`Marx doesnotspecifically disclose seventy percent of one frame periodis allocated to
`
`the writing period and the light emitting period and wherein thirty percent of the one
`
`frame period is allocated to the detection period. Since Marx discloses the general
`
`condition that most of the period has light emitting and since there is no evidenceof
`
`criticality of the 70% / 30%time breakdownof as claimed, it would have been obvious to
`
`one of ordinary skill in the art at the time of the invention for seventy percent of one
`
`period to be allocated to the writing period and the light emitting period and thirty
`
`percentof the one frame period to be allocated to the detection period ("Optimization of
`
`Ranges", MPEP 2144.05(II)A).
`
`Claims 1, 2 and 13 are rejected under 35 U.S.C. 103(a) as being unpatentable
`
`over Marx in view of Akimoto (2005/01 10720).
`
`3.
`
`With regard to claim 1, Marx discloses an image display device (Fig. 12),
`
`comprising:
`
`

`

`Application/Control Number: 12/212,691
`Art Unit: 2697
`
`Page 7
`
`plural pixels (Fig. 12, #101) each including a current-drive type light emitting
`
`element (Figs. 1-10, #8);
`
`plural signal lines (Fig. 13, #'s s_n through s_n+2) inputting image voltage to
`
`respective pixels (Figs. 4-10, #S); and
`
`a pixel selection circuit for selecting pixels into which the image voltage is written
`
`through the plural signal lines from the plural pixels (Fig. 12, #102),
`
`wherein each pixel includes a drive transistor, a first electrode of which is
`
`connected to a powersourceline (Figs. 1-10, #4), a capacitor element connected
`
`betweena gate electrode of the drive transistor and a corresponding signalline of the
`
`plural signal lines (Figs. 2-10, #6),
`
`wherein the pixel selection circuit includes plural scanning lines (Fig. 6, #Z) and
`
`plural detection gate lines (Fig. 6, #MZ),
`
`wherein one frame period includes a writing period in which the scanning lines
`
`are selected sequentially for writing the image voltage to respective pixels (Claim 12,
`
`“... a first operating mode ... includes ... closing the first switching means (10) at the
`
`beginning of a cycle; applying a control signal ... to the current control means (4) via the
`
`control line (S), the control signal corresponding to a desired luminous flux ...”), a light
`
`emitting period for driving the light emitting elements (Claim 3, “... a signal holding
`
`means (6) is connected to the control electrode of the current control means (4) in such
`
`a mannerthat the control signalis heldif the first switching means (10) interrupts the
`
`connection betweenthe control line (s) and the control electrode of the control means
`
`(4)”) and a detection period (Claim 15, “... a second operating mode, electrical
`
`

`

`Application/Control Number: 12/212,691
`Art Unit: 2697
`
`Page 8
`
`parametersof the light-emitting means (8) being measured ...”) in which the detection
`
`gate lines are selected (Claim 15, “... closing the second switching means (12),
`
`connecting the control line (S) to means for measuring the voltage ...”), sequentially
`
`(Claim 19, “... the lines or columns are actuated sequentially”);
`
`wherein the capacitor of each pixel is written with the image voltage during the
`
`writing period (Claim 3, “... a signal holding means (6) is connected to the control
`
`electrode of the current control means (4) in such a mannerthat the control signal is
`
`heldif the first switching means (10) interrupts the connection betweenthe control line
`
`(s) and the control electrode of the control means (4)”),
`
`wherein the light emitting element of each pixel emits light during the light
`
`emitting period (page 2, L19-24, “... a signal holding means 6 has been added to the
`
`circuit ... This makes it possible to extend the active period of time during which the
`
`light-emitting element 8 radiateslight”),
`
`wherein the pixel selection circuit sequentially selects pixels (Claim 19, “... the
`
`lines or columns are actuated sequentially”) in which voltage between terminals of the
`
`light emitting elementis detected from the plural pixels during the detection period
`
`(Claim 15, “... in a second operating mode ... connecting the control line (S) to means
`
`for measuring the voltage” & page 8 line 39 through page 9 line 3 “... a second
`
`switching means 12 is used to switchably connect a common connection of the current
`
`control means 4 andofthe light-emitting means 8 to the control line S. The control line
`
`S can furthermore be connected to means(not shownin the figure) for measuring
`
`voltages ...”), and
`
`

`

`Application/Control Number: 12/212,691
`Art Unit: 2697
`
`Page 9
`
`wherein each of the signal lines is also configured to be used as a detection line
`
`detecting voltage between terminals of a corresponding one ofthe light emitting
`
`elements (page 12, lines 22-24, "Figure 13 schematically shows part of an exemplary
`
`column-driver. Control lines S_n, S_n+1 and S_n+2 are connected to means for
`
`measuring the current and for applying control signal 201” & page 12, lines 37-39, "If
`
`only the switching means 208 is closed and one inputof the analog/digital converteris
`
`connected to a reference potential, it is possible to measure the voltage of the control
`
`line").
`
`Marx does not specifically disclose the pixel selection circuit includes plural
`
`lighting control lines. Akimoto discloses the pixel selection circuit includes plurallighting
`
`control lines (Fig. 1, #9; [0043]). Since Marx and the current application both disclose
`
`image display device controls (base device) and since Akimoto also discloses image
`
`display device controls (comparable device) improved in the same wayasthe current
`
`application discloses, that is by including plural lighting control lines in the pixel
`
`selection circuit, it would have been obvious to oneof ordinary skill in the art at the time
`
`of the invention to use Akimoto’s known technique of including plural lighting control
`
`lines in the pixel selection circuit in Marx. Since no change in Marx's or Akimoto’s
`
`elements would be expected, the combination would yield predictable results (“Use of
`
`Known Technique”, KSR, 550 U.S. 398).
`
`4.
`
`With regard to claim 2, Marx discloses each pixel includes the drive transistor ,
`
`the first electrode of which is connected to the power sourceline (Figs. 1-10, #4), a
`
`

`

`Application/Control Number: 12/212,691
`Art Unit: 2697
`
`Page 10
`
`switching transistor connected betweenthe gate electrode and a secondelectrode of
`
`the drive transistor (Fig. 6, #10), the capacitor element connected between the gate
`
`electrode of the drive transistor and the powersourceline in the plural signal lines (Figs.
`
`2-10, #6), and a detection transistor a first electrode of which is connected to one end of
`
`the light emitting element and a second electrode of which is connected to the
`
`corresponding signalline in the signal lines (Fig. 6, #12),
`
`wherein the other end ofthe light emitting element of each pixel is connected to a
`
`reference potential (Figs. 1-10, #8; & page 2, L1-2, “A current means 4 is connected to
`
`in series with a light-emitting element 8 between an operating voltage VDD and
`
`ground”),
`
`wherein a gate electrode of the switching transistor is connected to a
`
`corresponding scanning line in the plural scanning lines (Fig. 6, #Z), and
`
`wherein a gate electrode of the detection transistor is connected to a
`
`corresponding detection gate line in the plural detection gate lines (Fig. 6, #MZ).
`
`Marx discloses the capacitor element is connected between the gate electrode of
`
`the drive transistor and the power supply. Marx does not specifically disclose the
`
`capacitor element is connected betweenthe gate electrodeof the drive transistor and
`
`the corresponding signalline. Marx also does not disclose a lighting transistor a
`
`second electrode of which is connected to the secondelectrode of the drive transistor
`
`and a first electrode of which is connected to one endofthe light emitting element
`
`wherein a gate electrode of the lighting transistor is connected to a corresponding
`
`lighting control line in the plural lighting control lines. Akimoto discloses the capacitor
`
`

`

`Application/Control Number: 12/212,691
`Art Unit: 2697
`
`Page 11
`
`elementis connected betweenthe gate electrode of the drive transistor and the
`
`corresponding signalline (Fig. 6, #50), a lighting transistor a second electrode of which
`
`is connected to the second electrode of the drive transistor andafirst electrode of
`
`which is connected to one end of the light emitting element (Fig. 1, #15) wherein a gate
`
`electrodeofthe lighting transistor is connected to a corresponding lighting control line
`
`in the plural lighting control lines (Fig. 1, #9). See above for the rational to support a
`
`conclusion of obviousness to combine Akimoto with Marx.
`
`5.
`
`With regard to claim 13, Marx discloses almost the entire period of one frame
`
`period is allocated to the writing period and the light emitting period (page 2, L23-25).
`
`Marx doesnotspecifically disclose seventy percent of one frame periodis allocated to
`
`the writing period and the light emitting period and wherein thirty percent of the one
`
`frame period is allocated to the detection period. Since Marx discloses the general
`
`condition that most of the period haslight emitting and since there is no evidence of
`
`criticality of the 70% / 30%time breakdownasclaimed, it would have been obvious to
`
`one of ordinary skill in the art at the time of the invention for seventy percent of one
`
`period to be allocated to the writing period and the light emitting period and thirty
`
`percentof the one frame period to be allocated to the detection period ("Optimization of
`
`Ranges", MPEP 2144.05(II)A).
`
`

`

`Application/Control Number: 12/212,691
`Art Unit: 2697
`
`Page 12
`
`Claims 7 - 10 are rejected under 35 U.S.C. 103(a) as being unpatentable over
`
`the combination of Marx and Akimoto in view of Chung (2007/0024544).
`
`6.
`
`With regard to claim 7, Marx does not specifically disclose a switching circuit B
`
`connected betweenthe switching circuit A and one end of each signal line, wherein the
`
`switching circuit B connects one endof eachsignalline to the switching circuit A during
`
`the writing period and the detection period and connects one endof eachsignalline to a
`
`ramp-wavevoltage inputline to which ramp-waveform voltage in which the voltage level
`
`varies with time is supplied during the light emitting period continued from the writing
`
`period. Akimoto discloses the voltage generating circuit inputting a ramp-waveform
`
`voltage to one end of the signal lines in which the voltage level varies with time is
`
`supplied during the light emitting period continued from the writing period (Fig. 8,
`
`[0062]). See abovefor the rational to support a conclusion of obviousness to combine
`
`Akimoto with Marx. The combination of Marx and Akimoto doesnotspecifically disclose
`
`a switching circuit B connected between the switching circuit A and one end of the
`
`signal line, wherein the switching circuit B connects one endof each signalline to the
`
`switching circuit A during the writing period and the detection period and connects one
`
`end of eachsignalline to the voltage generating circuit.
`
`Chung discloses a switching circuit B (Fig. 8, #M11j) wherein the switching circuit
`
`B connects one end of eachsignalline during the writing period and the detection
`
`period to the voltage generator during the light emitting period continued from the
`
`writing period. Since the combination of Marx and Akimoto as well as the current
`
`

`

`Application/Control Number: 12/212,691
`Art Unit: 2697
`
`Page 13
`
`application disclose image display device controls (base device) and since Chung also
`
`discloses image display device controls (comparable device) improved in the same way
`
`as the current application discloses, that is by configuring switching circuits per above, it
`
`would have been obvious to one ofordinary skill in the art at the time of the invention to
`
`use Chung’s knowntechnique of configuring switching circuits per above in the
`
`combination of Marx and Akimoto. Since no change in Marx’s Akimoto’s or Chung’s
`
`elements would be expected, the combination would yield predictable results (“Use of
`
`Known Technique”, KSR, 550 U.S. 398).
`
`7.
`
`With regard to claim 8, Marx doesnotdisclose the detection circuit includes
`
`plural constant power sources supplying constant current to respective signal lines and
`
`a voltage detection circuit provided by each signalline, detecting a voltage value
`
`generated at one end of each signal line when constant current is supplied to each
`
`signal line from each constant current source. Akimoto discloses the detection circuit
`
`includes plural constant power sources supplying constant current (Fig. 5, #8) anda
`
`voltage detection circuit provided by each signalline (Fig. 5, #7 & Fig. 3), detecting a
`
`voltage value generated at one endof eachsignal line when constant currentis
`
`supplied to each signalline from each constant current source [0041]. See abovefor
`
`the rational to support a conclusion of obviousness to combine Akimoto with Marx. The
`
`combination of Marx and Akimoto does notdisclose the constant current is supplied to
`
`respective signallines.
`
`

`

`Application/Control Number: 12/212,691
`Art Unit: 2697
`
`Page 14
`
`Chung discloses the constant current is supplied to respective signal lines
`
`([(0019], “... a current sink receiving a predetermined current from the pixel via the data
`
`line ...”). See above for the rational to support a conclusion of obviousness to combine
`
`Chung with the combination of Marx and Akimoto.
`
`8.
`
`With regard to claim 9, Marx does not specifically disclose the voltage
`
`detection circuit includes an A/D converter converting a detected voltage value into a
`
`digital value, and wherein the image voltage generating circuit corrects normal image
`
`data inputted from the outside based on the digital value outputted from the A/D
`
`converter. Akimoto discloses the voltage detection circuit includes an A/D converter
`
`converting a detected voltage into a digital value [0041] and wherein the image voltage
`
`generating circuit corrects normal image data inputted from the outside based on the
`
`digital value outputted from the A/D converter ([0046], “... The graphic control circuit 34
`
`acquires a degree of change in the organic EL light emitting element 13 in each pixel on
`
`the basis of the information stored in the correction data memory 37in this manner, an
`
`usesits result as a coefficient to generate new correction data based on conversion
`
`information ...”). See abovefor the rational to support a conclusion of obviousnessto
`
`combine Akimoto with Marx.
`
`9.
`
`With regard to claim 10, Marx does not specifically disclose the pixel selection
`
`circuit includes plural scanning lines, plural lighting control lines and plural detection
`
`gate lines, wherein eachpixel includes the drive transistor, the first electrode of which is
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`Application/Control Number: 12/212,691
`Art Unit: 2697
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`Page 15
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`connected to the power sourceline, a switching transistor connected between the gate
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`electrode and a second electrode of the drive transistor, the capacitor element
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`connected betweenthe gate electrode of the drive transistor and the corresponding
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`signalline in the plural signal lines, a lighting transistor a second electrode of which is
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`connected to the second electrode of the drive transistor andafirst electrode of which is
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`connected to one endof the light emitting element and a detection transistor a first
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`electrode of which is connected to one endofthe light emitting element and a second
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`electrode of which is connected to Jthe corresponding signalline in the signallines,
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`wherein the other endofthe light emitting element of each pixel is connected to a
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`reference potential, wherein a gate electrode of the switching transistor is connected to
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`a corresponding scanningline in the plural scanning lines, wherein a gate electrode of
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`the lighting transistor is connected to a corresponding lighting control line in the plural
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`lighting control lines and wherein a gate electrode of the detection transistoris
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`connected to a corresponding detection gate line in the plural detection gate lines.
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`Akimoto discloses the pixel selection circuit includes plural scanning lines (Fig. 1,
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`#3) and plurallighting control lines (Fig. 5, #9), wherein each pixel includes the drive
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`transistor, the first electrode of which is connected to the powersourceline (Fig. 6,
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`#12), a switching transistor connected between the gate electrode and a second
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`electrode of the drive transistor (Fig. 6, #51), the capacitor element connected between
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`the gate electrode of the drive transistor and the corresponding signalline in the plural
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`signallines (Fig. 6, #50), a lighting transistor a second electrode of which is connected
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`to the second electrode of the drive transistor andafirst electrode of which is connected
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`Application/Control Number: 12/212,691
`Art Unit: 2697
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`Page 16
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`to one endofthe light emitting element (Fig. 6, #15A) wherein the other end of the light
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`emitting element of each pixel is connected to a reference potential (Fig. 6, #14),
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`wherein a gate electrode of the switching transistor is connected to a corresponding
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`scanning line in the plural scanning lines (Fig. 6, #53), wherein a gate electrode of the
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`lighting transistor is connected to a corresponding lighting control line in the plural
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`lighting control lines (Fig. 6, #9). See abovefor the rational to support a conclusion of
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`obviousness to combine Akimoto with Marx.
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`The combination of Marx and Akimoto doesnot disclose the pixel selection circuit
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`includes plural detection gate lines, and a detection transistor a first electrode of which
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`is connected to one end ofthe light emitting element and a secondelectrode of whichis
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`connected to the corresponding signalline in the signal lines, wherein a gate electrode
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`of the detection transistor is connected to a corresponding detection gateline in the
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`plural detection gate lines.
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`Chungdiscloses the pixel selection circuit includes plural detection gate lines
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`(Fig. 2, #Sn), and a detection transistor a first electrode of which is connected to one
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`end of the light emitting element and a second electrode of which is connected to the
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`corresponding signalline in the signal lines (Fig 3, #M2nm), wherein a gate electrodeof
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`the detection transistor is connected to a corresponding detection gateline in the plural
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`detection gate lines (Fig. 3, #Sn). See abovefor the rational to support a conclusion of
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`obviousness to combine Chung with Marx and Akimoto.
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`Application/Control Number: 12/212,691
`Art Unit: 2697
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`Page 17
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`Claims 11 and 12 are rejected under 35 U.S.C. 103(a) as being unpatentable
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`over the combination of Marx, Akimoto and Chung in view of Akimoto (6,950,081)
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`hereinafter referred to as Akimoto 081.
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`10. With regard to claim 11, the combination of Marx and Akimoto does not
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`specifically disclose each lighting transistor is turned on during a first period and a
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`second period when lighting voltage is supplied to a corresponding lighting control line
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`in the plural lighting control lines and is turned off during periods other than the above
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`periods in the writing period, wherein each switching transistor is turned on during the
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`second period anda third period when reset voltage is supplied to a corresponding
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`scanning line in the plural scanning lines and is turned off during periods other than the
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`aboveperiodsin the writing period, wherein each detection transistor is turned off
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`during the writing period, wherein each lighting transistor is turned on during the light
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`emitting period continued from the writing period, wherein each switching transistor is
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`turned off during the light emitting period, wherein each detection transistor is turned off
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`during the light emitting period, wherein eachlighting transistor is turned off during the
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`detection period, wherein each switching transistor is turned off during the detection
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`period, wherein each detection transistor is turned on during a period when detection
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`voltage is supplied to a corresponding detection gate line in the plural detection gate
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`lines and is turned off during periods other than the aboveperiod in the detection
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`period.
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`Application/Control Number: 12/212,691
`Art Unit: 2697
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`Page 18
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`Chung discloses each switching transistor is turned on during the second period
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`anda third period when reset voltage is supplied to a corresponding scanning line in the
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`plural scanning lines andis turned off during periods other than the above periods in the
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`writing period ((0067], “The fifth transistor M5Snm may beturned on ... so that current
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`flows through the fourth transistor M4nm.”), wherein each detection transistor is turned
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`off during the writing period [0084], wherein each detection transistor is turned off during
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`the light emitting period (Fig. 8, M12) being a detection transistor {[0111] M12j ... may
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`be turnedoff during the second period, where the second period corresponds to the
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`light emitting period [0077]}), wherein each lighting transistor is turned on during a light
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`emitting period continued from the writing period ([0139], “As shownin Fig. 10 ... via the
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`sixth transistor M6nj.”), wherein eachlighting transistor is turned off during a detection
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`period ([0069] “The sixth transistor may be turned off ...”), and wherein each detection
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`transistor is turned on during a period when detection voltage is supplied to a
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`corresponding detection gate line ([0110], “The twelfth and thirteenth transistors ... may
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`be controlled by a second control signal CS2”) in the plural detection gate lines and is
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`turned off during periods other than the abovepe