`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria1 Virginia 22313- 1450
`www.uspto.gov
`
`APPLICATION NO.
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`
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`
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` F ING DATE
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`FIRST NAMED INVENTOR
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`ATTORNEY DOCKET NO.
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`
`
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`CONF {MATION NO.
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`12/588,205
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`10/07/2009
`
`Hajime Akimoto
`
`HITA—1279
`
`5092
`
`7590
`03’2”“
`9999c99199 AMq —
`c/o Stites & Harbison PLLC
`SOTO LOPEZ, JOSE R
`1199 North Fairfax Street
`9 999
`Alexandria, VA 223 14- 1437
`
`NM
`
`2694
`
`
`
`
`NOT *ICATION DATE
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`DELIVERY MODE
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`03/29/2013
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`ELECTRONIC
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`Please find below and/0r attached an Office communication concerning this application or proceeding.
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`The time period for reply, if any, is set in the attached communication.
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`Notice of the Office communication was sent electronically on above—indicated "Notification Date" to the
`following e—mail address(es):
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`iplaw @ stites.com
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`PTOL—90A (Rev. 04/07)
`
`

`

`
`
`Office Action Summary
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`Application No.
`
`Applicant(s)
`
`
` 12/588,205 AKIMOTO ET AL.
`Examiner
`Art Unit
`JOSE SOTO LOPEZ
`2694
`
`-- The MAILING DA TE of this communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE 3 MONTH(S) OR THIRTY (30) DAYS,
`WHICHEVER IS LONGER, FROM THE MAILING DATE OF THIS COMMUNICATION.
`Extensions of time may be available under the provisions of 37 CFR1. 136(a).
`In no event however may a reply be timely filed
`after SIX () MONTHS from the mailing date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any
`earned patent term adjustment. See 37 CFR 1.704(b).
`
`Status
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`1)|Zl Responsive to communication(s) filed on 20 August 2012.
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`2a)|:l This action is FINAL.
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`2b)IXI This action is non-final.
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`3)I:I An election was made by the applicant in response to a restriction requirement set forth during the interview on
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`; the restriction requirement and election have been incorporated into this action.
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`4)|:l Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
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`closed in accordance with the practice under Exparte Quay/e, 1935 CD. 11, 453 O.G. 213.
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`Disposition of Claims
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`5)IZ Claim(s) L6 is/are pending in the application.
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`5a) Of the above claim(s) _ is/are withdrawn from consideration.
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`6)|:| Claim(s) _ is/are allowed.
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`7)|Xl Claim(s) 1_-6is/are rejected.
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`8)|:| Claim(s) _ is/are objected to.
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`9)I:I Claim((s)
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`are subject to restriction and/or election requirement.
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`* If any claims have been determined allowable, you may be eligible to benefit from the Patent Prosecution Highway
`program at a participating intellectual property office for the corresponding application. For more information, please see
`
`httn:,I/www usntq. quwua'ertslanr events/
`h/Indexis or send an inquiry to PPeredback us Emmi.
`
`Application Papers
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`10)I:| The specification is objected to by the Examiner.
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`11)|Xl The drawing(s) filed on 01/07/2009 and 12/02/2009 is/are: a)IXI accepted or b)I:I objected to by the Examiner.
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`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
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`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
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`Priority under 35 U.S.C. § 119
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`12)|X| Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
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`a)lZl All
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`b)|:l Some * c)I:I None of:
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`1.IXI Certified copies of the priority documents have been received.
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`2.|:l Certified copies of the priority documents have been received in Application No. _
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`3.I:I Copies of the certified copies of the priority documents have been received in this National Stage
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`application from the International Bureau (PCT Rule 17.2(a)).
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`* See the attached detailed Office action for a list of the certified copies not received.
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`
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`Attachment(s)
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`1) IZI Notice of References Cited (PTO-892)
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`2) D Information Disclosure Statement(s) (PTO/SB/08)
`Paper No(s)/Mai| Date
`US. Patent and Trademark Office
`PTOL-326 (Rev. 09-12)
`
`3) I] Interview Summary (PTO-413)
`Paper No(s)/Mai| Date.
`4) D Other:
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`Office Action Summary
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`Part of Paper No./Mai| Date 20130320
`
`

`

`Application/Control Number: 12/588,205
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`Page 2
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`Art Unit: 2694
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`DETAILED ACTION
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`Response to Arguments
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`1.
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`Applicant's arguments filed 08/20/2012 have been fully considered but they are
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`not persuasive.
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`As per claim 1, Applicant argues as follows:
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`“Applicants respectfully correct an interpretation of the Akimoto device as
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`summarized in the Office Action. In the rejection, the Examiner alleges that "during the
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`'write period' (being the first half of one frame), the gate drives circuit 82 sequential/y
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`scans each of the pixel rows " (Akimoto, column 11 , lines 35-40). Based on this excerpt
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`from Akimoto, the Examiner alleges that the Akimoto supply voltage is inherently
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`supplied to the pixels in a sequential manner. (Office Action, page 3, last paragraph).
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`However, contrary to" the Examiner's assertion, Akimoto does not disclose a supply
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`voltage being inherently, supplied to the pixels in a sequential manner. Applicants
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`respectfully correct the Examiner's interpretation of Akimoto, column 11 , lines 35- 40, in
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`that this excerpt refers to the claimed "disp/ay signal voltage " and not to the claimed
`H H
`"supply voltage .
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`Examiner respectfully disagrees and submits that Akimoto teaches wherein the
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`supply voltage is applied sequentially. Fig. 1 of Akimoto illustrates that the supply
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`

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`Application/Control Number: 12/588,205
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`Page 3
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`Art Unit: 2694
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`voltage applied to the electroluminescent element changes according to the sequential
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`operation of transistor 9. The voltage supplied to the electroluminescent element 7
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`changes when transistor 9 is activated.
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`Claim Rejections - 35 USC § 103
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`2.
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`The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all
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`obviousness rejections set forth in this Office action:
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`(a) A patent may not be obtained through the invention is not identically disclosed or described as set
`forth in section 102 of this title, if the differences between the subject matter sought to be patented and
`the prior art are such that the subject matter as a whole would have been obvious at the time the
`invention was made to a person having ordinary skill in the art to which said subject matter pertains.
`Patentability shall not be negatived by the manner in which the invention was made.
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`3.
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`Claims 1-6 are rejected under 35 U.S.C. 103(a) as being unpatentable over
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`Akimoto et al., US 6,950,081; in view of Libsch et al., US 7,167,169; in further view
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`of Shirasaki et al., US 2004/0113873.
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`With respect to claim 1, Akimoto discloses, an image display device (fig. 1, for
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`example) comprising:
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`a first pixel (fig. 7; analogous to top left pixel in fig. 1) comprising a first electro-
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`luminescent element (7) driven to illuminate according to a first display signal voltage
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`(signal applied to 17), a first driving TFT whose first current terminal is connected to a
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`first terminal of the first electro-luminescent element (63), and a first storage capacitor
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`whose first terminal is connected to a gate terminal of the first driving TFT (2);
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`Application/Control Number: 12/588,205
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`Page 4
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`Art Unit: 2694
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`a second pixel comprising a second electro-luminescent element driven to
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`illuminate according to a second display voltage, a second driving TFT whose current
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`terminal is connected to a first terminal of the second electro-luminescent element, and
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`a second storage capacitor whose first terminal is connected to a gate of the second
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`driving TFT (second pixel is top right pixel in fig. 1, for example);
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`a first power supply line (line between 65 and 63 in fig. 7) supplying a supply
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`voltage to the first electro-luminescent element via a channel of the first driving TFT (fig.
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`7); and
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`supplying a supply voltage to the first electro-luminescent element via a channel
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`of the first driving TFT flsupplying the supply We to the second electro-
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`luminescent element via a channel of the second driving TFT seguentially (column 11,
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`lines 35-40, “During the "write period" (being the first half of one frame), the gate drive
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`circuit 82 sequentially scans each of the pixel rows”, based on this operation, the
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`supply voltage is inherently supplied to the pixels in a sequential manner);
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`Akimoto does not expressly disclose, a first power supply line supplying a supply
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`voltage according to scanning the first power supply line by a power supply line
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`scanning circuit.
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`Libsch discloses, a first power supply line (Power Driver Line A in fig. 3)
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`supplying a supply voltage according to scanning the first power supply line by a power
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`supply line scanning circuit (Libsch et al., Fig. 3, refer to power driver line A and power
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`driver line B, see also Fig. 4 and column 7, lines 10-20, “V(1)-1, V(1)-2,.
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`.. V(1)-N
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`

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`Application/Control Number: 12/588,205
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`Page 5
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`Art Unit: 2694
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`represent line waveforms analogous to Vsupply 425 for row 1, 2, .
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`.
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`. N, respectively,
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`for OLED array 410.”)
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`Libsch and Akimoto are analogous art because they are from the same field of
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`invention EL control circuitry.
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`At the time of the invention it would have been obvious to one of ordinary skill in
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`the art to substitute the power supply lines of Akimoto et al. with power supply lines
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`supplying a supply voltage according to scanning the power supply lines by a power
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`supply line scanning circuit, such as taught by Libsch, for the purpose of illuminating the
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`OLED using a duty cycle of less than 100% (Libsch et al., column 5, lines 10-20).
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`Akimoto et al. as modified by Libsch do not explicitly teach wherein the power
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`supply line scanning circuit seguentially turns on and off a first power supply, line switch
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`which connects the power supply line scanning circuit and the first electro-Iuminescent
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`element while a signal voltage generation circuit is generating the first display signal
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`voltage, and the power supply line scanning circuit seguentially turns on and off a
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`second power supply line switch which connects the power supply line scanning circuit
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`and the second electro-Iuminescent element while the signal Voltage generation circuit
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`is generating the .second display signal voltage.
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`Shirasaki et al. teach wherein the power supply line scanning circuit
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`seguentially turns on and off a first power supply line switch which connects the
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`power supply line scanning circuit and the first electro-luminescent element while
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`a signal voltage generation circuit is generating the first display signal voltage,
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`and the power supply line scanning circuit seguentially turns on and off a second
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`Application/Control Number: 12/588,205
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`Page 6
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`Art Unit: 2694
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`power supply line switch which connects the power supply line scanning circuit
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`and the second electro-luminescent element while the signal voltage generation
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`circuit is generating the second display signal voltage (Shirasaki et al., Fig. 1, refer
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`to emission voltage scan driver 4, paragraph 70, “This emission voltage scan driver4 is
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`a so-ca/led shift register. That is, in accordance with the control signals ([52 output from
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`the controller 6, the emission voltage scan driver 4 sequential/y outputs pulse signals to
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`the emission voltage scan lines in turn from the emission voltage scan line Z1 to the
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`emission voltage scan line Zm’3.
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`It would have been obvious to one of ordinary skill in the art at the time of the
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`invention, to modify the power line scanning circuit of Akimoto et al. and Libsch, by
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`adding a first power supply line switch which connects the power supply line scanning
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`circuit and the first electro-luminescent element while a signal voltage generation circuit
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`is generating the first display signal voltage and a second power supply line switch
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`which connects the power supply line scanning circuit and the second electro-
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`luminescent element while the signal voltage generation circuit is generating the second
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`display signal voltage and sequentially turning on and off said first and second power
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`supply line switches, as taught by Shirasaki, for the purpose of stably displaying
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`images with the desired luminance (Shirasaki, paragraph 11).
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`With respect to claim 2, Akimoto, Libsch and Shirasaki disclose, an image
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`display device
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`according to claim 1 (see above), further comprising:
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`Application/Control Number: 12/588,205
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`Page 7
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`Art Unit: 2694
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`a power supply input line (Akimoto, 18 in fig. 7) connected to the first power
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`supply line (Akimoto, line between 65 and 63 in fig. 7) via a first power supply line
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`switch (Akimoto, 65 in fig. 7).
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`With respect to claim 3, Akimoto, Libsch and Shirasaki disclose, an image
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`display device according to claim 1 (see above),
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`wherein the first pixel further comprises a first reset switch (Akimoto, 64 in fig. 7)
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`connecting a current terminal of the first driving TFT and the gate terminal of the first
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`driving TFT (Akimoto, fig. 7),
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`wherein the second pixel further comprises a second reset switch connecting the
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`first current terminal of the second driving TFT and the gate terminal of the second
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`driving TFT (Akimoto, the pixel circuitry in fig. 7 is common to all the pixels).
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`The Figure 7 embodiment of Akimoto, as cited above, does not expressly
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`disclose that the reset switch is connects the first current terminal of the first driving TFT
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`and the gate terminal of the first driving TFT.
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`The Figure 6 embodiment of Akimoto discloses a first pixel that comprises a first
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`reset switch (5 in fig. 6) connecting a first current terminal of the first driving TFT and the
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`gate terminal of the first driving TFT (fig. 6).
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`At the time of the invention it would have been obvious to one of ordinary skill in
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`the art to perform the simple substitution of the reset switch taught in the Figure 6
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`embodiment of Akimoto for the reset switch taught in the Figure 7 embodiment. The
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`Page 8
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`resulting pixel circuit would have provided predictable results of reversing the
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`white/black analog relation of the signal voltage (Akimoto, column 9, lines 15-25).
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`With respect to claim 4, Akimoto, Libsch and Shirasaki disclose, an image
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`display device according to claim 2 (see above), further comprising:
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`a third pixel comprising a third electro-luminescent element driven to illuminate
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`according to a third display signal voltage, a third driving TFT whose first current
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`terminal is connected to a first terminal of the first electro-luminescent element, and a
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`third storage capacitor whose first terminal is connected to a gate of the third driving
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`TFT (Akimoto; bottom left pixel in fig. 1, for example);
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`a fourth pixel comprising a fourth electro-luminescent element driven to illuminate
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`according to a fourth display signal voltage, a fourth driving TFT whose first current
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`terminal is connected to a first terminal of the fourth electro-luminescent element, and a
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`fourth storage capacitor whose first terminal is connected to a gate of the fourth driving
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`TFT (Akimoto; bottom right pixel in fig. 1, for example);
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`a second power supply line (Libsch; Power Driver Line B in fig. 3) connected to
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`the power supply input line (Akimoto; line between 65 and 63 in fig. 7) via a second
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`supply line switch (Akimoto; 65 in fig. 7), supplying the supply voltage to the third
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`electro-luminescent element via a channel of the third driving TFT, and supplying the
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`supply voltage to the fourth electro-luminescent element via a channel of the fourth
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`driving TFT (Libsch; fig. 3);
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`

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`Application/Control Number: 12/588,205
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`Page 9
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`Art Unit: 2694
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`a signal voltage generation circuit supplying the first display signal voltage to the
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`first electro-luminescent element, supplying the second display signal voltage to the
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`second electro-luminescent element, supplying the third display signal voltage to the
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`third electro-luminescent element, and supplying the fourth display signal voltage to the
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`fourth electro-luminescent element (Akimoto; 21 in fig. 1);
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`a driving wave input line supplying a driving wave voltage to the first capacitor,
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`the second capacitor, the third capacitor, and the fourth capacitor (Akimoto; 27 in fig. 1);
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`a first signal line connected to a second terminal of the first capacitor and a
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`second terminal of the third capacitor (Akimoto; left-most 17 in fig. 1);
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`a second signal line connected to a second terminal of the second capacitor and
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`a second terminal of the fourth capacitor (Akimoto; right-most 17 in fig. 1);
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`a first signal switch selecting to connect the first signal line and the signal voltage
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`generation circuit or to connect the first signal line and the driving wave input line
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`(Akimoto; 23 and 26 in fig. 1); and
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`a second signal switch selecting to connect the second signal line and the signal
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`voltage generation circuit or to connect the second signal line and the driving wave input
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`line (Akimoto; 24, 26, 30 in fig. 1).
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`With respect to claim 5, Akimoto, Libsch and Shirasaki disclose, an image
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`display device according to claim 4 (see above), wherein a wave form of the driving
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`wave voltage is one triangular wave (Akimoto, 17 in fig. 3).
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`

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`Application/Control Number: 12/588,205
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`Page 10
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`Art Unit: 2694
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`With respect to claim 6, Akimoto, Libsch and Shirasaki disclose, an image
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`display device according to claim 4 (see above), wherein a wave form of the driving
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`wave voltage is repeated in each frame period (Akimoto, col. 5,
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`|1.46-49, col. 6, I153-
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`56).
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`Conclusion
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`Any inquiry concerning this communication or earlier communications from the
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`examiner should be directed to JOSE SOTO LOPEZ whose telephone number is
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`(571)270-5689. The examiner can normally be reached on Monday to Friday, from 8am
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`to 5pm.
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`If attempts to reach the examiner by telephone are unsuccessful, the examiner’s
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`supervisor, Sumati Lefkowitz can be reached on (571)272-3638. The fax phone
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`number for the organization where this application or proceeding is assigned is 571 -
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`273-8300.
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`

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`Application/Control Number: 12/588,205
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`Page 11
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`Art Unit: 2694
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`Information regarding the status of an application may be obtained from the
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`
`published applications may be obtained from either Private PAIR or Public PAIR.
`
`Status information for unpublished applications is available through Private PAIR only.
`
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`
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`
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`
`/JOSE R SOTO LOPEZ/
`
`Examiner, Art Unit 2694
`
`/Sumati Lefkowitz/
`
`Supervisory Patent Examiner, Art Unit 2694
`
`