`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria1 Virginia 22313- 1450
`www.uspto.gov
`
`APPLICATION NO.
`
`
`
`
`
` F ING DATE
`
`FIRST NAMED INVENTOR
`
`ATTORNEY DOCKET NO.
`
`
`
`
`CONF {MATION NO.
`
`12/588,205
`
`10/07/2009
`
`Hajime Akimoto
`
`HITA—1279
`
`5092
`
`7590
`1997,9919
`9999c99199 AMq —
`c/o Stites & Harbison PLLC
`SOTO LOPEZ, JOSE R
`1199 North Fairfax Street
`9 999
`Alexandria, VA 223 14- 1437
`
`NM
`
`2694
`
`
`
`
`NOT *ICATION DATE
`
`DELIVERY MODE
`
`11/27/2013
`
`ELECTRONIC
`
`Please find below and/0r attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above—indicated "Notification Date" to the
`following e—mail address(es):
`
`iplaw @ stites.com
`
`PTOL—90A (Rev. 04/07)
`
`

`

`
`
`Applicant(s)
`Application No.
` 12/588,205 AKIMOTO ET AL.
`
`Examiner
`Art Unit
`AIA (First Inventor to File)
`Office Action Summary
`
`JOSE SOTO LOPEZ [SENS 2694
`
`-- The MAILING DA TE of this communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`
`
`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE 3 MONTH(S) OR THIRTY (30) DAYS,
`WHICHEVER IS LONGER, FROM THE MAILING DATE OF THIS COMMUNICATION.
`Extensions of time may be available under the provisions of 37 CFR 1.136(a).
`In no event however may a reply be timely filed
`after SIX () MONTHS from the mailing date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any
`earned patent term adjustment. See 37 CFR 1 .704(b).
`
`Status
`
`1)IZI Responsive to communication(s) filed on 08/27/2013.
`El A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/were filed on
`
`2b)|:l This action is non-final.
`2a)|Z| This action is FINAL.
`3)I:I An election was made by the applicant in response to a restriction requirement set forth during the interview on
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`; the restriction requirement and election have been incorporated into this action.
`
`4)|:| Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
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`closed in accordance with the practice under Exparte Quay/e, 1935 CD. 11, 453 O.G. 213.
`
`Disposition of Claims
`
`5)IZI Claim(s) L6is/are pending in the application.
`5a) Of the above claim(s)
`is/are withdrawn from consideration.
`
`is/are allowed.
`6)I:I Claim(s)
`7)|Z| Claim(s)_1-6is/are rejected.
`8)|:I Claim(s)_ is/are objected to.
`
`
`are subject to restriction and/or election requirement.
`9)I:I Claim((s)
`* If any claims have been determined allowable, you may be eligible to benefit from the Patent Prosecution Highway program at a
`
`participating intellectual property office for the corresponding application. For more information, please see
`hit
`:/'I’vaIW.usnI‘.0. ovI’ atentS/init events/
`
`
`
`hI/index.‘s or send an inquiry to PPI-iieedback{®usgtc.00v.
`
`Application Papers
`
`10)I:l The specification is objected to by the Examiner.
`11)I:l The drawing(s) filed on
`is/are: a)I:I accepted or b)I:I objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`
`12)I:| Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
`Certified copies:
`
`a)I:l All
`
`b)|:l Some * c)I:l None of the:
`
`1.I:I Certified copies of the priority documents have been received.
`2.|:l Certified copies of the priority documents have been received in Application No.
`3.|:| Copies of the certified copies of the priority documents have been received in this National Stage
`
`application from the International Bureau (PCT Rule 17.2(a)).
`* See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`1) D Notice of References Cited (PTO-892)
`
`3) D Interview Summary (PTO-413)
`
`Paper N°ISI/Ma" Date' —
`PTO/SB/Os
`t
`t
`St
`I
`D'
`I'
`f
`2 I] I
`)
`4) I:I Other:
`a emen (s) (
`Isc osure
`n orma Ion
`)
`Paper No(s)/Mai| Date
`US. Patent and Trademark Office
`PTOL—326 (Rev. 08—13)
`
`Part of Paper No./Mai| Date 20131118
`
`Office Action Summary
`
`

`

`Application/Control Number: 12/588,205
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`Page 2
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`Art Unit: 2694
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`DETAILED ACTION
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`1.
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`The present application is being examined under the pre-AIA first to invent
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`provisions.
`
`Response to Arguments
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`2.
`
`Applicant's arguments filed 08/27/2013 have been fully considered but they are
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`not persuasive.
`
`As per claim 1, Applicant argues as follows:
`
`“Akimoto, either alone or in combination with Libsch and/or Shirasaki, fails to
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`teach, suggest, or disclose each and every limitation of claims 1 -6. For example, none
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`of the cited references teach or suggest that "the power supply line scanning circuit
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`sequentially turns on and off a first power supply line switch which connects the power
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`supply line scanning circuit and the first electro-luminescent element while a signal
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`voltage generation circuit is generating the first display signal voltage, and the power
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`supply line scanning circuit sequentially turns on and off a second power supply line
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`switch which connects the power supply line scanning circuit and the second electro-
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`luminescent element while the signal voltage generation circuit is generating the second
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`display signal voltage " as required by independent claim 1”
`
`

`

`Application/Control Number: 12/588,205
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`Page 3
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`Art Unit: 2694
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`The Office respectfully disagrees and submits that Shirasaki teaches the claimed
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`limitation. Shirasaki teaches, in Fig. 7, wherein the voltage applied to the power supply
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`line (Z) is switched between a first level VSE during a first period T35 and a second level
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`VNSE during a second period TNSE A first period wherein the switch outputs a voltage VSE
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`is being construed as the claimed “off” state and a second period wherein the switch
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`outputs a voltage VNSE is being construed as the claimed “on” state. As noted by
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`Applicant (Remarks, page 7), during the off state, no current flows through the LED
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`element (Shirasaki, paragraph 85, In this selection period T35, the selection voltage VSE
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`of the emission voltage scan line Z,- is equal to or lower than the reference voltage Vss,
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`and the anode potential of the organic EL element E,-,,- becomes lower than that of its
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`cathode potential. 80, a reverse bias voltage is applied to this organic EL element EL).
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`Consequently, no electric current from the emission voltage scan line Z,- f/ows through
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`the organic EL element EU). Furthermore, during the “on” state, current flows through
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`the LED element (Shirasaki, Fig. SB, paragraph 88-91, “Accordingly, as shown in FIG.
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`5B, in this non-selection period TNSE by flowing toward the low reference potential Vss
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`via the organic EL element E,-,,-, a display current flows through the organic EL layer 42
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`between the anode 41 and cathode 43 of the organic EL element EL), i.e., the source-
`
`drain current log of the transistor 12 flows. So, the organic EL element E,-,,- emits light”).
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`Furthermore, the change from the off-state to the on-state occurs while the signal
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`voltage is being stored in capacitor 13 (Shirasaki, paragraph 72, “During the selection
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`period, the data driver 5 stores electric charge, as current data, which has a magnitude
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`corresponding to the current value of this memory current, in each capacitor 13”). This
`
`

`

`Application/Control Number: 12/588,205
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`Page 4
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`Art Unit: 2694
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`switching process is sequentially performed for a plurality of display rows throughout a
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`sequence of frames. Therefore, Akimoto as modified by Libsch et al. and Shirasaki
`
`teach wherein the power supply line scanning circuit sequential/y turns on and off a first
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`power supply line switch which connects the power supply line scanning circuit and the
`
`first electro-luminescent element while a signal voltage generation circuit is generating
`
`the first display signal voltage, and the power supply line scanning circuit sequential/y
`
`turns on and off a second power supply line switch which connects the power supply
`
`line scanning circuit and the second electro-luminescent element while the signal
`
`voltage generation circuit is generating the second display signal voltage”.
`
`Claim Rejections - 35 USC § 103
`
`1.
`
`The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all
`
`obviousness rejections set forth in this Office action:
`
`(a) A patent may not be obtained through the invention is not identically disclosed or described as set
`forth in section 102 of this title, if the differences between the subject matter sought to be patented and
`the prior art are such that the subject matter as a whole would have been obvious at the time the
`invention was made to a person having ordinary skill in the art to which said subject matter pertains.
`Patentability shall not be negatived by the manner in which the invention was made.
`
`2.
`
`Claims 1-6 are rejected under 35 U.S.C. 103(a) as being unpatentable over
`
`Akimoto et al., US 6,950,081; in view of Libsch et al., US 7,167,169; in further view
`
`of Shirasaki et al., US 2004/0113873.
`
`

`

`Application/Control Number: 12/588,205
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`Page 5
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`Art Unit: 2694
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`With respect to claim 1, Akimoto discloses, an image display device (fig. 1, for
`
`example) comprising:
`
`a first pixel (fig. 7; analogous to top left pixel in fig. 1) comprising a first electro-
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`luminescent element (7) driven to illuminate according to a first display signal voltage
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`(signal applied to 17), a first driving TFT whose first current terminal is connected to a
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`first terminal of the first electro-luminescent element (63), and a first storage capacitor
`
`whose first terminal is connected to a gate terminal of the first driving TFT (2);
`
`a second pixel comprising a second electro-luminescent element driven to
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`illuminate according to a second display voltage, a second driving TFT whose current
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`terminal is connected to a first terminal of the second electro-luminescent element, and
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`a second storage capacitor whose first terminal is connected to a gate of the second
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`driving TFT (second pixel is top right pixel in fig. 1, for example);
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`a first power supply line (line between 65 and 63 in fig. 7) supplying a supply
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`voltage to the first electro-luminescent element via a channel of the first driving TFT (fig.
`
`7); and
`
`supplying a supply voltage to the first electro-luminescent element via a channel
`
`of the first driving TFT flsupplying the supply We to the second electro-
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`luminescent element via a channel of the second driving TFT seguentially (column 11,
`
`lines 35-40, “During the "write period" (being the first half of one frame), the gate drive
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`circuit 82 sequentially scans each of the pixel rows”, based on this operation, the
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`supply voltage is inherently supplied to the pixels in a sequential manner);
`
`

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`Application/Control Number: 12/588,205
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`Page 6
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`Art Unit: 2694
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`Akimoto does not expressly disclose, a first power supply line supplying a supply
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`voltage according to scanning the first power supply line by a power supply line
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`scanning circuit.
`
`Libsch discloses, a first power supply line (Power Driver Line A in fig. 3)
`
`supplying a supply voltage according to scanning the first power supply line by a power
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`supply line scanning circuit (Libsch et al., Fig. 3, refer to power driver line A and power
`
`driver line B, see also Fig. 4 and column 7, lines 10-20, “V(1)-1, V(1)-2,. .. V(1)-N
`
`represent line waveforms analogous to Vsupp/y 425 for row 1, 2, .
`
`.
`
`. N, respectively,
`
`for OLED array 410.”)
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`Libsch and Akimoto are analogous art because they are from the same field of
`
`invention EL control circuitry.
`
`At the time of the invention it would have been obvious to one of ordinary skill in
`
`the art to substitute the power supply lines of Akimoto et al. with power supply lines
`
`supplying a supply voltage according to scanning the power supply lines by a power
`
`supply line scanning circuit, such as taught by Libsch, for the purpose of illuminating the
`
`OLED using a duty cycle of less than 100% (Libsch et al., column 5, lines 10-20).
`
`Akimoto et al. as modified by Libsch do not explicitly teach wherein the power
`
`supply line scanning circuit seguentially turns on and off a first power supply, line switch
`
`which connects the power supply line scanning circuit and the first electro-luminescent
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`element while a signal voltage generation circuit is generating the first display signal
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`voltage, and the power supply line scanning circuit seguentially turns on and off a
`
`second power supply line switch which connects the power supply line scanning circuit
`
`

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`Application/Control Number: 12/588,205
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`Page 7
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`Art Unit: 2694
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`and the second electro-luminescent element while the signal Voltage generation circuit
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`is generating the .second display signal voltage.
`
`Shirasaki et al. teach wherein the power supply line scanning circuit
`
`seguentially turns on and off a first power supply line switch which connects the
`
`power supply line scanning circuit and the first electro-luminescent element while
`
`a signal voltage generation circuit is generating the first display signal voltage,
`
`and the power supply line scanning circuit seguentially turns on and off a second
`
`power supply line switch which connects the power supply line scanning circuit
`
`and the second electro-luminescent element while the signal voltage generation
`
`circuit is generating the second display signal voltage (Shirasaki et al., Fig. 1, refer
`
`to emission voltage scan driver 4, paragraph 70, “This emission voltage scan driver 4 is
`
`a so-called shift register. That is, in accordance with the control signals (/52 output from
`
`the controller 6, the emission voltage scan driver 4 sequential/y outputs pulse signals to
`
`the emission voltage scan lines in turn from the emission voltage scan line Z to the
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`emission voltage scan line Zm’3.
`
`It would have been obvious to one of ordinary skill in the art at the time of the
`
`invention, to modify the power line scanning circuit of Akimoto et al. and Libsch, by
`
`adding a first power supply line switch which connects the power supply line scanning
`
`circuit and the first electro-luminescent element while a signal voltage generation circuit
`
`is generating the first display signal voltage and a second power supply line switch
`
`which connects the power supply line scanning circuit and the second electro-
`
`luminescent element while the signal voltage generation circuit is generating the second
`
`

`

`Application/Control Number: 12/588,205
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`Page 8
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`Art Unit: 2694
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`display signal voltage and sequentially turning on and off said first and second power
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`supply line switches, as taught by Shirasaki, for the purpose of stably displaying
`
`images with the desired luminance (Shirasaki, paragraph 11).
`
`With respect to claim 2, Akimoto, Libsch and Shirasaki disclose, an image
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`display device
`
`according to claim 1 (see above), further comprising:
`
`a power supply input line (Akimoto, 18 in fig. 7) connected to the first power
`
`supply line (Akimoto, line between 65 and 63 in fig. 7) via a first power supply line
`
`switch (Akimoto, 65 in fig. 7).
`
`With respect to claim 3, Akimoto, Libsch and Shirasaki disclose, an image
`
`display device according to claim 1 (see above),
`
`wherein the first pixel further comprises a first reset switch (Akimoto, 64 in fig. 7)
`
`connecting a current terminal of the first driving TFT and the gate terminal of the first
`
`driving TFT (Akimoto, fig. 7),
`
`wherein the second pixel further comprises a second reset switch connecting the
`
`first current terminal of the second driving TFT and the gate terminal of the second
`
`driving TFT (Akimoto, the pixel circuitry in fig. 7 is common to all the pixels).
`
`The Figure 7 embodiment of Akimoto, as cited above, does not expressly
`
`disclose that the reset switch is connects the first current terminal of the first driving TFT
`
`and the gate terminal of the first driving TFT.
`
`

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`Application/Control Number: 12/588,205
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`Page 9
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`Art Unit: 2694
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`The Figure 6 embodiment of Akimoto discloses a first pixel that comprises a first
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`reset switch (5 in fig. 6) connecting a first current terminal of the first driving TFT and the
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`gate terminal of the first driving TFT (fig. 6).
`
`At the time of the invention it would have been obvious to one of ordinary skill in
`
`the art to perform the simple substitution of the reset switch taught in the Figure 6
`
`embodiment of Akimoto for the reset switch taught in the Figure 7 embodiment. The
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`resulting pixel circuit would have provided predictable results of reversing the
`
`white/black analog relation of the signal voltage (Akimoto, column 9, lines 15-25).
`
`With respect to claim 4, Akimoto, Libsch and Shirasaki disclose, an image
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`display device according to claim 2 (see above), further comprising:
`
`a third pixel comprising a third electro-luminescent element driven to illuminate
`
`according to a third display signal voltage, a third driving TFT whose first current
`
`terminal is connected to a first terminal of the first electro-luminescent element, and a
`
`third storage capacitor whose first terminal is connected to a gate of the third driving
`
`TFT (Akimoto; bottom left pixel in fig. 1, for example);
`
`a fourth pixel comprising a fourth electro-luminescent element driven to illuminate
`
`according to a fourth display signal voltage, a fourth driving TFT whose first current
`
`terminal is connected to a first terminal of the fourth electro-luminescent element, and a
`
`fourth storage capacitor whose first terminal is connected to a gate of the fourth driving
`
`TFT (Akimoto; bottom right pixel in fig. 1, for example);
`
`

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`Application/Control Number: 12/588,205
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`Page 10
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`Art Unit: 2694
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`a second power supply line (Libsch; Power Driver Line B in fig. 3) connected to
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`the power supply input line (Akimoto; line between 65 and 63 in fig. 7) via a second
`
`supply line switch (Akimoto; 65 in fig. 7), supplying the supply voltage to the third
`
`electro-luminescent element via a channel of the third driving TFT, and supplying the
`
`supply voltage to the fourth electro-luminescent element via a channel of the fourth
`
`driving TFT (Libsch; fig. 3);
`
`a signal voltage generation circuit supplying the first display signal voltage to the
`
`first electro-luminescent element, supplying the second display signal voltage to the
`
`second electro-luminescent element, supplying the third display signal voltage to the
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`third electro-luminescent element, and supplying the fourth display signal voltage to the
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`fourth electro-luminescent element (Akimoto; 21 in fig. 1);
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`a driving wave input line supplying a driving wave voltage to the first capacitor,
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`the second capacitor, the third capacitor, and the fourth capacitor (Akimoto; 27 in fig. 1);
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`a first signal line connected to a second terminal of the first capacitor and a
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`second terminal of the third capacitor (Akimoto; left-most 17 in fig. 1);
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`a second signal line connected to a second terminal of the second capacitor and
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`a second terminal of the fourth capacitor (Akimoto; right-most 17 in fig. 1);
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`a first signal switch selecting to connect the first signal line and the signal voltage
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`generation circuit or to connect the first signal line and the driving wave input line
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`(Akimoto; 23 and 26 in fig. 1); and
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`

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`Application/Control Number: 12/588,205
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`Page 11
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`Art Unit: 2694
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`a second signal switch selecting to connect the second signal line and the signal
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`voltage generation circuit or to connect the second signal line and the driving wave input
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`line (Akimoto; 24, 26, 30 in fig. 1).
`
`With respect to claim 5, Akimoto, Libsch and Shirasaki disclose, an image
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`display device according to claim 4 (see above), wherein a wave form of the driving
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`wave voltage is one triangular wave (Akimoto, 17 in fig. 3).
`
`With respect to claim 6, Akimoto, Libsch and Shirasaki disclose, an image
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`display device according to claim 4 (see above), wherein a wave form of the driving
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`wave voltage is repeated in each frame period (Akimoto, col. 5, l1.46-49, col. 6, I153-
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`56).
`
`Conclusion
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`THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time
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`policy as set forth in 37 CFR 1.136(a).
`
`A shortened statutory period for reply to this final action is set to expire THREE
`
`MONTHS from the mailing date of this action.
`
`In the event a first reply is filed within
`
`TWO MONTHS of the mailing date of this final action and the advisory action is not
`
`mailed until after the end of the THREE-MONTH shortened statutory period, then the
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`shortened statutory period will expire on the date the advisory action is mailed, and any
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`extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of
`
`

`

`Application/Control Number: 12/588,205
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`Page 12
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`Art Unit: 2694
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`the advisory action.
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`In no event, however, will the statutory period for reply expire later
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`than SIX MONTHS from the mailing date of this final action.
`
`Any inquiry concerning this communication or earlier communications from the
`
`examiner should be directed to JOSE SOTO LOPEZ whose telephone number is
`
`(571 )270-5689. The examiner can normally be reached on Monday to Friday, from 8am
`
`to 5pm.
`
`If attempts to reach the examiner by telephone are unsuccessful, the examiner’s
`
`supervisor, Sumati Lefkowitz can be reached on (571)272-3638. The fax phone
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`number for the organization where this application or proceeding is assigned is 571 -
`
`273-8300.
`
`Information regarding the status of an application may be obtained from the
`
`Patent Application Information Retrieval (PAIR) system. Status information for
`
`published applications may be obtained from either Private PAIR or Public PAIR.
`
`Status information for unpublished applications is available through Private PAIR only.
`
`For more information about the PAIR system, see http://pair-direct.uspto.gov. Should
`
`you have questions on access to the Private PAIR system, contact the Electronic
`
`Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a
`
`USPTO Customer Service Representative or access to the automated information
`
`system, call 800-786-9199 (IN USA OR CANADA) or 571-272—1000.
`
`/JOSE R SOTO LOPEZ/
`
`Examiner, Art Unit 2694
`
`/SUMATI LEFKOWITZ/
`
`Supervisory Patent Examiner, Art Unit 2694
`
`