`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria1 Virginia 22313- 1450
`wwwnsptogov
`
`APPLICATION NO.
`
`
`
`
` F ING DATE
`
`FIRST NAMED INVENTOR
`
`ATTORNEY DOCKET NO.
`
`
`
`
`CONF {MATION NO.
`
`12/702,987
`
`02/09/2010
`
`Katsumi MATSUMOTO
`
`501.50560X00
`
`3171
`
`20457
`
`7590
`
`09/11/2013
`
`ANTONELLLTERRY,STOUT&KRAUS,LLP
`1300 NORTH SEVENTEENTH STREET
`SUITE 1 800
`ARLINGTON, VA 22209-3873
`
`PARKER, JEFFREY ALAN
`
`2699
`
`MAIL DATE
`
`09/11/2013
`
`PAPER NUMBER
`
`DELIVERY MODE
`
`PAPER
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`PTOL—90A (Rev. 04/07)
`
`

`

`
`
`Applicant(s)
`Application No.
` 12/702,987 MATSUMOTO, KATSUMI
`
`Examiner
`Art Unit
`AIA (First Inventor to File)
`Office Action Summary
`
`JEFFREY A. PARKER [SENS 2699
`
`-- The MAILING DA TE of this communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`
`
`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE 3 MONTH(S) OR THIRTY (30) DAYS,
`WHICHEVER IS LONGER, FROM THE MAILING DATE OF THIS COMMUNICATION.
`Extensions of time may be available under the provisions of 37 CFR 1.136(a).
`In no event however may a reply be timely filed
`after SIX () MONTHS from the mailing date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any
`earned patent term adjustment. See 37 CFR 1 .704(b).
`
`Status
`
`1)IZI Responsive to communication(s) filed on 9 February 2010.
`El A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/were filed on
`
`2b)|ZI This action is non-final.
`2a)|:l This action is FINAL.
`3)I:I An election was made by the applicant in response to a restriction requirement set forth during the interview on
`
`; the restriction requirement and election have been incorporated into this action.
`
`4)|:| Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`
`closed in accordance with the practice under Exparte Quay/e, 1935 CD. 11, 453 O.G. 213.
`
`Disposition of Claims
`
`5)IZI Claim(s) His/are pending in the application.
`5a) Of the above claim(s)
`is/are withdrawn from consideration.
`
`is/are allowed.
`6)I:I Claim(s)
`7)|Z| Claim(s)_1-7is/are rejected.
`8)|:I Claim(s)_ is/are objected to.
`
`
`are subject to restriction and/or election requirement.
`9)I:I Claim((s)
`* If any claims have been determined allowable, you may be eligible to benefit from the Patent Prosecution Highway program at a
`
`participating intellectual property office for the corresponding application. For more information, please see
`hit
`I/'/\WIIW.USOI.O. ovI’ atentS/init events/
`
`
`
`hI/index.‘s or send an inquiry to PPI-iieedback{®usgtc.00v.
`
`Application Papers
`
`10)I:l The specification is objected to by the Examiner.
`11)|Xl The drawing(s) filed on 09 February 2010 is/are: a)IZI accepted or b)I:I objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`
`12)IXI Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
`Certified copies:
`
`a)IZl All
`
`b)|:l Some * c)I:l None of the:
`
`1.IXI Certified copies of the priority documents have been received.
`2.|:l Certified copies of the priority documents have been received in Application No.
`3.|:| Copies of the certified copies of the priority documents have been received in this National Stage
`
`application from the International Bureau (PCT Rule 17.2(a)).
`* See the attached detailed Office action for a list of the certified copies not received.
`
`Interim copies:
`
`a)|:l All
`
`b)I:I Some
`
`c)I:I None of the:
`
`Interim copies of the priority documents have been received.
`
`Attachment(s)
`
`1) E Notice of References Cited (PTO-892)
`
`3) D Interview Summary (PTO-413)
`
`Paper N°ISI/Ma" Date' —
`PTO/SB/08
`t
`t
`St
`I
`D'
`I'
`f
`2 IZI I
`)
`4) I:I Other:
`a emen (s) (
`Isc osure
`n orma Ion
`)
`Paper No(s)/Mai| Date 2/9/2010.
`U.S. Patent and Trademark Office
`PTOL—326 (Rev. 03-13)
`
`Part of Paper No./Mai| Date 20130614
`
`Office Action Summary
`
`

`

`Application/Control Number: 12/702,987
`
`Page 2
`
`Art Unit: 2699
`
`DETAILED ACTION
`
`Specification
`
`The disclosure is objected to because ofthe following informalities: Numerous locations
`
`in the Specification state "Fig. 7A and 7B” but should say ”Fig. 7" because there is only a Fig. 7
`
`and not a Fig. 7A and 7B. For instance, page 3, lines 15, 19, 20, 21, page 4, lines 17, 18, 21, 23,
`
`page 5, lines 4, 5, 17, page 6, line 2, and page 11, line 15.
`
`Appropriate correction is required.
`
`Claim Rejections - 35 USC § 103
`
`The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness
`
`rejections set forth in this Office action:
`
`(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in
`section 102 of this title, if the differences between the subject matter sought to be patented and the prior art
`are such that the subject matter as a whole would have been obvious at the time the invention was made to a
`person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be
`negatived by the manner in which the invention was made.
`
`The factual inquiries set forth in Graham v. John Deere C0,, 383 U.S. 1, 148 USPQ 459
`
`(1966), that are applied for establishing a background for determining obviousness under 35
`
`U.S.C. 103(a) are summarized as follows:
`
`1.
`
`Determining the scope and contents of the prior art.
`
`

`

`Application/Control Number: 12/702,987
`
`Page 3
`
`Art Unit: 2699
`
`2.
`
`3.
`
`4.
`
`Ascertaining the differences between the prior art and the claims at issue.
`
`Resolving the level of ordinary skill in the pertinent art.
`
`Considering objective evidence present in the application indicating obviousness
`or nonobviousness.
`
`Claims 1-7 are rejected under 35 U.S.C. 103(a) as being unpatentable over U.S.
`
`Publication 2009/0236600 to Yamazaki in view of Applicant’s Disclosure of known prior art in
`
`the Specification, Fig. 7A, 7B, and paragraphs 5-10, as Applicant Admitted Prior Art, herein
`
`AAPA.
`
`FEG. 4
`
`fieefiiefi $eemefiefiee Lees?
`
`
`
`fieeefiefi fieefieee‘efiefiee mew fie see “éfiemfi eeefiegefieg fie fiefie fieefiefifi
`
`

`

`Application/Control Number: 12/702,987
`
`Page 4
`
`Art Unit: 2699
`
`Regarding claim 1, Yamazaki teaches a liquid crystal display device comprising:
`
`the thin film transistor is constituted of a gate electrode, a gate insulation film which is
`
`formed so as to cover the gate electrode, a semiconductor layer which is formed on an upper
`
`surface of the gate insulation film, and a pair of electrodes which is arranged to face each other
`
`in an opposed manner on an upper surface of the semiconductor layer from the substrate side
`
`as viewed in a plan view (see paragraph 54 and Fig. 1 and 4 showing the gate electrode 5,
`
`semiconductor layer consisting of 51a/b and 53a/b over the gate insulating film 9, and
`
`source/drain electrodes 63 and 65),
`
`the semiconductor layer is formed of a stacked body consisting of a microcrystalline
`
`semiconductor layer and an amorphous semiconductor layer from the substrate side, and the
`
`semiconductor layer is formed in an island shape within a region where the gate electrode is
`
`formed as viewed in a plan view (see paragraphs 68, 101 and 102 and Fig. 4 showing the region
`
`51a/b is microcrystalline semiconductor layer and 53a/b is amorphous semiconductor layer and
`
`both are islands overlapping with the gate electrode 5 below), and
`
`each one ofthe pair of electrodes is formed such that, as viewed in a plan view, sides of
`
`the each one electrode excluding a side ofthe each one electrode which faces the other
`
`electrode project outwardly from the semiconductor layer, and a portion of the each one
`
`electrode which projects outwardly from the semiconductor layer overlaps with the gate
`
`electrode at least on the periphery of the semiconductor layer (see Fig. 4 showing the
`
`source/drain electrodes 63/65 facing each other and the other sides extending overlapping the
`
`semiconductor layer 51a/b, 53a/b and the gate electrode 5).
`
`

`

`Application/Control Number: 12/702,987
`
`Page 5
`
`Art Unit: 2699
`
`Yamazaki does not explicitly teach that a liquid crystal display panel having a pair of
`
`substrates which is arranged to face each other in an opposed manner with liquid crystal
`
`sandwiched therebetween; and
`
`a backlight arranged on a one-side surface ofthe liquid crystal display panel,
`
`thin film transistors being formed on a liquid-crystal-side surface of the substrate on a
`
`backlight side.
`
`However, AAPA supplies this operating context as follows (see Figs. 7A and 7B and
`
`paragraphs 5-10):
`
`a liquid crystal display panel having a pair of substrates which is arranged to face each
`
`other in an opposed manner with liquid crystal sandwiched therebetween (see paragraph 7);
`
`and
`
`a backlight arranged on a one-side surface ofthe liquid crystal display panel (see
`
`paragraph 7),
`
`thin film transistors being formed on a liquid-crystal-side surface of the substrate on a
`
`backlight side (see paragraphs 7 and 8).
`
`It would have been obvious to a person having ordinary skill in the art to apply the LCD
`
`pixel TFT taught by Yamazaki with the LCD backlight of AAPA for the purpose of providing
`
`necessary implementation details of an LCD and backlight implied by the LCD pixel teachings of
`
`the Yamazaki TFT (see paragraphs 4, 10, and 103).
`
`

`

`Application/Control Number: 12/702,987
`
`Page 6
`
`Art Unit: 2699
`
`Regarding claim 2, Yamazaki in view of AAPA teaches a liquid crystal display device
`
`according to claim 1. Yamazaki teaches wherein the semiconductor layer is formed such that a
`
`whole region of the microcrystalline semiconductor layer and a whole region ofthe amorphous
`
`semiconductor layer overlap with each other as viewed in a plan view (see Fig. 4 and paragraph
`
`102).
`
`Regarding claim 3, Yamazaki in view of AAPA teaches a liquid crystal display device
`
`according to claim 1. Yamazaki teaches wherein the semiconductor layer is formed such that at
`
`least a portion of the amorphous semiconductor layer projects from the microcrystalline
`
`semiconductor layer as viewed in a plan view (see Fig. 78 showing the top layer corresponding
`
`to the doping of the AS layer projecting from the MS layer underneath — therefore it would
`
`have been obvious to try with this embodiment for predictable results).
`
`Regarding claim 4, Yamazaki in view of AAPA teaches a liquid crystal display device
`
`according to claim 1. Yamazaki teaches wherein the semiconductor layer is formed such that at
`
`least a portion of the microcrystalline semiconductor layer projects from the amorphous
`
`semiconductor layer as viewed in a plan view (see Fig. 4 showing the MS layer projecting a little
`
`bit).
`
`

`

`Application/Control Number: 12/702,987
`
`Page 7
`
`Art Unit: 2699
`
`Regarding claim 5, Yamazaki in view of AAPA teaches a liquid crystal display device
`
`according to claim 1. Yamazaki teaches wherein the liquid crystal display panel includes a
`
`plurality of pixels, and each pixel is provided with the thin film transistor (see paragraph 236).
`
`Regarding claim 6, Yamazaki in view of AAPA teaches a liquid crystal display device
`
`according to claim 1. Yamazaki teaches wherein the liquid crystal display panel has a display
`
`part which is a mass constituted of a plurality of pixels, a circuit for driving the respective pixels
`
`of the display part is formed on the periphery ofthe display part, and the circuit is provided
`
`with the thin film transistor (see paragraph 236).
`
`Regarding claim 7, Yamazaki in view of AAPA teaches a liquid crystal display device
`
`according to claim 1. Yamazaki teaches wherein the liquid crystal display panel has a display
`
`part which is a mass constituted of a plurality of pixels (see paragraph 236), and drain signal
`
`lines which supply a video signal to the pixels, a drive circuit is formed on the periphery of the
`
`display part, the drive circuit is a time-division drive circuit which is connected with the plurality
`
`of drain signal lines, and supplies the video signal to the plurality of drain signal lines in a
`
`sequentially switching manner, and the time-division drive circuit is provided with the thin film
`
`transistor (see Figs. 17A-18C and paragraph 244-250).
`
`

`

`Application/Control Number: 12/702,987
`
`Page 8
`
`Art Unit: 2699
`
`Conclusion
`
`Any inquiry concerning this communication or earlier communications from the
`
`examiner should be directed to JEFFREY A. PARKER whose telephone number is (571)270-5161.
`
`The examiner can normally be reached on M-F 9:00-6:00.
`
`If attempts to reach the examiner by telephone are unsuccessful, the examiner’s
`
`supervisor, Will Boddie can be reached on (571) 272-0666. The fax phone number for the
`
`organization where this application or proceeding is assigned is 571-273-8300.
`
`Information regarding the status of an application may be obtained from the Patent
`
`Application Information Retrieval (PAIR) system. Status information for published applications
`
`may be obtained from either Private PAIR or Public PAIR. Status information for unpublished
`
`applications is available through Private PAIR only. For more information about the PAIR
`
`system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private
`
`PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you
`
`would like assistance from a USPTO Customer Service Representative or access to the
`
`automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
`
`/JAP/
`
`/William L Boddie/
`
`Supervisory Patent Examiner, Art Unit 2699
`
`