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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria1 Virginia 22313- 1450
`wwwnsptogov
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`APPLICATION NO.
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` F ING DATE
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`FIRST NAMED INVENTOR
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`ATTORNEY DOCKET NO.
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`CONF {MATION NO.
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`12/708,9 1 5
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`02/19/2010
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`Yoshinori Horikawa
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`AOY—4066US
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`5506
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`EXAMINER
`RATNERPRESTIA —
`07W —
`”90
`52473
`PO BOX 980
`ROSARIO BENITEz, GUSTAVO A
`VALLEY FORGE, PA 19482-0980
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`PAPER NUMBER
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`ART UNIT
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`2838
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`MAIL DATE
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`07/23/2012
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`DELIVERY MODE
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`PAPER
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`Please find below and/or attached an Office communication concerning this application or proceeding.
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`The time period for reply, if any, is set in the attached communication.
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`PTOL—90A (Rev. 04/07)
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`Office Action Summary
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`Application No.
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`Applicant(s)
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`12/708,915 HORIKAWA ET AL.
`Examiner
`Art Unit
`GUSTAVO ROSARIO BENITEZ
`2838
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`-- The MAILING DA TE of this communication appears on the cover sheet with the correspondence address --
`Period for Reply
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`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE 3 MONTH(S) OR THIRTY (30) DAYS,
`WHICHEVER IS LONGER, FROM THE MAILING DATE OF THIS COMMUNICATION.
`Extensions of time may be available under the provisions of 37 CFR1. 136(a).
`In no event however may a reply be timely filed
`after SIX () MONTHS from the mailing date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any
`earned patent term adjustment. See 37 CFR 1.704(b).
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`Status
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`1)|Zl Responsive to communication(s) filed on 19 February 2010.
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`2a)|:l This action is FINAL.
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`2b)IXI This action is non-final.
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`3)|:I An election was made by the applicant in response to a restriction requirement set forth during the interview on
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`; the restriction requirement and election have been incorporated into this action.
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`4)|:l Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
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`closed in accordance with the practice under Exparte Quay/e, 1935 CD. 11, 453 O.G. 213.
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`Disposition of Claims
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`5)IZ Claim(s) L8 is/are pending in the application.
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`5a) Of the above claim(s) _ is/are withdrawn from consideration.
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`6)|:| Claim(s) _ is/are allowed.
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`7)|Xl Claim(s) 1_-8is/are rejected.
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`8)|:| Claim(s) _ is/are objected to.
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`9)|:I Claim(s) _ are subject to restriction and/or election requirement.
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`Application Papers
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`10)|:I The specification is objected to by the Examiner.
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`11)IZI The drawing(s) filed on 19 February 2010 is/are: a)EI accepted or b)|:l objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
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`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
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`12)|:I The oath or declaration is objected to by the Examiner. Note the attached Office Action or form PTO-152.
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`Priority under 35 U.S.C. § 119
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`13)|X| Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
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`a)|Z AII
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`b)|:l Some * c)I:I None of:
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`1.IXI Certified copies of the priority documents have been received.
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`2.|:l Certified copies of the priority documents have been received in Application No. _
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`3.I:I Copies of the certified copies of the priority documents have been received in this National Stage
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`application from the International Bureau (PCT Rule 17.2(a)).
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`* See the attached detailed Office action for a list of the certified copies not received.
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`Attachment(s)
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`4) I] Interview Summary (PTO-413)
`1) IZI Notice of References Cited (PTO-892)
`Paper N0(S )/Mai| Date. _
`2) I] Notice of Draftsperson‘s Patent Drawing Review (PTO-948)
`5)I:I NOTICQ 0f Informal Patent Application
`3) IZI Information Disclosure Statement(s) (PTO/SB/08)
`Paper No(s)/Mai| DateM16”: Other:—
`U.S. Patent and Trademark Office
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`PTOL-326 (Rev. 03-11)
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`Office Action Summary
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`Part of Paper No./Mai| Date 20120712
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`

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`Application/Control Number: 12/708,915
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`Page 2
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`Art Unit: 2838
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`DETAILED ACTION
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`1.
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`This office action is in response to the application filed on February 19,
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`2010.
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`Information Disclosure Statement
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`2.
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`The information disclosure statement (IDS) submitted on 02/19/2010 has been
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`considered by the examiner.
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`Specification
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`3.
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`The lengthy specification has not been checked to the extent necessary to
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`determine the presence of all possible minor errors. Applicant's cooperation is
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`requested in correcting any errors of which applicant may become aware in the
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`specification.
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`4.
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`The title of the invention is not descriptive. A new title is required that is clearly
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`indicative of the invention to which the claims are directed.
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`Claim Objections
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`5.
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`Claim 8 is objected to because of the following informalities: Claim 8 has a
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`misspelled word “ether” should be change to "either". Appropriate correction is
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`required.
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`Claim Rejections - 35 USC § 1 12
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`The following is a quotation of the second paragraph of 35 U.S.C. 112:
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`The specification shall conclude with one or more claims particularly pointing out and distinctly
`claiming the subject matter which the applicant regards as his invention.
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`Application/Control Number: 12/708,915
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`Page 3
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`Art Unit: 2838
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`6.
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`Claims 1-8 are rejected under 35 U.S.C. 112, second paragraph, as being
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`indefinite for failing to particularly point out and distinctly claim the subject matter which
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`applicant regards as the invention.
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`Claim 1 presents “selects a voltage corresponding...” It is unclear which circuit is
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`the one performing the function of selecting “a voltage” is it the selection circuit or the
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`control section. Also it is unclear to what voltage is the applicant referring to when
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`mentioning “a voltage", is it the input voltage, the output voltage or which voltage.
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`Claim 1 present “a second terminal” it’s unclear if said second terminal
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`corresponds to the selection circuit or to another circuit or to the voltage supply and if it
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`not part of the selection circuit then it would be a "first terminal" of the circuit it belongs
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`because there is no other first terminal.
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`Claim 2 presents “...said second terminal does not receive one predetermined
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`voltage...” It is unclear what is the applicant referring to by the previous statement
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`because, on Claim 1 lines 12 and 13 it is mention that the second terminal receives said
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`passed output voltage. Clarification is needed to determine how the second terminal is
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`not receiving said voltage.
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`Claim 5 presents between said first terminal” It is unclear which input terminal
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`is the applicant referring to since there are two input terminals.
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`Claims 3, 4 and 6-8 are also rejected to under 35 U.S.C. 112, second paragraph,
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`for being dependent on a rejected claim under 35 U.S.C. 112, second paragraph.
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`Application/Control Number: 12/708,915
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`Page 4
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`Art Unit: 2838
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`Claim Rejections - 35 USC § 102
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`The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that
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`form the basis for the rejections under this section made in this Office action:
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`A person shall be entitled to a patent unless —
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`(b) the invention was patented or described in a printed publication in this or a foreign country or in
`public use or on sale in this country, more than one year prior to the date of application for patent in
`the United States.
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`7.
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`Claims 1-5 are rejected under 35 U.S.C. 102(b) as being anticipated by Chiu
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`(US 7,068,019).
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`Regarding Claim 1, Chiu teaches on (Figure 5) a voltage supply circuit
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`comprising: a reference voltage generating circuit (BR) operable to generate a
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`predetermined reference voltage (Vref); an operational amplifier circuit (DA) operable to
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`generate an output voltage (Vout) on the basis of said reference voltage; a selection
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`circuit (OSU, SW1 and SW2) having at least two first terminals and controlled on the
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`basis of a control signal (81 and 82) from a control section to select one of said first
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`terminals and to generate a passed output voltage representing said output voltage
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`passed through said first terminal selected; a second terminal (at OSU) operable to
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`receive said passed output voltage and capable of outputting said passed output
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`voltage (Vouta or Voutb) to a load circuit; and a detection circuit (Rb, R1 and R2)
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`operable to detect a magnitude of said passed output voltage and to generate a
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`detection voltage (at node A), wherein said selection circuit is controlled on the basis of
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`said control signal, selects a voltage corresponding to said passed output voltage
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`generated from among at least two of said detection voltages (at R1 and at R2) and
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`generates a selected detection voltage (positive terminal of DA) representing said
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`Application/Control Number: 12/708,915
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`Page 5
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`Art Unit: 2838
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`detection voltage selected, and said operational amplifier circuit (DA) decreases the
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`difference between said reference voltage and said selected detection voltage. (For
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`Example: Col. 3 lines 9-67 and Col. 4 Lines 1-20).
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`Regarding Claim 2, Chiu teaches on (Figure 5) that said selection circuit (OSU,
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`SW1 and SW2) generates a plurality of passed output voltages (Vouta or Voutb), said
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`second terminal does not receive one predetermined voltage of said plurality of passed
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`output voltages. (For Example: Col. 3 lines 9-67 and Col. 4 Lines 1-20).
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`Regarding Claim 3, Chiu teaches on (Figure 5) that said detection circuit (Rb,
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`R1 and R2) uses said predetermined passed output voltage as said detection voltage.
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`(For Example: Col. 3 lines 9-67 and Col. 4 Lines 1-20).
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`Regarding Claim 4, Chiu teaches on (Figure 5) that said detection circuit (Rb,
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`R1 and R2) performs detection by dividing said passed output voltage (Vouta or Voutb).
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`(For Example: Col. 3 lines 9-67 and Col. 4 Lines 1-20).
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`Regarding Claim 5, Chiu teaches on (Figure 5) that said detection circuit (Rb,
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`R1 and R2) includes two resistors ((Rb and R2) or (Rb and R1)) connected in series
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`with each other between said first terminal (at node B) and a ground terminal and
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`detects the voltage at the connection point of said two resistors. (For Example: Col. 3
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`lines 9-67 and Col. 4 Lines 1-20).
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`Claim Rejections - 35 USC § 103
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`The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all
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`obviousness rejections set forth in this Office action:
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`Application/Control Number: 12/708,915
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`Page 6
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`Art Unit: 2838
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`(a) A patent may not be obtained though the invention is not identically disclosed or described as set
`forth in section 102 of this title, if the differences between the subject matter sought to be patented and
`the prior art are such that the subject matter as a whole would have been obvious at the time the
`invention was made to a person having ordinary skill in the art to which said subject matter pertains.
`Patentability shall not be negatived by the manner in which the invention was made.
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`8.
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`Claims 6 and 7 are rejected under 35 U.S.C. 103(a) as being unpatentable
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`over Chiu (US 7,068,019) in view of Moraveji et al. (US 20050275394).
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`Regarding Claim 6, Chiu teaches on (Figure 5) the voltage supply circuit.
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`Chiu does not teach a buffer circuit that receives said passed output voltage at a
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`high impedance and outputs said passed output voltage at a low impedance, wherein
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`said second terminal receives said passed output voltage through said buffer circuit.
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`Moraveji teaches (Figure 2A) a buffer circuit (240) that receives said passed
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`output voltage (from 230) at a high impedance and outputs said passed output voltage
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`at a low impedance, wherein said second terminal (at 210) receives said passed output
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`voltage through said buffer circuit. (For Example: Paragraph 25-28)
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`It would have been obvious to one of ordinary skill in the art at the time of the
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`invention to modify the circuit of Chiu to include a buffer circuit that receives said
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`passed output voltage at a high impedance and outputs said passed output voltage at a
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`low impedance, wherein said second terminal receives said passed output voltage
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`through said buffer circuit as taught by Moraveji to prevent an unwanted offset voltage
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`from appearing on the output signal. (Moraveji, Paragraph 28)
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`Regarding Claim 7, Chiu teaches on (Figure 5) the voltage supply circuit.
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`Chiu does not teach that said detection circuit detects the magnitude of said
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`passed output voltage received through said buffer circuit.
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`Application/Control Number: 12/708,915
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`Page 7
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`Art Unit: 2838
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`Moraveji teaches (Figure 2A) that said detection circuit (210) detects the
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`magnitude of said passed output voltage received through said buffer circuit (240).
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`(For
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`Example: Paragraph 25-28)
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`It would have been obvious to one of ordinary skill in the art at the time of the
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`invention to modify the circuit of Chiu to include that said detection circuit detects the
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`magnitude of said passed output voltage received through said buffer circuit as taught
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`by Moraveji to prevent an unwanted offset voltage from appearing on the output signal.
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`(Moraveji, Paragraph 28)
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`9.
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`Claim 8 is rejected under 35 U.S.C. 103(a) as being unpatentable over Chiu
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`(US 7,068,019) in view of Moraveji et al. (US 20050275394) and Dwarakanath (US
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`4,495,472).
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`Regarding Claim 8, Chiu teaches on (Figure 5) the voltage supply circuit.
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`Chiu does not teach that said buffer circuit includes a transistor, said transistor
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`receives said passed output voltage at a control terminal of said transistor and outputs
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`the received voltage from ether one of a source terminal or an emitter terminal of said
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`transistor.
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`Dwarakanath teaches (Figure 2) that said buffer circuit (40) includes a transistor
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`(50), said transistor receives said passed output voltage (from 48) at a control terminal
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`of said transistor and outputs the received voltage from either one of a source terminal
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`or an emitter terminal of said transistor. (For Example: Col. 3 lines 34-67 and Col. 4
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`Lines 1-22).
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`Application/Control Number: 12/708,915
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`Page 8
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`Art Unit: 2838
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`It would have been obvious to one of ordinary skill in the art at the time of the
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`invention to modify the circuit of Chiu to include that said buffer circuit includes a
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`transistor, said transistor receives said passed output voltage at a control terminal of
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`said transistor and outputs the received voltage from ether one of a source terminal or
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`an emitter terminal of said transistor as taught by Dwarakanath to generated an output
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`signal that is more stable.
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`Conclusion
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`Any inquiry concerning this communication or earlier communications from the
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`examiner should be directed to GUSTAVO ROSARIO BENITEZ whose telephone
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`number is (571 )270-7888. The examiner can normally be reached on Monday thru
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`Thursday with alternate Fridays off.
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`If attempts to reach the examiner by telephone are unsuccessful, the examiner’s
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`supervisor, Monica Lewis can be reached on (571) 272-1838. The fax phone number
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`for the organization where this application or proceeding is assigned is 571 -273-8300.
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`Application/Control Number: 12/708,915
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`Page 9
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`Art Unit: 2838
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`Information regarding the status of an application may be obtained from the
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`Patent Application Information Retrieval (PAIR) system. Status information for
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`published applications may be obtained from either Private PAIR or Public PAIR.
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`Status information for unpublished applications is available through Private PAIR only.
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`For more information about the PAIR system, see http://pair-direct.uspto.gov. Should
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`you have questions on access to the Private PAIR system, contact the Electronic
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`Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a
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`USPTO Customer Service Representative or access to the automated information
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`system, call 800-786-9199 (IN USA OR CANADA) or 571 -272—1 000.
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`7/16/2012
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`/GARY L LAXTON/
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`Primary Examiner, Art Unit 2838
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`/GUSTAVO ROSARIO BENITEZ/
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`Examiner, Art Unit 2838
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`