`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria1 Virginia 22313- 1450
`wwwnsptogov
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`APPLICATION NO.
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`
`
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` F ING DATE
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`FIRST NAMED INVENTOR
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`ATTORNEY DOCKET NO.
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`
`
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`CONF {MATION NO.
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`12/942,176
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`11/09/2010
`
`Kikuo ONO
`
`1497.51198X00
`
`1168
`
`20457
`
`7590
`
`04/29/2013
`
`ANTONELLLTERRY,STOUT&KRAUS,LLP
`1300 NORTH SEVENTEENTH STREET
`SUITE 1800
`ARLINGTON, VA 22209-3873
`
`JUNGE, BRYAN R.
`
`2897
`
`MAIL DATE
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`04/29/2013
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`PAPER NUMBER
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`DELIVERY MODE
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`PAPER
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`Please find below and/or attached an Office communication concerning this application or proceeding.
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`The time period for reply, if any, is set in the attached communication.
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`PTOL—90A (Rev. 04/07)
`
`

`

`
`
`Applicant(s)
`Application No.
` 12/942,176 ONO, KIKUO
`
`Examiner
`Art Unit
`AIA (First Inventor to File)
`Office Action Summary
`
`BRYAN JUNGE its“ 2897
`
`-- The MAILING DA TE of this communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`
`
`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE 3 MONTH(S) OR THIRTY (30) DAYS,
`WHICHEVER IS LONGER, FROM THE MAILING DATE OF THIS COMMUNICATION.
`Extensions of time may be available under the provisions of 37 CFR 1.136(a).
`In no event however may a reply be timely filed
`after SIX () MONTHS from the mailing date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any
`earned patent term adjustment. See 37 CFR 1 .704(b).
`
`Status
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`1)IZI Responsive to communication(s) filed on 12 September 2012.
`El A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/were filed on
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`2b)|ZI This action is non-final.
`2a)|:l This action is FINAL.
`3)I:I An election was made by the applicant in response to a restriction requirement set forth during the interview on
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`; the restriction requirement and election have been incorporated into this action.
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`4)|:| Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
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`closed in accordance with the practice under Exparte Quay/e, 1935 CD. 11, 453 O.G. 213.
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`Disposition of Claims
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`5)IZI Claim(s) 1-12is/are pending in the application.
`5a) Of the above claim(s)
`is/are withdrawn from consideration.
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`is/are allowed.
`6)I:I Claim(s)
`7)|Z| Claim(s)_1-12 is/are rejected.
`8)|:I Claim(s)_ is/are objected to.
`
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`are subject to restriction and/or election requirement.
`9)I:I Claim((s)
`* If any claims have been determined allowable, you may be eligible to benefit from the Patent Prosecution Highway program at a
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`participating intellectual property office for the corresponding application. For more information, please see
`htt
`:/'/\W¢W.LISI>I‘.0. ovI’ atentS/init events/
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`
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`hI/index.‘s or send an inquiry to PPI-iieedback{®usgtc.00v.
`
`Application Papers
`
`10)I:l The specification is objected to by the Examiner.
`11)I:l The drawing(s) filed on
`is/are: a)I:I accepted or b)I:I objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
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`12)I:| Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
`Certified copies:
`
`a)I:l All
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`b)|:l Some * c)I:l None of the:
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`1.I:I Certified copies of the priority documents have been received.
`2.|:l Certified copies of the priority documents have been received in Application No.
`3.|:| Copies of the certified copies of the priority documents have been received in this National Stage
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`application from the International Bureau (PCT Rule 17.2(a)).
`* See the attached detailed Office action for a list of the certified copies not received.
`
`Interim copies:
`
`a)|:l All
`
`b)I:I Some
`
`c)I:I None of the:
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`Interim copies of the priority documents have been received.
`
`Attachment(s)
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`1) E Notice of References Cited (PTO-892)
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`3) D Interview Summary (PTO-413)
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`Paper N°ISI/Ma" Date' —
`PTO/SB/08
`t
`1
`St
`I
`D'
`I'
`f
`2 I] I
`)
`4) I:I Other:
`a emen (s) (
`Isc osure
`n orma Ion
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`Paper No(s)/Mai| Date
`U.S. Patent and Trademark Office
`PTOL—326 (Rev. 03-13)
`
`Part of Paper No./Mai| Date 20130419
`
`Office Action Summary
`
`

`

`Application/Control Number: 12/942,176
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`Page 2
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`Art Unit: 2897
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`DETAILED ACTION
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`1.
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`A request for continued examination under 37 CFR 1.114, including the fee set forth in
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`37 CFR 1.17(e), was filed in this application after final rejection. Since this application is
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`eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e)
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`has been timely paid, the finality of the previous Office action has been Withdrawn pursuant to
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`37 CFR 1.114. Applicant's submission filed on 09/12/2012 has been entered.
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`Response to Arguments
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`2.
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`Applicant's arguments have been fully considered but they are not persuasive. Applicant
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`argued Jeoung discloses the patterning of the conductive layer and the forming of the opening in
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`the insulating layer occur at the same time in one etching step and therefore does not teach first
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`and second etching steps.
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`The claim states in part ‘patterning the first transparent conductive film by a first etching’
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`and “forming a penetration hole...by a second etching.’ The broadest reasonable interpretation of
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`these limitations includes that portion of an etching process that patterns a conductive layer to be
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`considered as a 'first’ etching step and that portion that forms the penetrating hole to be
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`considered as a ‘second' etching step. Thus, Jeoung, as previously applied, and Seo, see below,
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`teach first and second etching steps for this reason. Jeoung and Seo further teach performing
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`such etching steps using the same layer of photoresist. Thus, the teachings of Jeoung, and now
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`Seo, in combination with the other references render the first and second etching steps obvious.
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`

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`Application/Control Number: 12/942,176
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`Page 3
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`Art Unit: 2897
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`Claim Rejections - 35 USC § 103
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`3.
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`The following is a quotation of 35 USC. 103(a) which forms the basis for all
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`obviousness rejections set forth in this Office action:
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`(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in
`section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are
`such that the subject matter as a whole would have been obvious at the time the invention was made to a person
`having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the
`manner in which the invention was made.
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`4.
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`Claims 1, 2, 11, and 12 are rejected under 35 USC. 103(a) as being unpatentable over
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`Lee et al. (US 2009/0268134) in view of Horiguchi et al. (US 2008/0180622) and Seo et al. (US
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`2005/0230684).
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`In reference to claim 1, Lee et al. (US 2009/0268134), hereafter “Lee,” discloses a
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`method of making a liquid crystal display device including forming a first conductive film, 124
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`in Figure 6, the first conductive film having a portion for a gate electrode of a thin film transistor
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`in a display region, paragraph 69, forming a gate insulating film, 140 in Figure 8, on the first
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`conductive film, forming a semiconductor layer 154, 164 of the thin film transistor on the gate
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`insulating film, paragraph 109, forming a second conductive film on the semiconductor layer, the
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`second conductive film having portions for a drain electrode 175 and a source electrode 173 of
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`the thin film transistor, paragraph 110, forming a first insulating film, 180p in Figure 12A, so as
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`to cover the thin film transistor, forming a second insulating film 230 on the first insulating film,
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`paragraph 112, forming a first transparent conductive film, 270 in Figure 14A, on the second
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`insulating film, forming an etching resist which is patterned by a photolithography process on the
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`first transparent conductive film, forming a common electrode by patterning the first transparent
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`conductive film by a first etching using the etching resist, paragraph 113, forming a penetration
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`hole, 235 in Figure 12A, in the second insulating film in the display region at a position above
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`

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`Application/Control Number: 12/942,176
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`Page 4
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`Art Unit: 2897
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`the second conductive film by a second etching, paragraph 112, removing the etching resist,
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`forming a third insulating film, 180q in Figure 16, on the common electrode and an inside of the
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`penetration hole, etching the third insulating film and the first insulating film so as to expose a
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`portion of the second conductive film inside the penetration hole, Figure 16 and paragraph 114,
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`forming a second transparent conductive film, 191 in Figure 2, on the portion of the second
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`conductive film exposed from the penetration hole and on the third insulating film and etching
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`the second transparent conductive film to form a pixel electrode, Figure 2 and paragraph 115.
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`Lee does not disclose both patterning the transparent conductive film by a first etching
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`using the etching resist and forming the penetration hole by a second etching using the (same)
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`etching resist applied to a surface of the second insulating film exposed from the first transparent
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`electrode after performing the first etching to form the common electrode using the etching
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`resist, or removing the etching resist.
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`Horiguchi discloses a method of making a liquid crystal display device including
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`teaching forming a common electrode 22b in Figure 8A by patterning a first transparent
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`conductive film by a first etching using a resist, paragraph 71, and after performing the first
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`etching to form the common electrode, forming a penetration hole in an insulating film 18 in the
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`display region by a second etching which is applied to a surface of the insulating film exposed
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`from the common electrode, paragraph 72. It would have been obvious to one of ordinary skill in
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`the art at the time of the invention to pattern the transparent conductive film by a first etching
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`using the etching resist and forming the penetration hole by a second etching applied to a surface
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`of the second insulating film exposed from the first transparent electrode after performing the
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`first etching to form the common electrode. One would have been motivated to do so in order to
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`Application/Control Number: 12/942,176
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`Page 5
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`Art Unit: 2897
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`simplify depositing and removing the transparent conductive film by avoiding depositing and
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`etching the film within the penetration hole.
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`Lee in view of Horiguchi does not disclose both patterning the transparent conductive
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`film by a first etching using the etching resist and forming the penetration hole by a second
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`etching using the (same) etching resist.
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`Seo et al. (US 2005/0230684), hereafter “Seo,” discloses a display device including
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`teaching etching both a conductive film, 60 in Figure 3A, by a first etching using the etching
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`resist 90 and forming a penetration hole 59—1 by a second etching using the (same) etching resist
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`and removing the resist, paragraphs 40—43. It would have been obvious to one of ordinary skill
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`in the art at the time of the invention to form the common electrode by patterning the first
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`transparent conductive film by a first etching using the etching resist and form the penetration
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`hole in the second insulating film by a second etching using the etching resist and to remove the
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`etching resist. One would have been motivated to do so in order to simplify manufacturing by
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`reducing the number of lithography steps.
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`In reference to claim 2, Lee discloses the first insulating film is mainly composed of
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`inorganic material, and the second insulating film is mainly composed of organic material,
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`paragraph 112.
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`In reference to claim ll, Lee discloses the first conductive film has a portion 129 in a
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`terminal region for a terminal to input a signal to the gate electrode, paragraph 69, the step of
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`forming the penetration hole in the second insulating film includes removing the second
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`insulating film in the terminal region, implied by Figure 12B and paragraph 112, the step of
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`forming the third insulating film 180q includes forming the third insulating film on the first
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`

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`Application/Control Number: 12/942,176
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`Page 6
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`Art Unit: 2897
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`insulating film 180p in the terminal region, Figure 16B and paragraph 114, the step of etching
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`the third insulating film and the first insulating film includes forming an opening, 181 in Figure
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`16B, in the third insulating film 180q, the first insulating film 180p and the gate insulting film
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`140 in the terminal region, the step of forming the second transparent conductive film includes
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`forming the second transparent conductive film on the portion of the first conductive film
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`exposed from the opening in the terminal region, and the step of etching the second transparent
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`conductive film includes etching the second transparent conductive film to form a terminal
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`electrode, 81 in Figure 3, in the terminal region, paragraph 115.
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`In reference to claim 12, Lee discloses the second conductive film has a portion 179 in a
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`terminal region for a terminal to input a signal to the drain electrode, paragraph 78, the step of
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`forming the penetration hole in the second insulating film includes removing the second
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`insulating film in the terminal region, implied by Figure 12B and paragraph 112, the step of
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`forming the third insulating film 180q includes forming the third insulating film on the first
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`insulating film 180p in the terminal region, Figure 16B and paragraph 114, the step of etching
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`the third insulating film and the first insulating film includes forming an opening, 182 in Figure
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`16B, in the third insulating film 180q and the first insulating film 180p in the terminal region, the
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`step of forming the second transparent conductive film includes forming the second transparent
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`conductive film on the portion of the second conductive film exposed from the opening in the
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`terminal region, and the step of etching the second transparent conductive film includes etching
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`the second transparent conductive film to form a terminal electrode, 82 in Figure 3, in the
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`terminal region, paragraph 115.
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`

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`Application/Control Number: 12/942,176
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`Page 7
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`Art Unit: 2897
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`Of note, Lee literally discloses the second conductive film has a portion 179 in a terminal
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`region for a terminal to input a signal to the source electrode, paragraph 78. However, in this
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`instance what is designated the ‘source’ is functionally the same as what applicant designates the
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`‘drain.’ It would be apparent to one of ordinary skill in the art that the respective disclosures are
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`obvious variants of one another if not the same structure, labeled differently. Lee discloses in
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`general, a gate line for transferring a gate signal or a scanning signal, a data line for transferring
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`an image signal or a data signal, a pixel electrode for receiving the image signal, and a thin film
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`transistor for controlling the image signal that is transferred to a pixel electrode of each pixel are
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`formed in a display panel. Connecting the data line to the ‘source’ and the pixel electrode to the
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`‘drain’ or the opposite is an arbitrary designation.
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`5.
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`Claims 3—6, 8 and 10 are rejected under 35 U.S.C. 103(a) as being unpatentable over Lee
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`et al. (US 2009/0268134) in view of Horiguchi et al. (US 2008/0180622) and Seo et al. (US
`
`2005/0230684) as applied to claims 1 and 2 above and further in view of Lim et al. (US
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`2008/0169470).
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`In reference to claims 3 and 4, Lee discloses the amount of etching on the second
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`insulating film, 230 in Figure 12A, is larger than the amount of etching on the first insulating
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`film 180p and wherein the second etching stops before the first insulating film is penetrated, see
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`Figure 12A.
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`Lee in view of Horiguchi and Seo is silent regarding the second etching being selective.
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`Lim et al. (US 2008/0169470), hereafter “Lim,” discloses a method of making a thin film
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`transistor device including etching a second insulating film, 118 in Figure 5E, by a selective etch
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`

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`Application/Control Number: 12/942,176
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`Page 8
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`Art Unit: 2897
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`where the amount of etching on the second insulating film 118 is larger than the amount of
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`etching on the first insulating film 116 and wherein the etching stops before the first insulating
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`film is penetrated, paragraph 63. It would have been obvious to one of ordinary skill in the art at
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`the time of the invention to etch the second insulating film selectively with respect to the first
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`insulating film as taught by Lim. One would have been motivated to do so in order to control the
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`etch depth by utilizing the first insulator as an etch stop layer.
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`In reference to claims 5 and 6, Lee discloses after the step of removing the etching resist,
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`forming the third insulating film, 185 in Figure 16A, on the common electrode, an inner side of
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`the penetration hole, and a surface of the first insulating film exposed to the inner side of the
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`penetration hole (inherent in 'coated to have a uniform thickness,’ paragraph 114), etching the
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`third insulating film and the first insulating film on the inner side of the penetration hole so as to
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`expose one of the drain electrode and the source electrode, paragraph 114, and forming a second
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`transparent electrode, 191 in Figure 2, on a portion of one of the drain electrode and the source
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`electrode 175 exposed from the penetration hole and on the third insulating film, paragraph 115.
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`In reference to claims 8 and 10, Lee in view of Horiguchi and Seo does not disclose the
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`second etching is ashing.
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`Lim discloses etching the second insulating layer, 118 in Figure 5E, by ashing, paragraph
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`63. It would have been obvious to one of ordinary skill in the art at the time of the invention to
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`carry out the second etching by ashing. One would have been motivated to do so in order to
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`selectively etch the second insulating layer relative to the first insulating layer, id.
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`

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`Application/Control Number: l2/942,l76
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`Page 9
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`Art Unit: 2897
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`6.
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`Claims 7 and 9 are rejected under 35 U.S.C. 103(a) as being unpatentable over Lee et al.
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`(US 2009/0268l34) in view of Horiguchi et al. (US 2008/0180622) and Seo et al. (US
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`2005/0230684) as applied to claims 1 and 2 above and further in view of Zhang (US 6,855,954).
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`In reference to claim 7 and 9, Lee in view of Horiguchi and Seo is silent regarding the
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`first etching is wet etching.
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`Zhang (US 6,855,954), hereafter “Zhang,” discloses a method of patterning a transparent
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`conductive layer including wet etching, col. 9 lines 12—15. It would have been obvious to one of
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`ordinary skill in the art at the time of the invention to carry out the first etch by wet etching. One
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`would have been motivated to do so in order to pattern an indium tin oxide (ITO) transparent
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`conductive layer.
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`Conclusion
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`7.
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`Any inquiry concerning this communication or earlier communications from the
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`examiner should be directed to BRYAN JUNGE whose telephone number is (57 l)270—57 17.
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`The examiner can normally be reached on Monday—Thursday 9:00AM to 5:00PM.
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`If attempts to reach the examiner by telephone are unsuccessful, the examiner’s
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`supervisor, Fernando Toledo can be reached on (571)272—1867. The fax phone number for the
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`organization where this application or proceeding is assigned is 571—273—8300.
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`

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`Application/Control Number: 12/942,176
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`Page 10
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`Art Unit: 2897
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`Information regarding the status of an application may be obtained from the Patent
`
`Application Information Retrieval (PAIR) system. Status information for published applications
`
`may be obtained from either Private PAIR or Public PAIR. Status information for unpublished
`
`applications is available through Private PAIR only. For more information about the PAIR
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`system, see http://pair—direct.uspto.gov. Should you have questions on access to the Private PAIR
`
`system, contact the Electronic Business Center (EBC) at 866—217—9197 (toll—free). If you would
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`information system, call 800—786—9199 (IN USA OR CANADA) or 571—272—1000.
`
`/Fernando L. Toledo/
`
`Supervisory Patent Examiner, Art Unit
`2897
`
`/Bryan R. Junge/
`Examiner, Art Unit 2897
`
`