`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria1 Virginia 22313- 1450
`www.uspto.gov
`
`APPLICATION NO.
`
`
`
`
`
` F ING DATE
`
`FIRST NAMED INVENTOR
`
`ATTORNEY DOCKET NO.
`
`
`
`
`
`CONF {MATION NO.
`
`13/377,212
`
`12/09/2011
`
`Hiroshi Kagata
`
`MAT—10513US
`
`2078
`
`EXAMINER
`RATNERPRESTIA —
`””0”“ —
`7590
`52473
`PO. BOX 980
`RAMASWAMY, ARUN
`VALLEY FORGE, PA 19482-0980
`
`PAPER NUMBER
`
`ART UNIT
`
`2848
`
`
`
`
`NOT *ICATION DATE
`
`DELIVERY MODE
`
`12/20/2013
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above—indicated "Notification Date" to the
`following e—mail address(es):
`
`ptocorrespondence @ratnerprestia.c0m
`
`PTOL—90A (Rev. 04/07)
`
`

`

`
`
`Applicant(s)
`Application No.
` 13/377,212 KAGATA ET AL.
`
`Examiner
`Art Unit
`AIA (First Inventor to File)
`Office Action Summary
`
`ARUN RAMASWAMY [SENS 2848
`
`-- The MAILING DA TE of this communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE g MONTHS FROM THE MAILING DATE OF
`THIS COMMUNICATION.
`Extensions of time may be available under the provisions of 37 CFR1. 136( a).
`after SIX () MONTHS from the mailing date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any
`earned patent term adjustment. See 37 CFR 1 .704(b).
`
`In no event, however, may a reply be timely filed
`
`Status
`
`1)IZI Responsive to communication(s) filed on 9 December 2011.
`El A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/were filed on
`
`2b)|ZI This action is non-final.
`2a)|:l This action is FINAL.
`3)I:I An election was made by the applicant in response to a restriction requirement set forth during the interview on
`
`; the restriction requirement and election have been incorporated into this action.
`
`4)|:| Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`
`closed in accordance with the practice under Exparte Quay/e, 1935 CD. 11, 453 O.G. 213.
`
`Disposition of Claims*
`
`5)IZI Claim(s) 1-51 is/are pending in the application.
`
`5a) Of the above claim(s) 4-6 16 1726-42 44 45 47 48 50 and 51 is/are withdrawn from consideration.
`
`6)I:I Claim(s)
`is/are allowed.
`
`7)|:| Claim(s) 1 -3 7- 15 18-25 43 46 and 49 is/are rejected.
`8)|:I Claim(s)_ is/are objected to.
`
`
`are subject to restriction and/or election requirement.
`9)I:I Claim((s)
`* If any claims have been determined allowable, you may be eligible to benefit from the Patent Prosecution Highway program at a
`
`participating intellectual property office for the corresponding application. For more information, please see
`hit
`:/'/\WIIW.LIsnto. ov/ atentS/init events/
`
`
`
`hilndex.‘s or send an inquiry to PPI-iieedback{®usgtc.00v.
`
`Application Papers
`
`10)I:l The specification is objected to by the Examiner.
`11)I:l The drawing(s) filed on
`is/are: a)I:I accepted or b)I:I objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`
`12)IXI Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
`Certified copies:
`
`a)IZl All
`
`b)|:l Some” c)I:l None of the:
`
`1.IXI Certified copies of the priority documents have been received.
`2.|:l Certified copies of the priority documents have been received in Application No.
`3.|:| Copies of the certified copies of the priority documents have been received in this National Stage
`
`application from the International Bureau (PCT Rule 17.2(a)).
`** See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`
`
`3) D Interview Summary (PTO-413)
`1) E Notice of References Cited (PTO-892)
`Paper No(s)/Mai| Date.
`.
`.
`4) I:I Other'
`2) E InformatIon DIsclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`Paper No(s)/Mai| Date 12/9/2011.
`US. Patent and Trademark Office
`PTOL—326 (Rev. 11-13)
`
`Office Action Summary
`
`Part of Paper No./Mai| Date 20131127
`
`

`

`Application/Control Number: 13/377,212
`
`Page 2
`
`Art Unit: 2848
`
`DETAILED ACTION
`
`1.
`
`The present application is being examined under the pre-AIA first to invent
`
`provisions.
`
`Claim Rejections - 35 USC § 103
`
`2.
`
`The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis
`
`for all obviousness rejections set forth in this Office action:
`
`(a) A patent may not be obtained though the invention is not identically disclosed or described
`as set forth in section 102 of this title, if the differences between the subject matter sought to
`be patented and the prior art are such that the subject matter as a whole would have been
`obvious at the time the invention was made to a person having ordinary skill in the art to which
`said subject matter pertains. Patentability shall not be negatived by the manner in which the
`invention was made.
`
`3.
`
`Claims 1-3, 7, 13-15, 23-25, 43, 46, and 49 are rejected under pre-AIA 35
`
`U.S.C. 103(a) as being unpatentable over Mochizuki et al. (US Patent 4,555,746) in
`
`view of Govindarajan (US Publication 2006/0151823).
`
`In re claim 1, Mochizuki discloses a capacitor comprising:
`
`a substrate (1- Figure 3, col.2 l.61) made of an organic film (col.1 ll.49-52);
`
`a first conductive layer (2' - Figure 3, col.2 l.65) provided on an upper surface of
`
`the substrate (Figure 3);
`
`a first dielectric layer (4' - Figure 3, col.2 L67) provided on an upper surface of the
`
`first conductive layer (Figure 3);
`
`a second dielectric layer (5 — Figure 3, col.3 l.2) provided on an upper surface of
`
`the first dielectric layer (4' - Figure 3); and
`
`

`

`Application/Control Number: 13/377,212
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`Page 3
`
`Art Unit: 2848
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`a second conductive layer (3 — Figure 3, col.2 l.65) provided on an upper surface
`
`of the second dielectric layer (5 — Figure 3).
`
`Mochizuki does not disclose the first dielectric layer having a thickness not less
`
`than 0.3 nm and not greater than 50 nm,
`
`the second dielectric layer having a thickness not less than 0.3 nm and not
`
`greater than 50 nm,
`
`the first dielectric layer is made of a plurality of metal oxide chips spread over on
`
`the upper surface of the first conductive layer, and
`
`wherein the second dielectric layer is made of a plurality of metal oxide chips
`
`spread over on a lower surface of the second conductive layer.
`
`Govindarajan discloses a first dielectric layer having a thickness not less than 0.3
`
`nm and not greater than 50 nm (1140-45, Figure 2, Figure 3),
`
`a second dielectric layer having a thickness not less than 0.3 nm and not greater
`
`than 50 nm (1140-45, Figure 2, Figure 3),
`
`the first dielectric layer is made of a plurality of metal oxide chips (1140-45) spread
`
`over on the upper surface of a conductive layer (14 — Figure 2, 1140) , and
`
`wherein the second dielectric layer is made of a plurality of metal oxide chips
`
`(1140-45) spread over on a lower surface of a second conductive layer (18 - Figure 2,
`
`1144).
`
`It would have been obvious to one having ordinary skill in the art at the time of
`
`the invention to incorporate the dielectric structure of Govindarajan into the invention of
`
`Mochizuki to create a component with high capacitor to store charge and a low leakage.
`
`

`

`Application/Control Number: 13/377,212
`
`Page 4
`
`Art Unit: 2848
`
`In re claim 2, Mochizuki in view of Govindarajan discloses the capacitor
`
`according to claim 1, as explained above. Mochizuki further discloses the upper surface
`
`of the substrate (1’ — Figure 3) has a first non-conductive-layer portion at an end of the
`
`upper surface of the substrate in a first direction (Figure 3),
`
`wherein the first conductive layer (2’ — Figure 3)
`
`is provided on the upper surface
`
`of the substrate (1’ — Figure 3) except the first non-conductive-layer portion (Figure 3),
`
`wherein the upper surface of the second dielectric layer (5 - Figure 3) has a
`
`second non-conductive-layer portion at an end of the upper surface of the second
`
`dielectric layer in a second direction opposite to the first direction (Figure 3),
`
`wherein the second conductive layer (3 — Figure 3) is provided on the upper
`
`surface of the second dielectric layer (5 — Figure 3) except the second non-conductive-
`
`layer portion (Figure 3),
`
`wherein the upper surface of the first conductive layer (2’- Figure 3)has a first
`
`non-dielectric-layer portion at an end of the upper surface of the first conductive layer in
`
`the second direction (Figure 3), and
`
`wherein the first dielectric layer (4' - Figure 3) is provided on the upper surface of
`
`the first conductive layer (2’ — Figure 3) except the first non-dielectric-layer portion
`
`(Figure 3).
`
`In re claim 3, Mochizuki in view of Govindarajan discloses the capacitor
`
`according to claim 2, as explained above. Mochizuki further discloses the upper surface
`
`of the substrate (1’ — Figure 3) has a second non-dielectric-layer portion at an end of the
`
`upper surface of the substrate (Figure 3), and
`
`

`

`Application/Control Number: 13/377,212
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`Page 5
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`Art Unit: 2848
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`wherein the first dielectric layer (4’ — Figure 3) is provided on the upper surface of
`
`the substrate (1’ — Figure 3) at an end of the upper surface of the substrate in the first
`
`direction except the second non-dielectric-layer portion (Figure 3).
`
`In re claim 7, Mochizuki in view of Govindarajan discloses the capacitor
`
`according to claim 1, as explained above. Mochizuki does not disclose the relative
`
`dielectric constants of the first dielectric layer and the second dielectric layer are not
`
`lower than 30.
`
`Govindarajan discloses the relative dielectric constants of the first dielectric layer
`
`and the second dielectric layer are not lower than 30 (117, 1126). When using a dielectric
`
`structure of greater than 2 laminations, at least two dielectrics will have a dielectric
`
`constant greater than 30.
`
`
`
`Figure 3 with Examiner’s Comments (Figure 3EC)
`
`

`

`Application/Control Number: 13/377,212
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`Page 6
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`Art Unit: 2848
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`In re claim 13, Mochizuki in view of Govindarajan discloses the capacitor
`
`according to claim 1, as explained above. Mochizuki further discloses an insulation
`
`coating layer (IC — Figure 3EC, co|.1 “49-52) that at least partially covers at least one of
`
`the upper surface and a lower surface of the substrate (1’ — Figure 3EC).
`
`In re claim 14, Mochizuki discloses a method of manufacturing a capacitor,
`
`comprising:
`
`providing a first conductive layer (2’ — Figure 3) on an upper surface of a first
`
`substrate (1’ — Figure 3) made of an organic film;
`
`preparing a first unit by providing a first dielectric layer (4’ - Figure 3) on an upper
`
`surface of the first conductive layer after said providing of the first conductive layer;
`
`providing a second conductive layer (3 — Figure 3) on a lower surface of a
`
`second substrate (1 — Figure 3) made of an organic film;
`
`preparing a second unit by providing a second dielectric layer (5 — Figure 3) on a
`
`lower surface of the second conductive layer (3 — Figure 3) after said providing of the
`
`second conductive layer (3 — Figure 3); and
`
`overlaying the first unit and the second unit such that the first conductive layer (2'
`
`Figure 3) and the second conductive layer (3 — Figure 3) face each other across the first
`
`dielectric layer (4’ — Figure 3) and the second dielectric layer (5 — Figure 3),
`
`Mochizuki does not disclose the first dielectric layer having a thickness not less
`
`than 0.3 nm and not greater than 50 nm,
`
`

`

`Application/Control Number: 13/377,212
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`Page 7
`
`Art Unit: 2848
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`the second dielectric layer having a thickness not less than 0.3 nm and not
`
`greater than 50 nm,
`
`wherein the first dielectric layer is made of a plurality of metal oxide chips spread
`
`over on the upper surface of a first conductive layer; and
`
`wherein the second dielectric layer is made of a plurality of metal oxide chips
`
`spread over on the lower surface of a second conductive layer.
`
`Govindarajan discloses a first dielectric layer having a thickness not less than 0.3
`
`nm and not greater than 50 nm (1140-45, Figure 2, Figure 3),
`
`a second dielectric layer having a thickness not less than 0.3 nm and not greater
`
`than 50 nm (1140-45, Figure 2, Figure 3),
`
`wherein the first dielectric layer is made of a plurality of metal oxide chips spread
`
`over on the upper surface of a first conductive layer (18 — Figure 2) (1140-45);
`
`and wherein the second dielectric layer is made of a plurality of metal oxide chips
`
`spread over on the lower surface of a second conductive layer (18 - Figure 2) (1140 -45).
`
`It would have been obvious to one having ordinary skill in the art at the time of
`
`the invention to incorporate the dielectric structure of Govindarajan into the invention of
`
`Mochizuki to create a component with high capacitor to store charge and a low leakage.
`
`In re claim 15, Mochizuki discloses a method of manufacturing a capacitor,
`
`comprising:
`
`preparing a first unit, said preparing of the first unit comprising
`
`providing a first conductive layer (2 — Figure 3) on an upper surface of a first
`
`substrate (1 — Figure 3) made of an organic film,
`
`

`

`Application/Control Number: 13/377,212
`
`Page 8
`
`Art Unit: 2848
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`providing a first dielectric layer (4 — Figure 3) on an upper surface of the first
`
`conductive layer (2 — Figure 3) after said providing of the first conductive layer,
`
`providing a second conductive layer (3 — Figure 3) on a lower surface of the first
`
`substrate (1 — Figure 3), and
`
`providing a second dielectric layer (5 — Figure 3) on a lower surface of the
`
`second conductive layer (3 - Figure 3) after said providing of the second conductive
`
`layer;
`
`preparing a second unit, said preparing of the second unit comprising
`
`providing a third conductive layer (3’ - Figure 3) on an upper surface of a second
`
`substrate (1’ — Figure 3) made of an organic film,
`
`providing a third dielectric layer (5’ — Figure 3) on an upper surface of the third
`
`conductive layer (3’ — Figure 3) after said providing of the third conductive layer,
`
`providing a fourth conductive layer (2’ - Figure 3) on a lower surface of the
`
`second substrate (1’ — Figure 3), and
`
`providing a fourth dielectric layer (4' - Figure 3) on a lower surface of the fourth
`
`conductive layer (2’ — Figure 3) after said providing of the fourth conductive layer; and
`
`overlaying the first unit and the second unit such that the second conductive
`
`layer (3 — Figure 3) and the fourth conductive layer (2’ — Figure 3) face each other
`
`across the second dielectric layer (5 — Figure 3) and the fourth dielectric layer (4’ —
`
`Figure 3),
`
`

`

`Application/Control Number: 13/377,212
`
`Page 9
`
`Art Unit: 2848
`
`Mochizuki does not disclose a thickness of each of the first dielectric layer, the
`
`second dielectric layer, the third dielectric layer, and the fourth dielectric layer is not less
`
`than 0.3 nm and not greater than 50 nm,
`
`wherein the first dielectric layer is made of a plurality of metal oxide chips spread
`
`over on the upper surface of the first conductive layer;
`
`wherein the second dielectric layer is made of a plurality of metal oxide chips
`
`spread over on the lower surface of the second conductive layer;
`
`wherein the third dielectric layer is made of a plurality of metal oxide chips spread
`
`over on the upper surface of the third conductive layer; and
`
`wherein the fourth dielectric layer is made of a plurality of metal oxide chips
`
`spread over on the lower surface of the fourth conductive layer.
`
`Govindarajan discloses a multilayer laminated dielectric structure wherein each
`
`dielectric layer is not less than 0.3 nm and not greater than 50 nm (1140-45),
`
`wherein each dielectric layer is made of a plurality of metal oxide chips (1140-45,
`
`Figure 2, Figure 3);
`
`It would have been obvious to one having ordinary skill in the art at the time of
`
`the invention was made to incorporate the laminated dielectric structure of Govindarajan
`
`as the laminated dielectric structure in the capacitor of Mochizuki to create a component
`
`with high capacitor to store charge and a low leakage.
`
`In re claim 23, Mochizuki in view of Govindarajan discloses the method
`
`according to claim 14, as explained above. Mochizuki further discloses the first
`
`substrate (1’ — Figure 3EC) includes an insulation coating layer (IC — Figure 3EC)
`
`

`

`Application/Control Number: 13/377,212
`
`Page 10
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`Art Unit: 2848
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`provided at least partially on a surface of at least one of the upper surface and a lower
`
`surface of the first dielectric layer (4’ — Figure 3EC).
`
`In re claim 24, Mochizuki in view of Govindarajan discloses the method
`
`according to claim 14, as explained above. Mochizuki further discloses an insulation
`
`coating layer (IC — Figure 3EC) covers at least a part of a surface of at least one of the
`
`first conductive layer (2’ — Figure 3EC) and the second conductive layer (3 — Figure 3).
`
`In re claim 25, Mochizuki in view of Govindarajan discloses the method
`
`according to claim 14, as explained above. Mochizuki further discloses an insulation
`
`coating layer (IC — Figure 30) covers at least a part of a surface of the first dielectric
`
`layer (4' - Figure 3EC).
`
`In re claim 43, Mochizuki discloses the method according to claim 15, as
`
`explained above. Mochizuki further discloses the first substrate(1 — Figure 3EC)
`
`includes an insulation coating layer (IC — Figure 3EC) provided at least partially on a
`
`surface of at least one of the upper surface and a lower surface of the first dielectric
`
`layer (4 — Figure 3EC).
`
`In re claim 46, Mochizuki discloses the method according to claim 15, as
`
`explained above. Mochizuki further discloses an insulation coating layer (IC - Figure
`
`3EC) covers at least a part of a surface of at least one of the first conductive layer (2 —
`
`Figure 3EC) and the second conductive layer (3 — Figure 3EC).
`
`In re claim 49, Mochizuki discloses the method according to claim 15, as
`
`explained above. Mochizuki further discloses an insulation coating layer (IC - Figure
`
`3EC) covers at least a part of a surface of the first dielectric layer (4 — Figure 3EC).
`
`

`

`Application/Control Number: 13/377,212
`
`Page 11
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`Art Unit: 2848
`
`4.
`
`Claims 8 and 18 are rejected under pre-AIA 35 U.S.C. 103(a) as being
`
`unpatentable over Mochizuki et al. (US Patent 4,555,746) in view of Govindarajan
`
`(US Publication 2006/0151823) as applied to claims 1 and 15 above, and further in
`
`view of Maeda eta l. (J P09283389A).
`
`In re claim 8, Mochizuki in view of Govindarajan discloses the capacitor
`
`according to claim 1, as explained above. Mochizuki in view of Govindarajan does not
`
`disclose at least one of the first conductive layer and the second conductive layer is
`
`partly or entirely made of conductive polymer.
`
`Maeda discloses a conductive layer of a capacitor partly or entirely made of
`
`conductive polymer.
`
`It would have been obvious to one having ordinary skill in the art at the time the
`
`invention was made to incorporate a well-known material having high conductivity into
`
`the electronic device of Mochizuki and Govindarajan.
`
`In re claim 18, Mochizuki discloses the capacitor according to claim 15, as
`
`explained above. Mochizuki in view of Govindarajan does not disclose at least one of
`
`the first conductive layer, the second conductive layer, the third conductive layer, and
`
`the fourth conductive layer contains conductive polymer.
`
`Maeda discloses a conductive layer of a capacitor partly or entirely made of
`
`conductive polymer.
`
`It would have been obvious to one having ordinary skill in the art at the time the
`
`invention was made to incorporate a well-known material having high conductivity into
`
`the electronic device of Mochizuki and Govindarajan.
`
`

`

`Application/Control Number: 13/377,212
`
`Page 12
`
`Art Unit: 2848
`
`5.
`
`Claims 9-12 and 19-22 are rejected under pre-AIA 35 U.S.C. 103(a) as being
`
`unpatentable over Mochizuki et al. (US Patent 4,555,746) in view of Govindarajan
`
`(US Publication 2006/0151823) as applied to claims 1 and 15 above, and further in
`
`view of Nishimura et al. (JP2008277724A).
`
`In re claim 9, Mochizuki in view of Govindarajan discloses the capacitor
`
`according to claim 1, as explained above. Mochizuki in view of Govindarajan does not
`
`disclose a surface of at least one of the first conductive layer and the second conductive
`
`layer has a rough portion.
`
`Nishimura discloses roughening a surface of a conductive layer that is in contact
`
`with a dielectric (1118-19).
`
`It would have been obvious to one having ordinary skill in the art to incorporate
`
`the concept of roughening a surface as disclosed by Nishimura, to increase the surface
`
`area and adhesion between the conductive layer and the dielectric layer.
`
`In re claim 10, Mochizuki in view of Govindarajan and in further view of
`
`Nishimura discloses the capacitor according to claim 9, as explained above. Mochizuki
`
`in view of Govindarajan and in further view of Nishimura does not disclose a hardness
`
`of the first conductive layer is different from a hardness of the second conductive layer.
`
`However, It would have been obvious to one having ordinary skill in the art at the time
`
`the invention was made to choose a conductive material with desired properties such as
`
`hardness, since it has been held to be within the general skill of a worker in the art to
`
`select a known material on the basis of its suitability for the intended use as a matter of
`
`obvious design choice.
`
`In re Leshin, 125 USPQ 416.
`
`

`

`Application/Control Number: 13/377,212
`
`Page 13
`
`Art Unit: 2848
`
`In re claim 11, Mochizuki in view of Govindarajan discloses the capacitor
`
`according to claim 1, as explained above. Mochizuki in view of Govindarajan does not
`
`disclose a surface of the substrate has a rough portion.
`
`Nishimura discloses roughening a surface that is in contact with a dielectric (1118-
`
`19).
`
`It would have been obvious to one having ordinary skill in the art to incorporate
`
`the concept of roughening a surface as disclosed by Nishimura, to increase the surface
`
`area of a substrate and adhesion to a dielectric layer.
`
`In re claim 12, Mochizuki in view of Govindarajan and in further view of
`
`Nishimura discloses the capacitor according to claim 11, as explained above. Mochizuki
`
`in view of Govindarajan and in further view of Nishimura does not disclose a hardness
`
`of the first conductive layer is different from a hardness of the second conductive layer.
`
`However, It would have been obvious to one having ordinary skill in the art at the time
`
`the invention was made to choose a conductive material with desired properties such as
`
`hardness, since it has been held to be within the general skill of a worker in the art to
`
`select a known material on the basis of its suitability for the intended use as a matter of
`
`obvious design choice.
`
`In re Leshin, 125 USPQ 416.
`
`In re claim 19, Mochizuki in view of Govindarajan discloses the capacitor
`
`according to claim 15, as explained above. Mochizuki in view of Govindarajan does not
`
`disclose a surface of at least one of the first conductive layer, the second conductive
`
`layer, the third conductive layer, and the fourth conductive layer has a rough portion.
`
`

`

`Application/Control Number: 13/377,212
`
`Page 14
`
`Art Unit: 2848
`
`Nishimura discloses roughening a surface of a conductive layer that is in contact
`
`with a dielectric (1118-19).
`
`It would have been obvious to one having ordinary skill in the art to incorporate
`
`the concept of roughening a surface as disclosed by Nishimura, to increase the surface
`
`area and adhesion between the conductive layer and the dielectric layer.
`
`In re claim 20, Mochizuki in view of Govindarajan and in further view of
`
`Nishimura discloses the capacitor according to claim 19, as explained above. Mochizuki
`
`in view of Govindarajan and in further view of Nishimura does not disclose a hardness
`
`of the first conductive layer is different from a hardness of the second conductive layer.
`
`However, It would have been obvious to one having ordinary skill in the art at the time
`
`the invention was made to choose a conductive material with desired properties such as
`
`hardness, since it has been held to be within the general skill of a worker in the art to
`
`select a known material on the basis of its suitability for the intended use as a matter of
`
`obvious design choice.
`
`In re Leshin, 125 USPQ 416.
`
`In re claim 21, Mochizuki in view of Govindarajan discloses the capacitor
`
`according to claim 15, as explained above. Mochizuki in view of Govindarajan does not
`
`disclose a surface of the first substrate has a rough portion.
`
`Nishimura discloses roughening a surface that is in contact with a dielectric (1118-
`
`19).
`
`It would have been obvious to one having ordinary skill in the art to incorporate
`
`the concept of roughening a surface as disclosed by Nishimura, to increase the surface
`
`area of a substrate and adhesion to a dielectric layer.
`
`

`

`Application/Control Number: 13/377,212
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`Page 15
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`Art Unit: 2848
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`In re claim 22, Mochizuki in view of Govindarajan and in further view of
`
`Nishimura discloses the capacitor according to claim 21, as explained above. Mochizuki
`
`in view of Govindarajan and in further view of Nishimura does not disclose a hardness
`
`of the first conductive layer is different from a hardness of the second conductive layer.
`
`However, It would have been obvious to one having ordinary skill in the art at the time
`
`the invention was made to choose a conductive material with desired properties such as
`
`hardness, since it has been held to be within the general skill of a worker in the art to
`
`select a known material on the basis of its suitability for the intended use as a matter of
`
`obvious design choice.
`
`In re Leshin, 125 USPQ 416.
`
`Conclusion
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`Any inquiry concerning this communication or earlier communications from the
`
`examiner should be directed to ARUN RAMASWAMY whose telephone number is
`
`(571 )270-1 962. The examiner can normally be reached on Mon-Fri, 8:30am-6:00pm.
`
`If attempts to reach the examiner by telephone are unsuccessful, the examiner’s
`
`supervisor, Jenny Wagner can be reached on 5712725359. The fax phone number for
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`the organization where this application or proceeding is assigned is 571-273-8300.
`
`

`

`Application/Control Number: 13/377,212
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`Page 16
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`Art Unit: 2848
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`
`published applications may be obtained from either Private PAIR or Public PAIR.
`
`Status information for unpublished applications is available through Private PAIR only.
`
`For more information about the PAIR system, see http://pair-direct.uspto.gov. Should
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`
`/A. R./
`
`Examiner, Art Unit 2835
`/Eric Thomas/
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`Primary Examiner, Art Unit 2848
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`