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`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMIVHSSIONER FOR PATENTS
`PO. Box 1450
`Alexandria1 Virginia 22313-1450
`wwwusptogov
`
`
`
`
`
`14/199,562
`
`03/06/2014
`
`Masahiro ISHII
`
`20326.0058US01
`
`6642
`
`04’2“” —HAMRE, SCHUMANN,MUELLER&LARSON P.C. «
`
`7590
`53148
`
`CHUNG, DAV ) Y
`45 South Seventh Street
`
`Suite 2700
`MINNEAPOLIS, MN 55402- 1683
`
`DAPER NUMBER
`
`ART UNIT
`2871
`
`NOTIFICATION DATE
`
`DELIVERY MODE
`
`04/24/20 1 7
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above—indicated "Notification Date" to the
`following e—mail address(es):
`PTOMail @hsml.c0m
`
`PTOL—90A (Rev. 04/07)
`
`

`

`
`
`Applicant(s)
`Application No.
` 14/199,562 ISHII ET AL.
`
`Examiner
`Art Unit
`AIA (First Inventor to File)
`Office Action Summary
`
`DAVID CHUNG $2213 2871
`
`-- The MAILING DA TE of this communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE g MONTHS FROM THE MAILING DATE OF
`THIS COMMUNICATION.
`Extensions of time may be available under the provisions of 37 CFR1. 136( a).
`after SIX () MONTHS from the mailing date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any
`earned patent term adjustment. See 37 CFR 1 .704(b).
`
`In no event, however, may a reply be timely filed
`
`Status
`
`1)IZI Responsive to communication(s) filed on 19 December 2016.
`El A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/were filed on
`
`2b)|ZI This action is non-final.
`2a)|:l This action is FINAL.
`3)|:I An election was made by the applicant in response to a restriction requirement set forth during the interview on
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`; the restriction requirement and election have been incorporated into this action.
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`4)|:| Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
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`closed in accordance with the practice under Exparte Quay/e, 1935 CD. 11, 453 O.G. 213.
`
`Disposition of Claims*
`
`5)IZI CIaim(s)1;8is/are pending in the application.
`5a) Of the above claim(s)
`is/are withdrawn from consideration.
`
`is/are allowed.
`6)|:I Claim(s)
`7)|Z| CIaim(s)_1-8is/are rejected.
`8)|:I Claim(s)_ is/are objected to.
`
`
`are subject to restriction and/or election requirement.
`9)|:I Claim((s)
`* If any claims have been determined allowable, you may be eligible to benefit from the Patent Prosecution Highway program at a
`
`participating intellectual property office for the corresponding application. For more information, please see
`hit z/thvvvtlsnto. ovI’ atentS/init events/
`
`
`
`iindex.‘s or send an inquiry to PPI-iieedback{®usgtc.00v.
`
`Application Papers
`
`10)I:l The specification is objected to by the Examiner.
`11)|Xl The drawing(s) filed on 06 March 2014 is/are: a)IZl accepted or b)|:l objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`
`12)IXI Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
`Certified copies:
`
`a)IZl All
`
`b)|:l Some” c)I:l None of the:
`
`1.IXI Certified copies of the priority documents have been received.
`2.|:l Certified copies of the priority documents have been received in Application No.
`3.|:| Copies of the certified copies of the priority documents have been received in this National Stage
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`application from the International Bureau (PCT Rule 17.2(a)).
`** See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`
`
`3) D Interview Summary (PTO-413)
`1) E Notice of References Cited (PTO-892)
`Paper No(s)/Mai| Date.
`.
`.
`4) I:I Other'
`2) I] InformatIon DIsclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`Paper No(s)/Mai| Date
`
`US. Patent and Trademark Office
`PTOL—326 (Rev. 11-13)
`
`Office Action Summary
`
`Part of Paper No./Mai| Date 20170417
`
`

`

`Application/Control Number: 14/199,562
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`Page 2
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`Art Unit: 2871
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`The present application, filed on or after March 16, 2013, is being examined
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`under the first inventor to file provisions of the AIA.
`
`DETAILED ACTION
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`Claim Rejections - 35 USC § 103
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`The following is a quotation of 35 U.S.C. 103 which forms the basis for all
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`obviousness rejections set forth in this Office action:
`
`A patent for a claimed invention may not be obtained, notwithstanding that the claimed
`invention is not identically disclosed as set forth in section 102, if the differences between the
`claimed invention and the prior art are such that the claimed invention as a whole would have
`been obvious before the effective filing date of the claimed invention to a person having
`ordinary skill in the art to which the claimed invention pertains. Patentability shall not be
`negated by the manner in which the invention was made.
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`Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over
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`Takenaka et al. (US 2008/0291379) in view of Kato (US 2002/0018169) and Ben-
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`Shalom et al. (US 7,551,245).
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`As to claim 1, Takenaka discloses in figure 1: a plurality of gate signal lines GL
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`each extending in a row direction; a plurality of data signal lines DL each extending in a
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`column direction; a plurality of pixel regions A arranged in the row direction and in the
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`column direction in an image display region AR; a common electrode CT formed in the
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`image display region AR; a plurality of common wirings CL extending in the row
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`direction, for supplying a common voltage to the common electrode; a rectangular
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`common bus line CBL surrounding the image display region AR. The common bus line
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`CBL includes a first common bus line extending in the column direction and being
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`electrically connected to the plurality of common wirings, and a second common bus
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`line extending in the row direction and being electrically connected to the first common
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`

`

`Application/Control Number: 14/199,562
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`Page 3
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`Art Unit: 2871
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`bus line. Takenaka further discloses in figures 1, a plurality of connection wirings CW2
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`and CW3 arranged in the row direction at positions outside the image display region, for
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`supplying the common voltage to the second common bus line. The plurality of
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`connection wirings comprise a first connection wiring and a second connection wiring
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`disposed at a position farther from the first common bus line in the row direction than
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`the first connection wiring.
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`Takenaka does not disclose that the second common bus line is divided into a
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`plurality of division wirings by a plurality of slits. Kato discloses in figure 48, a signal
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`wire divided into a plurality of L-shaped division wirings 43 by a plurality of slits. Kato
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`teaches that with this wiring structure, the cost of the flexible wiring boards may be
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`reduced. See paragraph [0051]. Therefore, it would have been obvious to one of
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`ordinary skill in the art before the effective filing date of the claimed invention to modify
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`Takenaka so that the second common bus line has the wiring structure disclosed by
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`Kato in order to reduce the cost of the flexible wiring boards. This modification would
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`result in a first division wiring connected to the first connection wiring and a second
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`division wiring connected to the second connection wiring
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`Takenaka does not disclose that the column direction width of the first division
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`wiring is smaller than the column division width of the second division wiring. Ben-
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`Shalom discloses in figures 10 and 11 that the line widths of the input portions 3 vary
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`depending on the distance of routing. That is, the input portions 3 routed a longer
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`distance have greater line widths, and the input portions 3 routed over a shorter
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`distance have smaller line widths.
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`In this display panel structure, a difference in the
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`

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`Application/Control Number: 14/199,562
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`Page 4
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`Art Unit: 2871
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`interconnect resistance among the individual input portions 3 can be eliminated, which
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`has been caused by a difference in the distance of routing. Thus, the influence of the
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`interconnect resistance on the drive pulse waveform, which varies with the individual
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`input portions 3, can be made uniform. Accordingly, the display panel according to this
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`preferred embodiment can obtain images of high display quality. See column 9, line 60
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`— column 10, line 13.
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`It would have been obvious to one of ordinary skill in the art
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`before the effective filing date of the claimed invention to further modify Takenaka so
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`that the column direction width of the first division wiring is smaller than the column
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`division width of the second division wiring in order to obtain images of high display
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`quality by eliminating the difference in interconnect resistance as taught by Ben-
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`Shalom.
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`As to claim 2, Takenaka in view of Kato and Ben-Shalom discloses all of the
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`elements of the claimed invention discussed above regarding claim 1. Furthermore,
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`Kato discloses in figure 48, a first division wiring 43 and a second division wiring formed
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`in an L-shape, wherein a row direction width of the first division wiring at an end
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`connected to the first connection wiring is equal to a row direction width of the second
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`division wiring at an end connected to the second connection wiring.
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`As to claim 3, Takenaka in view of Kato and Ben-Shalom discloses all of the
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`elements of the claimed invention discussed above regarding claim 1. Furthermore,
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`Takenaka in view of Kato discloses that ends of the plurality of division wirings
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`connected to the first common bus line are coupled to each other.
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`

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`Application/Control Number: 14/199,562
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`Page 5
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`Art Unit: 2871
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`As to claim 4, Takenaka in view of Kato and Ben-Shalom discloses all of the
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`elements of the claimed invention discussed above regarding claim 1. Furthermore,
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`Takenaka discloses in figure 1 that the first common bus line and the second common
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`bus line are electrically connected to each other via a metal wiring.
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`As to claims 5 and 6, Takenaka in view of Kato and Ben-Shalom discloses all of
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`the elements of the claimed invention discussed above regarding claim 1. Takenaka in
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`view of Kato and Ben-Shalom does not disclose that the first common bus line is formed
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`in the same layer as the plurality of data signal lines and the second common bus line is
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`formed in the same layer as the plurality of gate signal lines. However, one of ordinary
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`skill would have noted that the first common bus line runs parallel to the data signal
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`lines and the second common bus line runs parallel to the gate signal lines. This allows
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`the first common bus line and the data signal lines to be patterned from a single metal
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`layer and allows the second common bus line and the gate signal lines to be patterned
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`from a single metal layer, improving the efficiency of manufacturing. Therefore, it would
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`have been obvious to one of ordinary skill in the art before the effective filing date of the
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`claimed invention to modify Takenaka so that the first common bus line is formed in the
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`same layer as the plurality of data signal lines and the second common bus line is
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`formed in the same layer as the plurality of gate signal lines in order to improve the
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`efficiency of manufacturing.
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`As to claim 7, Takenaka in view of Kato and Ben-Shalom discloses all of the
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`elements of the claimed invention discussed above regarding claim 1. Furthermore,
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`

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`Application/Control Number: 14/199,562
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`Page 6
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`Art Unit: 2871
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`Takenaka discloses in figure 1 that the first common bus line, the second common bus
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`line, and the common electrode CT are formed in the same layer.
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`As to claim 8, Takenaka in view of Kato and Ben-Shalom discloses all of the
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`elements of the claimed invention discussed above regarding claim 1. Furthermore,
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`Takenaka discloses in figure 1 that the first common bus line comprises first common
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`bus lines disposed on both sides of the image display region and the second common
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`bus line comprises second common bus lines disposed in a line symmetric manner with
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`respect to a center line in the row direction of the image display region.
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`Response to Arguments
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`Applicant’s arguments with respect to claim 1 have been considered but are
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`moot in view of the new grounds of rejection. The new grounds of rejection are based
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`in part on the newly cited prior art of Ben-Shalom et al. (US 7,551,245).
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`Conclusion
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`Any inquiry concerning this communication or earlier communications from the
`
`examiner should be directed to David Chung whose telephone number is (571) 272-
`
`2288. The examiner can normally be reached Monday thru Friday from 8:30 AM to 5:00
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`PM.
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`If attempts to reach the examiner by telephone are unsuccessful, the examiner’s
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`supervisor Ed Glick can be reached at (571) 272-2490. The fax number for the
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`organization where this application or proceeding is assigned is 571 -273-8300.
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`

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`Application/Control Number: 14/199,562
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`Page 7
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`Art Unit: 2871
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`Information regarding the status of an application may be obtained from the
`
`Patent Application Information Retrieval (PAIR) system. Status information for
`
`published applications may be obtained from either Private PAIR or Public PAIR.
`
`Status information for unpublished applications is available through Private PAIR only.
`
`For more information about the PAIR system, see http://pair-direct.uspto.gov. Should
`
`you have questions on access to the Private PAIR system, contact the Electronic
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`Business Center (EBC) at 866-217-9197 (toll-free).
`
`If you would like assistance from a
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`USPTO Customer Service Representative or access to the automated information
`
`system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
`
`/David Y. Chung/
`Examiner, Art Unit 2871
`
`/Edward Glick/
`
`Supervisory Patent Examiner, Art Unit 2871
`
`