`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMIVHSSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria1 Virginia 22313-1450
`www.uspto.gov
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`'I AND1%9
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`14/813,753
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`07/30/2015
`
`Hidekuni YOMO
`
`WASH1-52283US1
`
`1077
`
`02/26/2016 —PEARNE & GORDON LLP m
`7590
`52054
`1801 EAST 9TH STREET
`YU’ LIHONG
`S UITE 1 200
`CLEVELAND, OH 441 14-3 108
`
`PAPER NUMBER
`
`2631
`
`NOTIFICATION DATE
`
`DELIVERY MODE
`
`02/26/2016
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above—indicated "Notification Date" to the
`following e—mail address(es):
`
`patdocket @ pearne.c0m
`jcholley @pearne.c0m
`
`PTOL—90A (Rev. 04/07)
`
`
`
`
`
`Applicant(s)
`Application No.
` 14/813,753 YOMO ET AL.
`
`Examiner
`Art Unit
`AIA (First Inventorto File)
`Office Action Summary
`
`2631LIHONG YU first“
`
`-- The MAILING DA TE of this communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE g MONTHS FROM THE MAILING DATE OF
`THIS COMMUNICATION.
`Extensions of time may be available under the provisions of 37 CFR 1.136(a).
`after SIX (6) MONTHS from the mailing date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any
`earned patent term adjustment. See 37 CFR 1.704(b).
`
`In no event, however, may a reply be timely filed
`
`-
`-
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`Status
`
`1)IXI Responsive to communication(s) filed on 07/30/2015.
`[I A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/were filed on
`
`2b)lX| This action is non-final.
`2a)I:| This action is FINAL.
`3)I:I An election was made by the applicant in response to a restriction requirement set forth during the interview on
`
`
`; the restriction requirement and election have been incorporated into this action.
`
`4)|:I Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under EX parte Quay/e, 1935 CD. 11, 453 O.G. 213.
`
`3) D Interview Summary (PT0_413)
`1) E Notice of References Cited (PTO-892)
`Paper No(s)/Mai| Date.
`.
`.
`—
`4) I:I Other'
`2) E Information Disclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`Paper No(s)/Mai| Date See Continuation Sheet.
`U.S. Patent and Trademark Office
`PTOL-326 (Rev. 11-13)
`
`Office Action Summary
`
`Part of Paper No./Mai| Date 20160219
`
`Disposition of Claims*
`5)|XI Claim(s) L6is/are pending in the application.
`5a) Of the above claim(s)
`is/are withdrawn from consideration.
`6 III Claim s) _ is/are allowed.
`s L6 is/are rejected.
`
`is/are objected to.
`
`) )
`
`_
`
`
`are subject to restriction and/or election requirement.
`9)|:l Claim(s
`)
`* If any claims have been determined allowable, you may be eligible to benefit from the Patent Prosecution Highway program at a
`
`participating intellectual property office for the corresponding application. For more information, please see
`htt
`://www.usoto. ov/ atents/init events"
`h/index.‘s
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`, or send an inquiry to PF"I-Ifeedback{<‘buspto.qov.
`
`Application Papers
`
`10)I:I The specification is objected to by the Examiner.
`11)|Z| The drawing(s) filed on 07/30/2015 is/are: a)IXI accepted or b)I:I objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`12)IZI Acknowledgment is made of a claim for foreign priority under 35 U.S.C. §119(a)-(d) or (f).
`Certified copies:
`
`b)I:I Some” c)I:I None of the:
`a)le All
`1.IZI Certified copies of the priority documents have been received.
`2.I:I Certified copies of the priority documents have been received in Application No.
`3.I:I Copies of the certified copies of the priority documents have been received in this National Stage
`
`application from the International Bureau (PCT Rule 17.2(a)).
`** See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`
`
`
`
`Continuation Sheet (PTOL-326)
`
`Application No. 14/813,753
`
`Continuation of Attachment(s) 2). Information Disclosure Statement(s) (PTO/SB/08), Paper No(s)/Mai| Date :01/28/2016, 08/13/2015,
`07/30/2015.
`
`
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`Application/Control Number: 14/813,753
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`Page 2
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`Art Unit: 2631
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`DETAILED ACTION
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`1.
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`The present application is being examined under the pre—AIA first to invent provisions.
`
`2.
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`Claim 5 is objected to because of the following informalities:
`
`Claim Objections
`
`Claim 5 has limitation “1024/2M”. It is not clear whether the symbol “I” stands for “or”
`
`or a division. Since “/” is used as an “or” in later part of claim 5, “/” is interpreted as “or” for
`
`examination purpose.
`
`Appropriate correction is required.
`
`Double Patenting
`
`3.
`
`The nonstatutory double patenting rejection is based on a judicially created doctrine
`
`grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or
`
`improper timewise extension of the “right to exclude” granted by a patent and to prevent possible
`
`harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where
`
`the claims at issue are not identical, but at least one examined application claim is not patentably
`
`distinct from the reference claim(s) because the examined application claim is either anticipated
`
`by, or would have been obvious over, the reference claim(s). See, e. g., In re Berg, 140 F.3d
`
`1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed.
`
`Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686
`
`
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`Application/Control Number: 14/813,753
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`Page 3
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`Art Unit: 2631
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`F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA
`
`1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
`
`A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may
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`be used to overcome an actual or provisional rejection based on a nonstatutory double patenting
`
`ground provided the reference application or patent either is shown to be commonly owned with
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`this application, or claims an invention made as a result of activities undertaken within the scope
`
`of a joint research agreement. See MPEP § 717.02 for applications subject to examination under
`
`the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§
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`706.02(l)(l) — 706.02(l)(3) for applications not subject to examination under the first inventor to
`
`file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR
`
`1.321(b).
`
`The USPTO Internet website contains terminal disclaimer forms which may be used.
`
`Please visit www.uspto.gov/forms/. The filing date of the application in which the form is filed
`
`determines what form (e. g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be
`
`used. A web—based eTerminal Disclaimer may be filled out completely online using web—screens.
`
`An eTerminal Disclaimer that meets all requirements is auto—processed and approved
`
`immediately upon submission. For more information about eTerminal Disclaimers, refer to
`
`
`
`4.
`
`Claim 2 is rejected on the ground of nonstatutory double patenting as being unpatentable
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`over claim 1 of US. Patent No. (US 9,191,253 B2). Although the claims at issue are not
`
`identical, they are not patentably distinct from each other because:
`
`
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`Application/Control Number: 14/813,753
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`Page 4
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`Art Unit: 2631
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`Instant Application: 14/813,753
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`US. Patent No. (US 9,191,253 B2)
`
`2. A signal converter that performs at least
`one of a fast Fourier transform and an inverse
`
`fast Fourier transform, comprising:
`
`1. An adaptive equalizer that performs
`adaptive equalization on a time—domain signal
`in a frequency domain, comprising a signal
`conversion section that performs at least one
`of a fast Fourier transform and an inverse fast
`
`Fourier transform, wherein the signal
`conversion section includes:
`
`and the inverse fast Fourier transform.
`
`a memory capable of reading and writing
`signals for 2M samples, where M is a natural
`number;
`
`a memory capable of reading and writing
`signals for 2M samples, where M is a natural
`number;
`
`2M registers accessible to the memory;
`
`2M registers accessible to the memory;
`
`M butterfly operation sections: and
`
`M butterfly operation sections; and
`
`a switching control section that switches a
`connection state between the 2M registers and
`the M butterfly operation sections, wherein:
`
`a switching control section that switches a
`connection state between the 2M registers and
`the M butterfly operation sections, wherein:
`
`the signal converter includes two pairs of the
`memory and the 2M registers; and the
`switching control section switches a
`connection state (i) between the 2M registers
`in one of the two pairs and the M butterfly
`operation sections and (ii) between the 2M
`registers in the other of the two pairs and the
`M butterfly operation sections, such that a
`role of the memory is switched between a
`memory for output and a memory for input
`for each stage of the fast Fourier transform
`and the inverse fast Fourier transform.
`
`the signal conversion section includes two
`pairs of the memory and the 2M registers;
`and the switching control section switches a
`connection state (i) between the 2M registers
`in one of the two pairs and the M butterfly
`operation sections and (ii) between the 2M
`registers in the other of the two pairs and the
`M butterfly operation sections, such that a
`role of the memory is switched between a
`memory for output and a memory for input
`for each stage of the fast Fourier transform
`
`Claim Rejections - 35 USC § 112
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`5.
`
`The following is a quotation of the first paragraph of pre—AIA 35 USC. 112:
`
`
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`Application/Control Number: 14/813,753
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`Page 5
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`Art Unit: 2631
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`The specification shall contain a written description of the invention, and of the manner and
`process of making and using it, in such full, clear, concise, and exact terms as to enable any person
`skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the
`same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
`
`6.
`
`Claim 6 is rejected under 35 U.S.C. 112 (pre—AIA), first paragraph, as failing to comply
`
`with the written description requirement. The claim 6 contains new subject matter which was
`
`not described in the specification in such a way as to reasonably convey to one skilled in the
`
`relevant art that the inventor or a joint inventor, or for pre—AIA the inventor(s), at the time the
`
`application was filed, had possession of the claimed invention.
`
`Claim 6 recites “a memory, having two—bank configuration and each bank having a single
`
`port, capable of reading and writing signals for 2M samples by one access”. However, in
`
`paragraph [0071] of the instant Specification, the applicant states “signal conversion section 200
`
`is capable of reducing the number of memory access by configuring a two—bank wide—bit
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`memory. Stated differently, the number of necessary memory access which was 2x(1024/M) in a
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`one—bank configuration is reduced to half”. This means that the number of memory access is
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`(1024/M), not “one access’ as stated in claim 6.
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`Further, one skilled in the art would consider “reading and writing" a memory as two
`
`1’1’161’1’101'y acces SC S .
`
`Claim Rejections - 35 USC § 103
`
`7.
`
`The following is a quotation of pre—AIA 35 U.S.C. 103(a) which forms the basis for all
`
`obviousness rejections set forth in this Office action:
`
`(a) A patent may not be obtained though the invention is not identically disclosed or described as set
`forth in section 102 of this title, if the differences between the subject matter sought to be patented and
`the prior art are such that the subject matter as a whole would have been obvious at the time the
`
`
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`Application/Control Number: 14/813,753
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`Page 6
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`Art Unit: 2631
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`invention was made to a person having ordinary skill in the art to which said subject matter pertains.
`Patentability shall not be negatived by the manner in which the invention was made.
`
`8.
`
`Claims 1 and 3 are rejected under pre—AIA 35 U.S.C. 103(a) as being unpatentable over
`
`Nishijima et al (US 2005/0094804 A1) in View of Mundarath et al (US 2009/0313314 A1).
`
`Consider claim 1:
`
`Nishijima discloses a signal converter that performs at least one of a fast Fourier
`
`transform and an inverse fast Fourier transform (see Fig. 45 and paragraphs 0223 -0224, where
`
`Nishijima describes a FFT transform using butterfly computations), comprising:
`
`0
`
`a memory, capable of reading and writing signals for 2M samples by two
`
`accesses, where M is a natural number (see Fig. 46 and paragraphs 0231-0232,
`
`where Nishijima describes an input memory 460] receives I 6 input data, thus
`
`M=8);
`
`0
`
`2M register accessible to the memory (see Fig. 46 and paragraphs 0231-0232,
`
`0
`
`o
`
`where Nishijima describes the memory 460] could be registerfor storing the I 6
`
`input data; see Fig. 43A and paragraph 0219, where Nishijima describes I 6
`
`registers 4301 (Reg00 to Reg15) for storing the input data);
`
`M butterfly operation sections (see Fig. 46 and paragraph 0231-00232, where
`
`Nishijima describes 8 butterfly computing elements 4604); and
`
`a switching control section that switches a connection state between the 2M
`
`registers and the M butterfly operation sections (see Fig. 46 and paragraph 023] -
`
`00233, where Nishijima describe a selector 4602 that selects the input data in
`
`accordance with setting of a selector setting part 4612 for setting wiring, thus a
`
`
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`Application/Control Number: 14/813,753
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`Page 7
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`Art Unit: 2631
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`connection state; see paragraph 0203, where Nishijima describes the selector
`
`performs switching ofprocessing).
`
`Nishijima does not specifically disclose the memory having a single port.
`
`Mundarath teaches a memory having a single port (see paragraph 003], where
`
`Mundarath describes a fast Fourier transform using a single-port memory, a register, a
`
`selection unit, and a DSP performing butterfly operations).
`
`It would have been obvious to one of ordinary skill in the art at the time the invention
`
`was made to modify the invention of Nishijima, and to have that the memory having a single
`
`port, as taught by Mundarath, thus allowing for efficient use of hardware, as discussed by
`
`Mundarath (see paragraph 0028).
`
`Consider claim 3:
`
`Nishijima in view of Mundarath discloses the signal converter according to claim 1
`
`above. Nishijima discloses a twiddle—factor memory that stores twiddle factors in each stage of
`
`the fast Fourier transform and the inverse fast Fourier transform, and that is capable of reading
`
`signals for M samples; and M twiddle—factor registers that are accessible to the twiddle—factor
`
`memory, and that obtains the twiddle factors and passes the twiddle factors to the M butterfly
`
`operation sections (see Fig. 45 and paragraphs 0223 -0224, where Nishijima describes the
`
`multiplication coejficients W0, W], W and W3, thus twiddle factors, that are used in each stage
`
`of the butterfly computations).
`
`
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`Application/Control Number: 14/813,753
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`Page 8
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`Art Unit: 2631
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`9.
`
`Claim 4 is rejected under pre—AIA 35 U.S.C. 103(a) as being unpatentable over Nishijima
`
`et al (US 2005/0094804 Al) in view of Mundarath et al (US 2009/0313314 A1), as applied to
`
`claim 1 above, and further in view of Pyu (US 2002/0178195 Al).
`
`Consider claim 4:
`
`Nishijima in view of Mundarath discloses the signal converter according to claim 1
`
`above. Nishijima does not specifically disclose the memory stores data for M samples
`
`collectively in one address.
`
`Pyu teaches memory stores data for M samples collectively in one address (see Fig. 6 and
`
`paragraphs 005 7-0069, where Pyu describes using one output address to store samples of one
`
`butterfly calculation results).
`
`It would have been obvious to one of ordinary skill in the art at the time the invention
`
`was made to modify the invention of Nishijima, and to include that the memory stores data for M
`
`samples collectively in one address, as taught by Ryu, thus allowing for simplifying calculation
`
`process, as discussed by Ryu (see paragraph 0027).
`
`10.
`
`Claim 5 is rejected under pre—AIA 35 U.S.C. 103(a) as being unpatentable over Nishijima
`
`et al (US 2005/0094804 A1) in view of Mundarath et al (US 2009/0313314 A1) and Pyu (US
`
`2002/0178195 Al), as applied to claim 4 above, and further in view of Weill (US 2011/0007783
`
`A1).
`
`Consider claim 5:
`
`Nishijima in view of Mundarath and Pyu discloses the signal converter according to
`
`claim 4 above. Nishijima discloses an address space of the memory is 1024/2M (see Fig. 46 and
`
`
`
`Application/Control Number: 14/813,753
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`Page 9
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`Art Unit: 2631
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`paragraphs 0231-0232, where Nishijima describes the memory 460] could be register for
`
`storing the I 6 input data; see Fig. 43A and paragraph 0219, where Nishijima describes I 6
`
`registers 4301 (RegOO to Reg15) for storing the input data, therefore 2M=I6).
`
`Nishijima does not specifically disclose the signal converter performs the fast Fourier
`
`transform /the inverse fast Fourier transform operation at 1024 points.
`
`Weill teaches a signal converter performs the fast Fourier transform /the inverse fast
`
`Fourier transform operation at 1024 points (see Fig. 13 and paragraph 015], where Weill
`
`describes that a I 024-point FFT is performed).
`
`It would have been obvious to one of ordinary skill in the art at the time the invention
`
`was made to modify the invention of Nishijima, and to include that the signal converter performs
`
`the fast Fourier transform /the inverse fast Fourier transform operation at 1024 points, as taught
`
`by Weill, thus allowing for faster FFT, as discussed by Weill (see paragraph 015]).
`
`11.
`
`Claim 6 is rejected under pre—AIA 35 U.S.C. 103(a) as being unpatentable over Nishijima
`
`et al (US 2005/0094804 A1) in view of Yu (US 2006/0253514 A1).
`
`Consider claim 6:
`
`Nishijima discloses a signal converter that performs at least one of a fast Fourier
`
`transform and an inverse fast Fourier transform (see Fig. 45 and paragraphs 0223 -0224, where
`
`Nishijima describes a FFT transform using butterfly computations), comprises:
`
`0
`
`a memory, capable of reading and writing signals for 2M samples by one access,
`
`where M is a natural number (see Fig. 46 and paragraphs 0231-0232, where
`
`Nishijima describes an input memory 460] receives I 6 input data, thus M= 8);
`
`
`
`Application/Control Number: 14/813,753
`
`Page 10
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`Art Unit: 2631
`
`0
`
`2M register accessible to the memory (see Fig. 46 and paragraphs 0231-0232,
`
`0
`
`o
`
`where Nishijima describes the memory 460] could be registerfor storing the I 6
`
`input data; see Fig. 43A and paragraph 0219, where Nishijima describes I 6
`
`registers 4301 (Reg00 to Reg15) for storing the input data);
`
`M butterfly operation sections (see Fig. 46 and paragraph 0231-00232, where
`
`Nishijima describes 8 butterfly computing elements 4604); and
`
`a switching control section that switches a connection state between the 2M
`
`registers and the M butterfly operation sections (see Fig. 46 and paragraph 023] -
`
`00233, where Nishijima describe a selector 4602 that selects the input data in
`
`accordance with setting of a selector setting part 4612 for setting wiring, thus a
`
`connection state; see paragraph 0203, where Nishijima describes the selector
`
`performs switching ofprocessing).
`
`Nishijima does not specifically disclose the memory haVing two—bank configuration and
`
`each bank haVing a single port.
`
`Yu teaches a memory haVing two—bank configuration and each bank haVing a single port
`
`(see Fig. 6, paragraphs 0030 and 0037, where Yu describes a fast Fourier transform using
`
`single-port memory banks).
`
`It would have been obVious to one of ordinary skill in the art at the time the invention
`
`was made to modify the invention of Nishijima, and to have that the memory haVing two—bank
`
`configuration and each bank haVing a single port, as taught by Yu, thus allowing for reducing the
`
`circuit area of the deVice, as discussed by Yu (see paragraph 0030).
`
`
`
`Application/Control Number: 14/813,753
`
`Page 11
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`Art Unit: 2631
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`Conclusion
`
`Any inquiry concerning this communication or earlier communications from the
`
`examiner should be directed to LIHONG YU Whose telephone number is (571)270—5147. The
`
`examiner can normally be reached on 8:30 am—7:00 pm Monday—Friday.
`
`If attempts to reach the examiner by telephone are unsuccessful, the examiner’s
`
`supervisor, Shuwang Liu can be reached on (571) 272—3036. The fax phone number for the
`
`organization Where this application or proceeding is assigned is 571—273—8300.
`
`Information regarding the status of an application may be obtained from the Patent
`
`Application Information Retrieval (PAIR) system. Status information for published applications
`
`may be obtained from either Private PAIR or Public PAIR. Status information for unpublished
`
`applications is available through Private PAIR only. For more information about the PAIR
`
`system, see http://pair—direct.uspto.gov. Should you have questions on access to the Private PAIR
`
`system, contact the Electronic Business Center (EBC) at 866—217—9197 (toll—free). If you would
`
`like assistance from a USPTO Customer Service Representative or access to the automated
`
`information system, call 800—786—9199 (IN USA OR CANADA) or 571—272—1000.
`
`/LIHONG YU/
`
`Primary Examiner, Art Unit 2631
`
`