www.uspto.gov
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`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 2231371450
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`15/582,794
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`05/01/2017
`
`ARATA KISHI
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`PIPMM-57489
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`4480
`
`759°
`52°“
`PEARNE & GORDON LLP
`
`11/02/2018
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`1801 EAST 9TH STREET
`SUITE 1200
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`CLEVELAND, OH 44114-3108
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`PATEL DEVANG R
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`1735
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`PAPER NUMBER
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`NOTIFICATION DATE
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`DELIVERY MODE
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`11/02/2018
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`ELECTRONIC
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`Please find below and/or attached an Office communication concerning this application or proceeding.
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`The time period for reply, if any, is set in the attached communication.
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`Notice of the Office communication was sent electronically on above—indicated "Notification Date" to the
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`following e—mail address(es):
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`patdoeket@pearne.eom
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`PTOL-90A (Rev. 04/07)
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`

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`Off/09 A0170” Summary
`
`Application No.
`15/582,794
`Examiner
`DEVANG R PATEL
`
`Applicant(s)
`KISHI et al.
`Art Unit
`1735
`
`AIA Status
`Yes
`
`- The MAILING DA TE of this communication appears on the cover sheet wit/7 the correspondence address -
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE g MONTHS FROM THE MAILING
`DATE OF THIS COMMUNICATION.
`Extensions of time may be available under the provisions of 37 CFR 1.136(a). In no event, however, may a reply be timely filed
`after SIX (6) MONTHS from the mailing date of this communication.
`|f NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any
`earned patent term adjustment. See 37 CFR 1.704(b).
`
`Status
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`1). Responsive to communication(s) filed on 5/1/17.
`[:1 A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/were filed on
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`2a)D This action is FINAL.
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`2b)
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`This action is non-final.
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`3)[:] An election was made by the applicant in response to a restriction requirement set forth during the interview on
`; the restriction requirement and election have been incorporated into this action.
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`4)[:] Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Expat/7e Quay/e, 1935 CD. 11, 453 O.G. 213.
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`Disposition of Claims*
`5)
`Claim(s)
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`1—10 is/are pending in the application.
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`5a) Of the above claim(s)
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`is/are withdrawn from consideration.
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`E] Claim(s)
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`is/are allowed.
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`Claim(s) fl is/are rejected.
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`[:1 Claim(s) _ is/are objected to.
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`) ) ) )
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`6 7
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`8
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`
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`are subject to restriction and/or election requirement
`[j Claim(s)
`9
`* If any claims have been determined aflowabte. you may be eligible to benefit from the Patent Prosecution Highway program at a
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`participating intellectual property office for the corresponding application. For more information, please see
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`http://www.uspto.gov/patents/init events/pph/index.jsp or send an inquiry to PPeredback@uspto.gov.
`
`Application Papers
`10)[:] The specification is objected to by the Examiner.
`
`11). The drawing(s) filed on 5/1/17 is/are: a). accepted or b)[:] objected to by the Examiner.
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`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`12). Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
`Certified copies:
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`a). All
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`b)D Some”
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`C)D None of the:
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`1..
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`Certified copies of the priority documents have been received.
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`2.[:]
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`Certified copies of the priority documents have been received in Application No.
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`3:] Copies of the certified copies of the priority documents have been received in this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
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`** See the attached detailed Office action for a list of the certified copies not received.
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`Attachment(s)
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`1)
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`Notice of References Cited (PTO-892)
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`Information Disclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`2)
`Paper No(s)/Mail Date_
`U.S. Patent and Trademark Office
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`3) C] Interview Summary (PTO-413)
`Paper No(s)/Mail Date
`4) CI Other-
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`PTOL-326 (Rev. 11-13)
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`Office Action Summary
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`Part of Paper No./Mai| Date 20180823
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`

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`Application/Control Number: 15/582,794
`Art Unit: 1735
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`Page 2
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`DETAILED ACTION
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`Notice of Pre-AIA or AIA Status
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`The present application, filed on or after March 16, 2013, is being examined
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`under the first inventor to file provisions of the AIA.
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`Claim Rejections - 35 USC § 102
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`The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that
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`form the basis for the rejections under this section made in this Office action:
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`A person shall be entitled to a patent unless —
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`(a)(1) the claimed invention was patented, described in a printed publication, or in public use,
`on sale or otherwise available to the public before the effective filing date of the claimed
`invention.
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`1.
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`Claim(s) 1, 4 and 8-9 are rejected under 35 U.S.C. 102(a)(1) as being
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`anticipated by lgarashi (US 2012/0255766).
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`a.
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`Regarding claim 1, lgarashi discloses a connecting method of a circuit
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`member (abstract), comprising:
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`a first process of preparing a connection material containing an adhesive
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`and a solder material that disperses in the adhesive [1] 0042];
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`a second process of preparing a first circuit member having a first
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`electrode and a second circuit member having a second electrode, and disposing
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`the first circuit member and the second circuit member to cause the first
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`electrode and the second electrode to oppose each other via the connection
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`material [1] 0044-0045]; and
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`a third process of compressing the first circuit member and the second
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`circuit member while applying heat to the connection material, wherein the third
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`process includes a first pressing process which is performed before a
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`

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`Application/Control Number: 15/582,794
`Art Unit: 1735
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`Page 3
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`temperature of the connection material reaches a melting point of the solder
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`material, and a second pressing process which follows the first pressing process,
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`wherein, in the first pressing process, after the solder material is pressed at a first
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`pressure and is deformed, pressure is changed to a second pressure that is
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`lower than the first pressure, and the solder material is pressed at the second
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`pressure in the second pressing process [fig. 1; 11 0018-0022].
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`b.
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`As to claim 4, lgarashi discloses that the adhesive includes a
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`thermosetting resin, of which many examples are given [1] 0035-0036], and
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`wherein a temperature at which hardening reaction proceeds for at least one of
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`the exemplary thermosetting resins is higher than the melting point of the solder
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`material [1] 0032].
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`c.
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`As to claims 8-9, lgarashi also discloses several examples of solder
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`material alloys, including a bismuth-indium alloy (Sn-Bi-ln), wherein an amount of
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`bismuth contained in the bismuth-indium alloy is 57% by mass [1] 0032].
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`Claim Rejections - 35 USC § 103
`
`The following is a quotation of 35 U.S.C. 103 which forms the basis for all
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`obviousness rejections set forth in this Office action:
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`A patent for a claimed invention may not be obtained, notwithstanding that the claimed
`invention is not identically disclosed as set forth in section 102, if the differences between the
`claimed invention and the prior art are such that the claimed invention as a whole would have
`been obvious before the effective filing date of the claimed invention to a person having
`ordinary skill in the art to which the claimed invention pertains. Patentability shall not be
`negated by the manner in which the invention was made.
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`This application currently names joint inventors. In considering patentability of the
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`claims the examiner presumes that the subject matter of the various claims was
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`

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`Application/Control Number: 15/582,794
`Art Unit: 1735
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`Page 4
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`commonly owned as of the effective filing date of the claimed invention(s) absent any
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`evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to
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`point out the inventor and effective filing dates of each claim that was not commonly
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`owned as of the effective filing date of the later invention in order for the examiner to
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`consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2)
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`prior art against the later invention.
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`2.
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`Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over
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`lgarashi as applied to claim 1 above, and in view of Katsurayama (US 2010/0059872) &
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`lde et al. (US 2010/0195292, hereafter “lde”).
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`d.
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`As to claims 2—3, lgarashi does not mention the first pressure being about
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`15-30 MPa and second pressure being equal to or lower than the 40% of the first
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`pressure. However, such pressure range is known in the art. Katsurayama (also
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`directed to connected structure using adhesive and solder material- abstract)
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`teaches applying a predetermined bonding pressure which is typically adjusted to
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`0 MPa or above and 20 MPa or less [1] 0154], which falls within claimed range.
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`Similarly, lde discloses bonding a first electrode of a first circuit member (circuit
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`board 200- fig. 2C) to a second electrode of a second circuit member (chip),
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`wherein metallic bond is made by imparting a low pressure in a range of 0.1 to 20
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`MPa [1] 0061, 0073, 0090]. lde further teaches such low-pressure application for
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`flip-chip implementation allows a reduction in the deformation of the wiring or the
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`like [1] 0061]. It is noted that second lower pressure of 0.3 MPa taught by lgarashi
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`[Table 1] is encompassed within 0.1-20 MPa pressure (lde) and 20 MPa or less
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`(Katsurayama). An exemplary second pressure of 0.3 MPa would be equal to
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`

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`Application/Control Number: 15/582,794
`Art Unit: 1735
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`Page 5
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`lower than 40% of exemplary first pressure (e.g. 20 MPa). The pressure ranges
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`taught by prior art overlap with claimed ranges. In the case where the claimed
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`ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case
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`of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA
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`1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Both
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`Katsurayama and lde discloses adjusting bonding pressure between 0.1 to 20
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`MPa and thus, it is art-recognized result effective variable. An artisan would have
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`been also motivated to apply low pressure in a range of 0.1 to 20 MPa in
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`connecting method of lgarashi because it would reduce deformation of the wiring
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`or other structural features on the circuit members (lde). It would have been
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`obvious to one of ordinary skill in the art to select any portion of the disclosed
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`ranges from the ranges disclosed in the prior art reference, particularly in view of
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`the fact that:
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`“The normal desire of scientists or artisans to improve upon what is
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`already generally known provides the motivation to determine where in a
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`disclosed set of percentage ranges is the optimum combination of percentages”,
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`In re Peterson 65 USPQ2d 1379 (CAFC 2003). Also In re Geisler 43 USPQ2d
`1365 (Fed. Cir. 1997); In re Woodruff, 16 USPQ2d 1934 (CCPA 1976); mi
`Malagari, 182 USPQ 549, 553 (CCPA 1974).
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`Therefore, it would have been obvious to one of ordinary skill in the art at
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`the time of the invention to choose the instantly claimed pressure through
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`process optimization in the combination of lgarashi, Katsurayama and lde, since
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`it has been held that where the general conditions of a claim are disclosed in the
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`prior art, discovering the optimum or workable ranges involves only routine skill in
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`the art. See In re Boesch, 205 USPQ 215 (CCPA 1980). MPEP 2144.05.
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`

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`Application/Control Number: 15/582,794
`Art Unit: 1735
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`Page 6
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`3.
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`Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over
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`Igarashi as applied to claim 1 above, and in view of Tong et al. (US 2003/0189260,
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`“Tong”).
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`e.
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`As to claims 5-7, Igarashi discloses a gold plated bump on the circuit
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`element (for example, semiconductor chip- 11 0021). Nonetheless, Tong (drawn
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`to circuit member bonding structure and method) teaches it is known in prior art
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`to form bumps of conductive pads (electrodes) of a carrier (circuit member) in the
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`field of semiconductor packaging, wherein the bumps serve as medium of
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`electrical connection between the chip and the carrier [Background- 11 0005].
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`Therefore, it would have been obvious to a person of ordinary skill in the art
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`before the effective filing date of the invention to provide a suitable bump material
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`on at least one electrode in the connection method of Igarashi since such feature
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`is conventional in the art and doing so would result in desired electrical
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`connection between the circuit members (Tong). As an example, Tong teaches
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`an electrode 222 (first conductive layer) made of titanium or chromium and a
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`bump 224 (second layer) formed of copper, palladium or gold [fig. 2A, 11 0022].
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`Gold has Vickers hardness of greater than 20 Hv while the solder material (e.g.
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`Sn-Bi alloy- lgarashi- 1] 0032) has Vickers hardness of less than 20 Hv, which
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`satisfied the recited values. Therefore, given teachings of Igarashi and Tong, one
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`of ordinary skill in the art would have found it obvious to have gold bump on at
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`least one electrode to form electrical connection between the circuit members in
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`order to produce structure such as flip-chip assembly.
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`

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`Application/Control Number: 15/582,794
`Art Unit: 1735
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`Page 7
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`4.
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`Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Igarashi
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`(US 2012/0255766).
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`f.
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`As to claim 10, Igarashi discloses bismuth-indium alloy (Sn-Bi-ln), wherein
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`the amount of bismuth contained in the bismuth-indium alloy is 57% by mass [1]
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`0032], which is very close to claimed amount of 55% by mass. The claim would
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`have been obvious since it has been held that a prima facie case of obviousness
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`exists where the claimed ranges and prior art ranges do not overlap but are close
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`enough that one skilled in the art would have expected them to have the same
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`properties. Titanium Metals Corp. ofAmerica v. Banner, 778 F.2d 775,
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`227 USPQ 773 (Fed. Cir. 1985), MPEP 2144.05.
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`5.
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`Claim 10 is additionally rejected under 35 U.S.C. 103 as being unpatentable
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`over Igarashi as applied to claim 8 above, and in view of Kishi et al. (US 2016/0316554,
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`“Kishi”).
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`g.
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`As to claim 10, Igarashi is silent as to the amount of bismuth being from
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`51% by mass to 55% by mass in the bismuth-indium-alloy. However, Kishi (also
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`drawn to connection structure of circuit members) teaches using solder material
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`containing bismuth-indium alloy, wherein the amount of bismuth is 51% or 55%
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`by mass bismuth [1] 0008, 0037-0039]. Kishi teaches that it is highly preferable to
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`have 43-47% mass indium (i.e. 53-57% mass bismuth) for the bismuth-indium
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`alloy from the viewpoint of improving electrical connection reliability [11 0040].
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`Therefore, it would have been obvious to a person of ordinary skill in the art
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`before the effective filing date of the invention to employ bismuth-indium alloy
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`