`
`V i$ T {a
`
`A
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 2231371450
`www.uspto.gov
`
`16/154,287
`
`10/08/2018
`
`Takashi MIBU
`
`20295.0024U501
`
`1754
`
`53148
`
`759°
`
`07/31/20”
`
`HAMRE, SCHUMANN, MUELLER & LARSON RC.
`45 South Seventh Street
`Suite 2700
`
`MINNEAPOLIS, MN 55402-1683
`
`LIU' SHAN
`
`2871
`
`PAPER NUMBER
`
`NOTIFICATION DATE
`
`DELIVERY MODE
`
`07/31/2019
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above—indicated "Notification Date" to the
`
`following e—mail address(es):
`PTOMai1@hsml.eom
`
`PTOL-90A (Rev. 04/07)
`
`

`

`0/7709 A0170” Summary
`
`Application No.
`16/154,287
`Examiner
`SHAN LIU
`
`Applicant(s)
`MIBU, Takashi
`Art Unit
`2871
`
`AIA (FITF) Status
`Yes
`
`- The MAILING DA TE of this communication appears on the cover sheet wit/7 the correspondence address -
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE g MONTHS FROM THE MAILING
`DATE OF THIS COMMUNICATION.
`Extensions of time may be available under the provisions of 37 CFR 1.136(a). In no event, however, may a reply be timely filed after SIX (6) MONTHS from the mailing
`date of this communication.
`|f NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any earned patent term
`adjustment. See 37 CFR 1.704(b).
`
`Status
`
`1). Responsive to communication(s) filed on 10/8/2019.
`[:1 A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/were filed on
`
`2a)D This action is FINAL.
`
`2b)
`
`This action is non-final.
`
`3)[:] An election was made by the applicant in response to a restriction requirement set forth during the interview on
`; the restriction requirement and election have been incorporated into this action.
`
`4)[:] Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Expat/7e Quay/e, 1935 CD. 11, 453 O.G. 213.
`
`Disposition of Claims*
`5)
`Claim(s)
`
`1—12 is/are pending in the application.
`
`5a) Of the above claim(s)
`
`is/are withdrawn from consideration.
`
`E] Claim(s)
`
`is/are allowed.
`
`Claim(s) fl is/are rejected.
`
`[:1 Claim(s) _ is/are objected to.
`
`) ) ) )
`
`6 7
`
`8
`
`
`
`are subject to restriction and/or election requirement
`[j Claim(s)
`9
`* If any claims have been determined aflowabie. you may be eligible to benefit from the Patent Prosecution Highway program at a
`
`participating intellectual property office for the corresponding application. For more information, please see
`
`http://www.uspto.gov/patents/init events/pph/index.jsp or send an inquiry to PPeredback@uspto.gov.
`
`Application Papers
`10)[:] The specification is objected to by the Examiner.
`
`11). The drawing(s) filed on 10/8/2019 is/are: a). accepted or b)E] objected to by the Examiner.
`
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`12). Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
`Certified copies:
`
`a). All
`
`b)D Some**
`
`C)D None of the:
`
`1.. Certified copies of the priority documents have been received.
`
`2.[:] Certified copies of the priority documents have been received in Application No.
`
`3:] Copies of the certified copies of the priority documents have been received in this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`
`** See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`1)
`
`Notice of References Cited (PTO-892)
`
`Information Disclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`2)
`Paper No(s)/Mail Date_
`U.S. Patent and Trademark Office
`
`3) C] Interview Summary (PTO-413)
`Paper No(s)/Mail Date
`4) CI Other-
`
`PTOL-326 (Rev. 11-13)
`
`Office Action Summary
`
`Part of Paper No./Mai| Date 20190722
`
`

`

`Application/Control Number: 16/154,287
`Art Unit: 2871
`
`Page 2
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`Notice of Pre-AIA or AIA Status
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`The present application, filed on or after March 16, 2013, is being examined under the first
`
`inventor to file provisions of the AIA.
`
`In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102
`
`and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory
`
`basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and
`
`the rationale supporting the rejection, would be the same under either status.
`
`Claim Rejections - 35 USC § 103
`
`The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections
`
`set forth in this Office action:
`
`A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is
`not identically disclosed as set forth in section 102 of this title, if the differences between the claimed
`invention and the prior art are such that the claimed invention as a whole would have been obvious
`before the effective filing date of the claimed invention to a person having ordinary skill in the art to
`which the claimed invention pertains. Patentability shall not be negated by the manner in which the
`invention was made.
`
`Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US
`
`2014/0118652) in view of Son at al. (US 2014/0168554) and Sasaki (US 2012/0057119).
`
`Re claim 1, Zhang et al. teaches a liquid crystal display panel (Fig. 10, abs, [0007, 0063, 0036,
`
`0057-0062, 0003, 0044]) having a plurality of pixels (Abs, [0007, 0039] Fig. 10) arranged in a matrix (Abs,
`
`[0007, 0039] Fig. 10) comprising:
`
`a first substrate (Abs, [0007, 0039], Fig. 10);
`
`a plurality of transistors (Fig. 10, Abs, [0057]) provided on the first substrate (Abs, [0007, 0039],
`
`Fig. 10) in each of the plurality of pixels (Abs, [0007, 0039] Fig. 10);
`
`each of the plurality of transistors (Fig. 10, Abs, [0057]) includes a gate electrode (Fig. 10, [0041,
`
`0049]), and a source and drain electrode (Fig. 10, [0041, 0049]).
`
`

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`Application/Control Number: 16/154,287
`Art Unit: 2871
`
`Page 3
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`Zhang et al. does not explicitly point out that a second substrate opposed to the first substrate;
`
`a liquid crystal layer disposed between the first substrate and the second substrate; each of the plurality
`
`of transistors includes a semiconductor layer. Zhang et al. also does not teach that a first spacer
`
`provided on the second substrate; and a first laminated structure provided on the first substrate,
`
`wherein the first spacer is located between the two adjacent transistors among the plurality of
`
`transistors in each of the plurality of pixels, the first laminated structure is provided opposite to the first
`
`spacer, and the first laminated structure includes a first film formed in a same layer as that of the gate
`
`electrode and a second film formed in a same layer as that of one of the semiconductor layer and the
`
`source and drain electrode.
`
`Son et al. teaches that a second substrate (Fig. 6A) opposed to the first substrate (Fig. 6A); a
`
`liquid crystal layer (Fig. 6A, [0009, 0090]) disposed between the first substrate and the second substrate
`
`(Fig. 6A, [0009, 0090]); a first spacer (194 and/or 192 in Fig. 4-7D, [0099, 0057-0059, 0087-0096])
`
`provided on the second substrate (Fig. 6A, [0057-0059, 0087]); and a first laminated structure (Fig. 6A,
`
`[0078]) provided on the first substrate (Fig. 6A), wherein the first spacer (194 and/or 192 in Fig. 4-7D,
`
`[0057-0059, 0087-0096]) is located between the two adjacent transistors (Fig. 4) among the plurality of
`
`transistors (Fig. 4) in each ([0099]) of the plurality of pixels (PXL in Fig. 7A-7D and Fig. 4, [0099]), the first
`
`laminated structure (Fig. 6A, [0078]) is provided opposite to (Fig. 6A) the first spacer (194 and/or 192 in
`
`Fig. 4-7D, [0057-0059, 0087-0096]).
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that a second substrate opposed to the first substrate; a liquid crystal
`
`layer disposed between the first substrate and the second substrate; a first spacer provided on the
`
`second substrate; and a first laminated structure provided on the first substrate, wherein the first spacer
`
`is located between the two adjacent transistors among the plurality of transistors in each of the plurality
`
`of pixels, the first laminated structure is provided opposite to the first spacer as taught by Son et al. for
`
`

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`Application/Control Number: 16/154,287
`Art Unit: 2871
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`Page 4
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`the system of Zhang et al. since this would help to provide a widely used a LCD device with low
`
`consumption power and maintain a constant distance between the array substrate and the color filter
`
`substrate, and the pixel region is prevented from being damaged when an external force is applied and
`
`the spacers are shifted (Son et al., [0005, 0010, 0078, 0012]).
`
`Sasaki teaches that (Fig. 1-7D) each of the plurality of transistors (Fig. 1 and 7A) includes a
`
`semiconductor layer (24d/52/54/56 in Fig. 1, 4A-4D and 7A, [0069, 0111, 0116]); the first laminated
`
`structure (Fig. 2A-2C) includes a first film (28 in Fig. 2A-2C, [0073, 0074]) formed in a same layer (Fig. 3A-
`
`3D, [0074]) as that of the gate electrode (Fig. 1, 3A and 7A, [0069]) and a second film (Fig. 2A-2C) formed
`
`in a same layer (Fig. 4A-4D) as that of one of the semiconductor layer (24d/52/54/56 in Fig. 1, 4A-4D and
`
`7A, [0069, 0111, 0116]) and the source and drain electrode (58 in Fig. 1, 4A-4D and 7A, [0108]).
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that each of the plurality of transistors includes a semiconductor
`
`layer; the first laminated structure includes a first film formed in a same layer as that of the gate
`
`electrode and a second film formed in a same layer as that of one of the semiconductor layer and the
`
`source and drain electrode as taught by Sasaki for the system of Zhang et al. in view of Son et al. since
`
`this would help to provide a touch-type liquid crystal display apparatus with a built-in contact through
`
`the same manufacturing steps as those of the thin film transistor during the formation of the thin film
`
`transistors (Sasaki, [0038, 0103]).
`
`Re claim 2, Zhang et al. does not teaches that the first laminated structure includes a third film
`
`formed in a same layer as that of the other of the semiconductor layer and the source and drain
`
`electrode.
`
`Sasaki teaches that (Fig. 1-7D) the first laminated structure (Fig. 2A-2C) includes a third film (Fig.
`
`2A-2C) formed in a same layer (Fig. 4A-4D) as that of the other of the semiconductor layer
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`

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`Art Unit: 2871
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`Page 5
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`(24d/52/54/56 in Fig. 1, 4A-4D and 7A, [0069, 0111, 0116]) and the source and drain electrode (58 in Fig.
`
`1, 4A-4D and 7A, [0108]).
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that the first laminated structure includes a third film formed in a
`
`same layer as that of the other of the semiconductor layer and the source and drain electrode as taught
`
`by Sasaki for the system of Zhang et al. in view of Son et al. and Sasaki since this would help to provide a
`
`touch-type liquid crystal display apparatus with a built-in contact through the same manufacturing steps
`
`as those of the thin film transistor during the formation of the thin film transistors (Sasaki, [0038, 0103]).
`
`Re claim 3, Zhang et al. does not teaches that the second film is formed in a same layer as that
`
`of the semiconductor layer, the third film is formed in a same layer as that of the source and drain
`
`electrode, and the first film, the second film, and the third film are laminated in this order from a
`
`bottom to a top.
`
`Sasaki teaches that (Fig. 1-7D) the second film (Fig. 2A-2C) is formed in a same layer (Fig. 4A-4D)
`
`as that of the semiconductor layer (24d/52/54/56 in Fig. 1, 4A-4D and 7A, [0069, 0111, 0116]), the third
`
`film (Fig. 2A-2C) is formed in a same layer (Fig. 4A-4D) as that of the source and drain electrode (58 in
`
`Fig. 1, 4A-4D and 7A, [0108]), and the first film (28 in Fig. 2A-2C, [0073, 0074]), the second film
`
`(24d/52/54/56 in Fig. 1, 4A-4D and 7A, [0069, 0111, 0116]), and the third film are (58 in Fig. 1, 4A-4D
`
`and 7A, [0108]) laminated in this order from a bottom to a top.
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that the second film is formed in a same layer as that of the
`
`semiconductor layer, the third film is formed in a same layer as that of the source and drain electrode,
`
`and the first film, the second film, and the third film are laminated in this order from a bottom to a top
`
`as taught by Sasaki for the system of Zhang et al. in view of Son et al. and Sasaki since this would help to
`
`

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`Application/Control Number: 16/154,287
`Art Unit: 2871
`
`Page 6
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`provide a touch-type liquid crystal display apparatus with a built-in contact through the same
`
`manufacturing steps as those of the thin film transistor during the formation of the thin film transistors
`
`(Sasaki, [0038, 0103]).
`
`Re claim 4, Zhang et al. already teaches the two adjacent transistors (Fig. 10) in planar view (Fig.
`
`10). Zhang et al. does not teach that a part of the first spacer overlaps a part of the two adjacent
`
`transistors in planar view.
`
`Son et al. teaches that a part (Fig. 4) of the first spacer (194 and/or 192 in Fig. 4-7D, [0099, 0057-
`
`0059, 0087-0096]) overlaps (Fig. 4) a part (Fig. 4) of the two adjacent transistors (Fig. 4) in planar view
`
`(Fig. 4).
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that a part of the first spacer overlaps a part of the two adjacent
`
`transistors in planar view as taught by Son et al. for the system of Zhang et al. in view of Son et al. and
`
`Sasaki since this would help to maintain a constant distance between the array substrate and the color
`
`filter substrate, and the pixel region is prevented from being damaged when an external force is applied
`
`and the spacers are shifted (Son et al., [0010, 0078, 0012]).
`
`Re claim 5, Zhang et al. already teaches the two adjacent transistors (Fig. 10) in planar view (Fig.
`
`10). Zhang et al. does not teach that the first spacer does not overlap the two adjacent transistors in
`
`planar view.
`
`Sasaki teaches that (Fig. 1-7D) the first spacer (Fig. 1-2C) does not overlap (Fig. 1) the two
`
`adjacent transistors (Fig. 1) in planar view (Fig. 1).
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that the first spacer does not overlap the two adjacent transistors in
`
`

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`Application/Control Number: 16/154,287
`Art Unit: 2871
`
`Page 7
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`planar view as taught by Sasaki for the system of Zhang et al. in view of Son et al. and Sasaki since this
`
`would help to provide a touch-type liquid crystal display apparatus with a built-in contact through the
`
`same manufacturing steps as those of the thin film transistor during the formation of the thin film
`
`transistors (Sasaki, [0038, 0103]).
`
`Re claim 6, Zhang et al. does not teach that a second spacer provided on the second substrate,
`
`wherein a leading end of the second spacer contacts with the first substrate, and a leading end of the
`
`first spacer does not contact with the first substrate.
`
`Son et al. teaches that a leading end (Fig. 6A) of the first spacer (194 and/or 192 in Fig. 4-7D,
`
`[0099, 0057-0059, 0087-0096]) does not contact (Fig. 6A) with the first substrate (Fig. 6A).
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that a part of the first spacer overlaps a part of the two adjacent
`
`transistors in planar view as taught by Son et al. for the system of Zhang et al. in view of Son et al. and
`
`Sasaki since this would help that the pixel region is prevented from being damaged when an external
`
`force is applied and the spacers are shifted (Son et al., [0078, 0012]).
`
`Sasaki teaches that (Fig. 1-7D) a second spacer (16 in Fig. 1 and 2A, abs, [0060]) provided on the
`
`second substrate (Fig. 2A), wherein a leading end (Fig. 2A)of the second spacer (16 in Fig. 1 and 2A, abs,
`
`[0060]) contacts (Fig. 2A) with the first substrate (Fig. 2A),
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that a second spacer provided on the second substrate, wherein a
`
`leading end of the second spacer contacts with the first substrate as taught by Sasaki for the system of
`
`Zhang et al. in view of Son et al. and Sasaki since this would help to support the first and second
`
`substrates in such a manner as to separate the first and second substrates from each other in parallel to
`
`

`

`Application/Control Number: 16/154,287
`Art Unit: 2871
`
`Page 8
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`each other for a touch-type liquid crystal display apparatus with a built-in contact (Sasaki, [0060, 0007,
`
`0038]).
`
`Re claim 7, Zhang et al. also teaches that ([0044, 0015]) each display region on the first substrate
`
`includes a pixel electrode and a common electrode ([0044]), the pixel electrode and the common
`
`electrode ([0044]) are separated from each other by an insulating layer ([0044]), and the pixel electrode
`
`may be disposed above the common electrode or below the common electrode ([0044]). Zhang et al.
`
`does not teach that a second laminated structure provided on the first substrate at a position opposed
`
`to the second spacer, wherein the second laminated structure has a structure in which a metal layer is
`
`further laminated on a laminated structure identical to that of the first laminated structure.
`
`Sasaki teaches that a second laminated structure (Fig. 1 and 2A, abs, [0060]) provided on the
`
`first substrate (Fig. 2A) at a position opposed to the second spacer (16 in Fig. 1 and 2A, abs, [0060]),
`
`wherein the second laminated structure (Fig. 1 and 2A, abs, [0060]) has a structure (Fig. 2A) in which a
`
`step height layer (30b in Fig. 2A, [0120]) is further laminated on a laminated structure (the laminated
`
`stricture of 28, 52, 54, 56 and 58 in Fig. 2A, or the laminated stricture of 28, 50, 52, 54, 56, 58, 60 and 62
`
`in Fig. 2A) identical to that (the laminated stricture of 28, 52, 54, 56 and 58 in Fig. 23-2C, or the
`
`laminated stricture of 28, 50, 52, 54, 56, 58, 60 and 62 in Fig. 23-2C) of the first laminated structure (Fig.
`
`ZB-ZC).
`
`Son et al. teaches that a step height layer (174 in Fig. 6A-6B, [0060, 0064, 0078]) is a metal layer
`
`of a common line (Fig. 6A-6B, [0060, 0064, 0078]) above the common electrode (172 in Fig. 6A).
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that a second laminated structure provided on the first substrate at a
`
`position opposed to the second spacer, wherein the second laminated structure has a structure in which
`
`a step height layer is further laminated on a laminated structure identical to that of the first laminated
`
`

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`Application/Control Number: 16/154,287
`Art Unit: 2871
`
`Page 9
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`structure as taught by Sasaki and employ that a step height layer is a metal layer of a common line
`
`above the common electrode as taught by Son et al. for the system of Zhang et al. in view of Son et al.
`
`and Sasaki such that a metal layer of a common line above the common electrode, a second laminated
`
`structure provided on the first substrate at a position opposed to the second spacer, wherein the second
`
`laminated structure has a structure in which the metal layer is further laminated on a laminated
`
`structure identical to that of the first laminated structure since this would help to support the first and
`
`second substrates in such a manner as to separate the first and second substrates from each other in
`
`parallel to each other for a touch-type liquid crystal display apparatus with a built-in contact (Sasaki,
`
`[0060, 0007, 0038]), and it helps to electrically connect to common electrode through a metal wiring
`
`have relatively low resistivity and provide a widely used a LCD device with low consumption power, and
`
`the pixel region is prevented from being damaged when an external force is applied and the spacers are
`
`shifted (Son et al., [0057, 0010, 0078, 0012]).
`
`Re claim 8, Zhang et al. also teaches that (Fig. 10, [0044, 0015, 0057]) a plurality of pixel
`
`electrodes (Fig. 10, [0044, 0057]) provided in corresponding one of the plurality of pixels (Fig. 10, ([0044,
`
`0057]); a common electrode ([0044]) that is opposed to the plurality of pixel electrodes (Fig. 10, [0044,
`
`0057]) and provided across the plurality of pixels (Fig. 10, [0057, 0044]); and a common line ([0003])
`
`electrically connected to the common electrode ([0003]). Zhang et al. does not teach that the common
`
`line provided above the common electrode and wherein the metal layer is the common line. As stated in
`
`the rejection of claim 7 above, Zhang et al. in view of Son et al. and Sasaki teaches that the common line
`
`provided above the common electrode and wherein the metal layer is the common line.
`
`

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`Application/Control Number: 16/154,287
`Art Unit: 2871
`
`Page 10
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`Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. in view
`
`of Son et al. and Sasaki as applied to claim 6 above, and further in view of Chen et al. (US
`
`2010/0110022).
`
`Re claims 9 and 10, Zhang et al. in view of Son et al. and Sasaki already teaches that the first
`
`spacer, the second spacer, the leading end of the second spacer contacts with the first substrate, and
`
`the leading end of the first spacer does not contact with the first substrate as stated in the rejection of
`
`claim 6.
`
`Chen et al. teaches that a leading end of a second spacer (228a in Fig. 2A-ZB) contacts with the
`
`first substrate (Fig. 23), a leading end of a first spacer (228b/228c/228d in Fig. 2A-ZB) does not contact
`
`with the first substrate (Fig. 23), a height (Fig. 23) of the first spacer (228b/228c/228d in Fig. 2A-ZB) is
`
`different (Fig. 23) from a height (Fig. 23) of the second spacer (228a in Fig. 2A-ZB) and an area of the
`
`leading end of the first spacer (228b/228c/228d in Fig. 2A-ZB) is larger than (Fig. 23, Fig. 2A, Fig. 3A-SB)
`
`an area of the leading end of the second spacer (228a in Fig. 2A-ZB) in planar view.
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that a leading end of a second spacer contacts with the first substrate,
`
`a leading end of a first spacer does not contact with the first substrate, a height of the first spacer is
`
`different from a height of the second spacer and an area of the leading end of the first spacer is larger
`
`than an area of the leading end of the second spacer in planar view as taught by Chen et al. for the
`
`system of Zhang et al. in view of Son et al. and Sasaki such that a height of the first spacer of the system
`
`of Zhang et al. in view of Son et al. and Sasaki is different from a height of the second spacer of the
`
`system of Zhang et al. in view of Son et al. and Sasaki and an area of the leading end of the first spacer of
`
`the system of Zhang et al. in view of Son et al. and Sasaki is larger than an area of the leading end of the
`
`second spacer of the system of Zhang et al. in view of Son et al. and Sasaki in planar view since this
`
`would help to provide a touch display panel with stronger support thereof, increasing press-resistant
`
`

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`Application/Control Number: 16/154,287
`Art Unit: 2871
`
`Page 11
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`capability and longer lifetime, meanwhile keeping the current inducting sensitivity of the touch panel
`
`itself (Chen et al., [0013]).
`
`Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US
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`2014/0118652) in view of Son at al. (US 2014/0168554) and Sasaki (US 2012/0057119).
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`Re claim 11, Zhang et al. teaches that a liquid crystal display panel (Fig. 10, abs, [0007, 0063,
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`0036, 0057-0062, 0003, 0044]) comprising:
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`a plurality of pixels (Abs, [0007, 0039] Fig. 10) arranged in a matrix (Abs, [0007, 0039] Fig. 10);
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`a first substrate (Abs, [0007, 0039], Fig. 10);
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`a plurality of transistors (Fig. 10, Abs, [0057]) provided on the first substrate (Abs, [0007, 0039],
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`Fig. 10) in each of the plurality of pixels (Abs, [0007, 0039] Fig. 10);
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`an insulator ([0044, 0015]); and
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`a metal layer (the layer of the common electrode line, [0003]),
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`wherein
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`each of the plurality of transistors (Fig. 10, Abs, [0057]) includes a gate electrode (Fig. 10, [0041,
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`0049]), and a source and drain electrode (Fig. 10, [0041, 0049]).
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`Zhang et al. does not explicitly point out that a second substrate opposed to the first substrate;
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`a liquid crystal layer disposed between the first substrate and the second substrate; the insulator
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`covering the transistor; the metal layer formed on the insulating film, each of the plurality of transistors
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`includes a semiconductor layer. Zhang et al. also does not teach that a first spacer that is provided on
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`the second substrate and has a leading end that does not contact with the first substrate; a second
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`spacer that is provided on the second substrate and has a leading end that contacts with the first
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`substrate; a first laminated structure provided on the first substrate; a second laminated structure
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`provided on the first substrate; the first laminated structure is provided opposite to the first spacer, the
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`second laminated structure is provided opposite to the second spacer, the first laminated structure
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`includes a first film formed in a same layer as that of the gate electrode, a second film formed in a same
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`layer as that of the semiconductor layer, and a third film formed in a same layer as that of the source
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`and drain electrode, and the second laminated structure includes the first film formed in a same layer as
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`that of the gate electrode, the second film formed in a same layer as that of the semiconductor layer,
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`and the third film formed in a same layer as that of the source and drain electrode, and a fourth film
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`formed in a same layer as that of the metal layer.
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`Son et al. teaches that a second substrate (Fig. 6A) opposed to the first substrate (Fig. 6A); a
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`liquid crystal layer (Fig. 6A, [0009, 0090]) disposed between the first substrate (Fig. 6A) and the second
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`substrate (Fig. 6A); the insulator (180 in Fig. 5-6A, [0076]) covering the transistor (Fig. 5); the metal layer
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`(174 in Fig. 6A-6B, [0060, 0064, 0078]) formed on the insulating film (180 in Fig. 5-6A, [0076]).
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`Before the effective filling date of the claimed invention, it would have been obvious to the
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`artisan of ordinary skill to employ that a second substrate opposed to the first substrate; a liquid crystal
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`layer disposed between the first substrate and the second substrate; the insulator covering the
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`transistor; the metal layer formed on the insulating film as taught by Son et al. for the system of Zhang
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`et al. since this would help to provide a widely used a LCD device with low consumption power, and the
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`pixel region is prevented from being damaged when an external force is applied and the spacers are
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`shifted (Son et al., [0005, 0010, 0078, 0012]).
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`Sasaki teaches that (Fig. 1-7D) each of the plurality of transistors (Fig. 1 and 7A) includes a
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`semiconductor layer (24d/52/54/56 in Fig. 1, 4A-4D and 7A, [0069, 0111, 0116]); a first spacer (TPS in
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`Fig. 1 and 23-2C, [0079, 0080, 0090]) that is provided on the second substrate (Fig. 23-2C) and has a
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`leading end (Fig. 23-2C) that does not contact (Fig. 23-2C) with the first substrate (Fig. 23-2C); a second
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`spacer (16 in Fig. 1 and 2A, abs, [0060]) that is provided on the second substrate (Fig. 2A) and has a
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`leading end (Fig. 2A) that contacts (Fig. 2A) with the first substrate (Fig. 2A); a first laminated structure
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`(Fig. 23-2C) provided on the first substrate (Fig. 23-2C); a second laminated structure (Fig. 2A) provided
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`on the first substrate (Fig. 2A); the first laminated structure (Fig. 23-2C) is provided opposite to the first
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`spacer (TPS in Fig. 1 and 23-2C, [0079, 0080, 0090]), the second laminated structure (Fig. 2A) is provided
`
`opposite to the second spacer (16 in Fig. 1 and 2A, abs, [0060]), the first laminated structure (Fig. ZB-2C)
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`includes a first film (28in Fig. 23-2C, [0073, 0074]) formed in a same layer (Fig. 3A-3D, [0074]) as that of
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`the gate electrode (Fig. 1, 3A and 7A, [0069]), a second film (52/54/56 in Fig. 23-2C, 4A-4D and 7A,
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`[0069, 0111, 0116]) formed in a same layer as that of the semiconductor layer (24d/52/54/56 in Fig. 1,
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`4A-4D and 7A, [0069, 0111, 0116]), and a third film (58 in Fig. 1, 23-2C, 4A-4D and 7A, [0108]) formed in
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`a same layer as that of the source and drain electrode (58 in Fig. 1, 23-2C, 4A-4D and 7A, [0108]), and
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`the second laminated structure (Fig. 2A) includes the first film (28 in Fig. 2A, [0073, 0074]) formed in a
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`same layer as that of the gate electrode (Fig. 1, 3A and 7A, [0069]), the second film (52/54/56 in Fig. 2A,
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`4A-4D and 7A, [0069, 0111, 0116]) formed in a same layer as that of the semiconductor layer (52/54/56
`
`in Fig. ZB-ZC, 4A-4D and 7A, [0069, 0111, 0116]), and the third film (58in Fig. 1, 2A, 4A-4D and 7A,
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`[0108]) formed in a same layer as that of the source and drain electrode (58 in Fig. 1, 23-2C, 4A-4D and
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`7A, [0108]), and a fourth film (30b in Fig. 2A, [0120]) formed as a step height layer (30b in Fig. 2A,
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`[0120]).
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`Son et al. teaches that a step height layer (174 in Fig. 6A-6B, [0060, 0064, 0078]) is a metal layer
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`of a common line (Fig. 6A-6B, [0060, 0064, 0078]) above the common electrode (172 in Fig. 6A).
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that each of the plurality of transistors includes a semiconductor
`
`layer; a first spacer that is provided on the second substrate and has a leading end that does not contact
`
`with the first substrate; a second spacer that is provided on the second substrate and has a leading end
`
`that contacts with the first substrate; a first laminated structure provided on the first substrate; a
`
`second laminated structure provided on the first substrate; the first laminated structure is provided
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`opposite to the first spacer, the second laminated structure is provided opposite to the second spacer,
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`the first laminated structure includes a first film formed in a same layer as that of the gate electrode, a
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`second film formed in a same layer as that of the semiconductor layer, and a third film formed in a same
`
`layer as that of the source and drain electrode, and the second laminated structure includes the first
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`film formed in a same layer as that of the gate electrode, the second film formed in a same layer as that
`
`of the semiconductor layer, and the third film formed in a same layer as that of the source and drain
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`electrode, and a fourth film formed as a step height layer as taught by Sasaki and employ that a step
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`height layer is a metal layer of a common line above the common electrode as taught by Son et al. for
`
`the system of Zhang et al. in view of Son et al. and Sasaki such that each of the plurality of transistors
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`includes a semiconductor layer; a first spacer that is provided on the second substrate and has a leading
`
`end that does not contact with the first substrate; a second spacer that is provided on the second
`
`substrate and has a leading end that contacts with the first substrate; a first laminated structure
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`provided on the first substrate; a second laminated structure provided on the first substrate; the first
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`laminated structure is provided opposite to the first spacer, the second laminated