`
`V i$ T {a
`
`A
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 2231371450
`www.uspto.gov
`
`16/154,287
`
`10/08/2018
`
`Takashi MIBU
`
`20295.0024U501
`
`1754
`
`53148
`
`759°
`
`11/25/2019
`
`HAMRE, SCHUMANN, MUELLER & LARSON RC.
`45 South Seventh Street
`Suite 2700
`
`MINNEAPOLIS, MN 55402-1683
`
`LIU' SHAN
`
`2871
`
`PAPER NUMBER
`
`NOTIFICATION DATE
`
`DELIVERY MODE
`
`11/25/2019
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above—indicated "Notification Date" to the
`
`following e—mail address(es):
`PTOMai1@hsml.eom
`
`PTOL-90A (Rev. 04/07)
`
`

`

`0/7709 A0170” Summary
`
`Application No.
`16/154,287
`Examiner
`SHAN LIU
`
`Applicant(s)
`MIBU, Takashi
`Art Unit
`2871
`
`AIA (FITF) Status
`Yes
`
`- The MAILING DA TE of this communication appears on the cover sheet wit/7 the correspondence address -
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE g MONTHS FROM THE MAILING
`DATE OF THIS COMMUNICATION.
`Extensions of time may be available under the provisions of 37 CFR 1.136(a). In no event, however, may a reply be timely filed after SIX (6) MONTHS from the mailing
`date of this communication.
`|f NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any earned patent term
`adjustment. See 37 CFR 1.704(b).
`
`Status
`
`1). Responsive to communication(s) filed on 10/31/2019.
`CI A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/were filed on
`
`2a). This action is FINAL.
`
`2b) D This action is non-final.
`
`3)[:] An election was made by the applicant in response to a restriction requirement set forth during the interview
`on
`; the restriction requirement and election have been incorporated into this action.
`
`4):] Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Expade Quay/e, 1935 CD. 11, 453 O.G. 213.
`
`Disposition of Claims*
`
`5)
`
`Claim(s)
`
`1—10 and 13 is/are pending in the application.
`
`5a) Of the above claim(s)
`
`is/are withdrawn from consideration.
`
`
`
`[:1 Claim(ss)
`
`is/are allowed.
`
`Claim(ss) 1— 10 and 13 is/are rejected.
`
`D Claim(ss_) is/are objected to.
`
`) ) ) )
`
`S)
`are subject to restriction and/or election requirement
`[:1 Claim(s
`* If any claims have been determined aflowable. you may be eligible to benefit from the Patent Prosecution Highway program at a
`
`participating intellectual property office for the corresponding application. For more information, please see
`
`http://www.uspto.gov/patents/init events/pph/index.jsp or send an inquiry to PPeredback@uspto.gov.
`
`Application Papers
`
`10)|:l The specification is objected to by the Examiner.
`
`is/are: a)[] accepted or b)l:] objected to by the Examiner.
`11)[:] The drawing(s) filed on
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`
`12). Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
`Certified copies:
`
`a). All
`
`b)|:] Some**
`
`c)l:i None of the:
`
`1.. Certified copies of the priority documents have been received.
`
`2C] Certified copies of the priority documents have been received in Application No.
`
`3D Copies of the certified copies of the priority documents have been received in this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`
`** See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`1)
`
`Notice of References Cited (PTO-892)
`
`2) C] Information Disclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`Paper No(s)/Mail Date_
`U.S. Patent and Trademark Office
`
`3) E] Interview Summary (PTO-413)
`Paper No(s)/Mail Date
`4) CI Other-
`
`PTOL-326 (Rev. 11-13)
`
`Office Action Summary
`
`Part of Paper No./Mai| Date 20191118
`
`

`

`Application/Control Number: 16/154,287
`Art Unit: 2871
`
`Page 2
`
`Notice of Pre-AIA or AIA Status
`
`The present application, filed on or after March 16, 2013, is being examined under the first
`
`inventor to file provisions of the AIA.
`
`Response to Amendment
`
`The amendment filed 10/31/2019 has been entered. Claims 12-13 are cancelled, claims 1, 4-5,
`
`7-8 and 10 are amended, and new claim 13 is added. Claims 1-10 and 13 are currently pending in this
`
`application.
`
`In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102
`
`and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory
`
`basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and
`
`the rationale supporting the rejection, would be the same under either status.
`
`Claim Rejections - 35 USC § 103
`
`The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections
`
`set forth in this Office action:
`
`A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is
`not identically disclosed as set forth in section 102 of this title, if the differences between the claimed
`invention and the prior art are such that the claimed invention as a whole would have been obvious
`before the effective filing date of the claimed invention to a person having ordinary skill in the art to
`which the claimed invention pertains. Patentability shall not be negated by the manner in which the
`invention was made.
`
`Claims 1-3, 5, 13 are rejected under 35 U.S.C. 103 as being unpatentable over Jean at al. (US
`
`2010/0134731) in view of Sasaki (US 2012/0057119).
`
`Re claim 1, Jeon et al. teaches that a liquid crystal display panel (Fig. 1-4, [0034-0066]) having a
`
`plurality of pixels arranged in a matrix (Fig. 1-3) comprising:
`
`a first substrate (110 in Fig. 4, [0046]);
`
`

`

`Application/Control Number: 16/154,287
`Art Unit: 2871
`
`Page 3
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`a second substrate (210 in Fig. 4, [0075]) opposed to the first substrate (110 in Fig. 4, [0046]);
`
`a liquid crystal layer (3 in Fig. 4, [0036]) disposed between the first substrate and the second
`
`substrate (Fig. 4, [0036]);
`
`a plurality of transistors (Qa and Qb in Fig. 2-3, [0041]) provided on the first substrate (110 in
`
`Fig. 4, [0046]) in one of the plurality of pixels (Fig. 1-3);
`
`a first spacer (the spacer 363 contact 100 and 200 in Fig. 3-4, [0076, 0077, 0085]) provided on
`
`the second substrate (210 in Fig. 4, [0075]); and
`
`a first laminated structure (the portions of 180q, 230, 180p, 140 and 121 overlapping with 363 in
`
`Fig. 4) provided on the first substrate (110 in Fig. 4, [0046]),
`
`wherein
`
`in a plan view (Fig. 3), the first spacer (363 in Fig. 3-4, [0076, 0077, 0085]) is located between
`
`two adjacent transistors (Qa and Qb in Fig. 2-3, [0041]) among the plurality of transistors (Qa and Qb in
`
`Fig. 2-3, [0041]),
`
`in the plan view (Fig. 3), the first laminated structure (the portions of 180p, 140 and 121
`
`overlapping with 363 in Fig. 4) is located between the two adjacent transistors (Qa and Qb in Fig. 2-3,
`
`[0041]) among the plurality of transistors (Qa and Qb in Fig. 2-3, [0041]), and is provided opposite to
`
`(Fig. 4) the first spacer (363 in Fig. 3-4, [0076, 0077, 0085]),
`
`each of the plurality of transistors (Qa and Qb in Fig. 2-3, [0041]) includes a gate electrode
`
`(124a/124b in Fig. 3, [0046]), a semiconductor layer (154a/154b in Fig. 3, [0048-0049]) and a source and
`
`drain electrode (173a/173b/175a/175b in Fig. 3, [0050-0054]), and
`
`the first laminated structure (the portions of 180p, 140 and 121 overlapping with 363 in Fig. 4)
`
`includes a first film (the portion of 121 overlapping with 363 in Fig. 3-4, [0076]) formed in a same layer
`
`as that of the gate electrode (124a/124b in Fig. 3, [0046]).
`
`

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`Application/Control Number: 16/154,287
`Art Unit: 2871
`
`Page 4
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`Jeon et al. already teaches that the first spacer (363 in Fig. 3-4, [0076, 0077, 0085]) is a cell gap
`
`maintaining spacer (Fig. 4) and located between two adjacent transistors (Qa and Qb in Fig. 2-3, [0041]),
`
`and the first laminated structure (the portions of 180p, 140 and 121 overlapping with 363 in Fig. 4) is
`
`provided opposite to (Fig. 4) the first spacer (363 in Fig. 3-4, [0076, 0077, 0085]). Jeon et al. does not
`
`teach that the first laminated structure includes a second film formed in a same layer as that of one of
`
`the semiconductor layer and the source and drain electrode.
`
`Sasaki teaches that (Fig. 1-7D, Fig. 9) teaches that a first spacer (16 in Fig. 1 and 2A, abs, [0060])
`
`is provided as a cell gap maintaining unit (Fig. 2A, abs, [0060]) and second spacers (TPS in Fig. 1 and 23-
`
`2C, [0079, 0080, 0090]) are provided as a touch detection unit (Fig. 1 and 23-2C, [0079, 0080, 0090]), a
`
`first laminated structure (Fig. 2A) is provided opposite to the first spacer (16 in Fig. 1 and 2A, abs,
`
`[0060]), the first laminated structure (Fig. 2A) includes a first film (28 in Fig. 2A, [0073, 0074]) formed in
`
`a same layer (Fig. 3A-3D, [0074]) as that of the gate electrode (Fig. 1, 3A and 7A, [0069]) and a second
`
`film (Fig. 2A) formed in a same layer (Fig. 4A-4D) as that of one of the semiconductor layer
`
`(24d/52/54/56 in Fig. 1, 4A-4D and 7A, [0069, 0111, 0116]) and the source and drain electrode (58 in Fig.
`
`1, 4A-4D and 7A, [0108]).
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that a first spacer is provided as a cell gap maintaining unit and second
`
`spacers are provided as a touch detection unit, a first laminated structure is provided opposite to the
`
`first spacer; the first laminated structure includes a first film formed in a same layer as that of the gate
`
`electrode and a second film formed in a same layer as that of one of the semiconductor layer and the
`
`source and drain electrode as taught by Sasaki for the system ofJeon et al. such that second spacers are
`
`provided as a touch detection unit, a first laminated structure is provided opposite to the first spacer
`
`and the first laminated structure includes a first film formed in a same layer as that of the gate electrode
`
`and a second film formed in a same layer as that of one of the semiconductor layer and the source and
`
`

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`Application/Control Number: 16/154,287
`Art Unit: 2871
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`Page 5
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`drain electrode since this would help to provide a touch-type liquid crystal display apparatus with a
`
`built-in contact through the same manufacturing steps as those of the thin film transistor during the
`
`formation of the thin film transistors, and the cell gap maintaining spacer and the touch detection
`
`spacer can be formed by the same/simple manufacturing steps and have same dimensional accuracy
`
`(Sasaki, [0038, 0103, 0091, 0035]).
`
`Re claim 2, Jeon et al. does not teaches that the first laminated structure includes a third film
`
`formed in a same layer as that of the other of the semiconductor layer and the source and drain
`
`electrode.
`
`Sasaki teaches that (Fig. 1-7D) the first laminated structure (Fig. 2A) includes a third film (Fig. 2A)
`
`formed in a same layer (Fig. 4A-4D) as that of the other of the semiconductor layer (24d/52/54/56 in Fig.
`
`1, 4A-4D and 7A, [0069, 0111, 0116]) and the source and drain electrode (58 in Fig. 1, 4A-4D and 7A,
`
`[0108]).
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that the first laminated structure includes a third film formed in a
`
`same layer as that of the other of the semiconductor layer and the source and drain electrode as taught
`
`by Sasaki for the system of Jeon et al. in view of Sasaki since this would help to provide a touch-type
`
`liquid crystal display apparatus with a built-in contact through the same manufacturing steps as those of
`
`the thin film transistor during the formation of the thin film transistors, and the cell gap maintaining
`
`spacer and the touch detection spacer can be formed by the same/simple manufacturing steps and have
`
`same dimensional accuracy (Sasaki, [0038, 0103, 0091, 0035]).
`
`Re claim 3, Jeon et al. does not teaches that the second film is formed in a same layer as that of
`
`the semiconductor layer, the third film is formed in a same layer as that of the source and drain
`
`

`

`Application/Control Number: 16/154,287
`Art Unit: 2871
`
`Page 6
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`electrode, and the first film, the second film, and the third film are laminated in this order from a
`
`bottom to a top.
`
`Sasaki teaches that (Fig. 1-7D) the second film (52/54/56 in Fig. 2A, [0069, 0111, 0116]) is
`
`formed in a same layer (Fig. 1-4D) as that of the semiconductor layer (24d/52/54/56 in Fig. 1, 4A-4D and
`
`7A, [0069, 0111, 0116]), the third film (58 in Fig. 2A, [0108]) is formed in a same layer (Fig. 1-4D) as that
`
`of the source and drain electrode (58 in Fig. 1, 4A-4D and 7A, [0108]), and the first film (28 in Fig. 2A,
`
`[0073, 0074]), the second film (52/54/56 in Fig. 2A, [0069, 0111, 0116]), and the third film are (58 in Fig.
`
`2A, [0108]) laminated in this order from a bottom to a top.
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that the second film is formed in a same layer as that of the
`
`semiconductor layer, the third film is formed in a same layer as that of the source and drain electrode,
`
`and the first film, the second film, and the third film are laminated in this order from a bottom to a top
`
`as taught by Sasaki for the system of Jeon et al. in view of Sasaki since this would help to provide a
`
`touch-type liquid crystal display apparatus with a built-in contact through the same manufacturing steps
`
`as those of the thin film transistor during the formation of the thin film transistors, and the cell gap
`
`maintaining spacer and the touch detection spacer can be formed by the same/simple manufacturing
`
`steps and have same dimensional accuracy (Sasaki, [0038, 0103, 0091, 0035]).
`
`Re claim 5, Jeon et al. also teaches that the first spacer (the spacer 363 contact 100 and 200 in
`
`Fig. 3-4, [0076, 0077, 0085]) does not overlap (Fig. 3-4) the two adjacent transistors (Qa and Qb in Fig. 2-
`
`3, [0041]) in the plan planar view (Fig. 3).
`
`

`

`Application/Control Number: 16/154,287
`Art Unit: 2871
`
`Page 7
`
`Re claim 13, Jeon et al. does not teaches that the first film is spaced apart from the gate
`
`electrode, the second film is spaced apart from the semiconductor layer, and the third film is spaced
`
`apart from the source and drain electrode.
`
`Sasaki teaches that (Fig. 1-7D) the first film (28 in Fig. 2A, [0073, 0074]) is spaced apart (Fig. 1-
`
`3D, [0105]) from the gate electrode (Fig. 1), the second film (52/54/56 in Fig. 2A, [0069, 0111, 0116]) is
`
`spaced apart (Fig. 1-4D) from the semiconductor layer (24d/52/54/56 in Fig. 1, 4A-4D and 7A, [0069,
`
`0111, 0116]), and the third film (58 in Fig. 2A, [0108]) is spaced apart (Fig. 1-4D) from the source and
`
`drain electrode (58 in Fig. 1, 4A-4D and 7A, [0108]).
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that the first film is spaced apart from the gate electrode, the second
`
`film is spaced apart from the semiconductor layer, and the third film is spaced apart from the source
`
`and drain electrode as taught by Sasaki for the system ofJeon et al. in view of Sasaki since this would
`
`help to provide a touch-type liquid crystal display apparatus with a built-in contact through the same
`
`manufacturing steps as those of the thin film transistor during the formation of the thin film transistors,
`
`and the cell gap maintaining spacer and the touch detection spacer can be formed by the same/simple
`
`manufacturing steps and have same dimensional accuracy (Sasaki, [0038, 0103, 0091, 0035]).
`
`Claims 1, 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Son at al. (US
`
`2014/0168554) in view of Sasaki (US 2012/0057119).
`
`Re claim 1, Son et al. teaches that a liquid crystal display panel (Fig. 4-7D, [0046-0104]) having a
`
`plurality of pixels arranged in a matrix (Fig. 7A-7D) comprising:
`
`a first substrate (110 in Fig. 6A-6B, [0080]);
`
`a second substrate (190 in Fig. 6A-6B, [0080]) opposed to the first substrate (110 in Fig. 6A-6B,
`
`[0080]);
`
`

`

`Application/Control Number: 16/154,287
`Art Unit: 2871
`
`Page 8
`
`a liquid crystal layer ([0017, 0090]) disposed between the first substrate and the second
`
`substrate ([0017, 0090], Fig. 6A-6B);
`
`a plurality of transistors (the thin film transistors in the pixel PXL in 7A-7D, each is located in the
`
`R G B subpixels and corresponding to the thin film transistor T in Fig. 4-5, [0054, 0099]) provided on the
`
`first substrate (110 in Fig. 6A-6B, [0080]) in one of the plurality of pixels (one pixel of PXL in Fig. 7A-7D;
`
`[0099]),
`
`a first spacer (194 in Fig. 4-7D, [0099, 0057-0059, 0087-0096]) provided on the second substrate
`
`(190 in Fig. 6A-6B, [0080]); and
`
`a first laminated structure (the Fig. 6A, [0078]) provided on the first substrate (110 in Fig. 6A-6B,
`
`[0080]),
`
`wherein
`
`in a plan view, the first spacer (194 in Fig. 4-7D, [0099, 0057-0059, 0087-0096]) is located
`
`between two adjacent transistors (Fig. 4 and 7A-7D) among the plurality of transistors (the thin film
`
`transistors in the pixel PXL in 7A-7D, each is located in the R G B subpixels and corresponding to the thin
`
`film transistor T in Fig. 4-5, [0054, 0099]),
`
`in the plan view, the first laminated structure (the portions of 160, 152 and 130 overlapping
`
`with 192 in Fig. 6A, [0078]) is located between the two adjacent transistors (Fig. 4 and 7A-7D) among the
`
`plurality of transistors (the thin film transistors in the pixel PXL in 7A-7D, each is located in the R G B
`
`subpixels and corresponding to the thin film transistor T in Fig. 4-5, [0054, 0099]), and is provided
`
`opposite to the first spacer (194 in Fig. 4-7D, [0099, 0057-0059, 0087-0096]),
`
`each of the plurality of transistors (the thin film transistors in the pixel PXL in 7A-7D, each is
`
`located in the R G B subpixels and corresponding to the thin film transistor T in Fig. 4-5, [0054, 0099])
`
`includes a gate electrode (124 in Fig. 4-5, [0067]), an active layer (142 in Fig. 5, [0069]), and a source and
`
`drain electrode (154/156 in Fig. 4-5, [0070]).
`
`

`

`Application/Control Number: 16/154,287
`Art Unit: 2871
`
`Page 9
`
`Son et al. does not teach that each of the plurality of transistors includes a semiconductor layer,
`
`and the first laminated structure includes a first film formed in a same layer as that of the gate electrode
`
`and a second film formed in a same layer as that of one of the semiconductor layer and the source and
`
`drain electrode.
`
`Sasaki teaches that (Fig. 1-7D) each of the plurality of transistors (Fig. 1 and 7A) includes a
`
`semiconductor layer (24d/52/54/56 in Fig. 1, 4A-4D and 7A, [0069, 0111, 0116]); the first laminated
`
`structure (Fig. 2A-2C) includes a first film (28 in Fig. 2A-2C, [0073, 0074]) formed in a same layer (Fig. 3A-
`
`3D, [0074]) as that of the gate electrode (Fig. 1, 3A and 7A, [0069]) and a second film (Fig. 2A-2C) formed
`
`in a same layer (Fig. 4A-4D) as that of one of the semiconductor layer (24d/52/54/56 in Fig. 1, 4A-4D and
`
`7A, [0069, 0111, 0116]) and the source and drain electrode (58 in Fig. 1, 4A-4D and 7A, [0108]).
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that each of the plurality of transistors includes a semiconductor
`
`layer; the first laminated structure includes a first film formed in a same layer as that of the gate
`
`electrode and a second film formed in a same layer as that of one of the semiconductor layer and the
`
`source and drain electrode as taught by Sasaki for the system of Son et al. since this would help to
`
`provide a touch-type liquid crystal display apparatus with a built-in contact through the same
`
`manufacturing steps as those of the thin film transistor during the formation of the thin film transistors
`
`(Sasaki, [0038, 0103]).
`
`Re claim 4, Son et al. teaches that a part (Fig. 4) of the first spacer (194 and/or 192 in Fig. 4-7D,
`
`[0099, 0057-0059, 0087-0096]) overlaps (Fig. 4) a part (Fig. 4) of the two adjacent transistors (Fig. 4) in
`
`planar view (Fig. 4).
`
`

`

`Application/Control Number: 16/154,287
`Art Unit: 2871
`
`Page 10
`
`Re claim 6, Son et al. teaches that a second spacer (192 in Fig. 4, [0057-0059]) as a gap form
`
`spacer ([0058]), and a leading end (Fig. 6A) of the first spacer (194 in Fig. 4-7D, [0099, 0057-0059, 0087-
`
`0096]) does not contact (Fig. 6A) with the first substrate (Fig. 6A). Son et al. does explicitly point out that
`
`a second spacer provided on the second substrate, wherein a leading end of the second spacer contacts
`
`with the first substrate.
`
`Sasaki teaches that (Fig. 1-7D) a second spacer (16 in Fig. 1 and 2A, abs, [0060]) provided on the
`
`second substrate (Fig. 2A), wherein a leading end (Fig. 2A) of the second spacer (16 in Fig. 1 and 2A, abs,
`
`[0060]) contacts (Fig. 2A) with the first substrate (Fig. 2A),
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that a second spacer provided on the second substrate, wherein a
`
`leading end of the second spacer contacts with the first substrate as taught by Sasaki for the system of
`
`Son et al. in view of Sasaki since this would help to support the first and second substrates in such a
`
`manner as to separate the first and second substrates from each other in parallel to each other for a
`
`touch-type liquid crystal display apparatus with a built-in contact (Sasaki, [0060, 0007, 0038]).
`
`Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Son at al. in view of
`
`Sasaki as applied to claim 6 above, and further in view of Chen et al. (US 2010/0110022).
`
`Re claims 9 and 10, Son et al. in view of Sasaki already teaches that the first spacer, the second
`
`spacer, the leading end of the second spacer contacts with the first substrate, and the leading end of the
`
`first spacer does not contact with the first substrate as stated in the rejection of claim 6.
`
`Chen et al. teaches that a leading end of a second spacer (228a in Fig. 2A-23) contacts with the
`
`first substrate (Fig. 23), a leading end of a first spacer (228b/228c/228d in Fig. 2A-23) does not contact
`
`with the first substrate (Fig. 23), a height (Fig. 23) of the first spacer (228b/228c/228d in Fig. 2A-23) is
`
`different (Fig. 23) from a height (Fig. 23) of the second spacer (228a in Fig. 2A-23) and an area of the
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`leading end of the first spacer (228b/228c/228d in Fig. 2A-ZB) is larger than (Fig. 23, Fig. 2A, Fig. 3A-3B)
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`an area of the leading end of the second spacer (228a in Fig. 2A-ZB) in plan view.
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`Before the effective filling date of the claimed invention, it would have been obvious to the
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`artisan of ordinary skill to employ that a leading end of a second spacer contacts with the first substrate,
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`a leading end of a first spacer does not contact with the first substrate, a height of the first spacer is
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`different from a height of the second spacer and an area of the leading end of the first spacer is larger
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`than an area of the leading end of the second spacer in planar view as taught by Chen et al. for the
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`system of Son et al. in view of Sasaki such that a height of the first spacer of the system of Son et al. in
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`view of Sasaki is different from a height of the second spacer of the system of Son et al. in view of Sasaki
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`and an area of the leading end of the first spacer of the system of Son et al. in view of Sasaki is larger
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`than an area of the leading end of the second spacer of the system of Son et al. in view of Sasaki in plan
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`view since this would help to provide a touch display panel with stronger support thereof, increasing
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`press-resistant capability and longer lifetime, meanwhile keeping the current inducting sensitivity of the
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`touch panel itself (Chen et al., [0013]).
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`Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US
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`2011/0122357) in view of Sasaki (US 2012/0057119).
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`Re claim 1, Chang et al. teaches that a liquid crystal display panel (Fig. 1-2 and 5-6, [0074, 0027-
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`0073, 0075]) having a plurality of pixels arranged in a matrix (Fig. 1-2) comprising:
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`a first substrate (110 in Fig. 6, [0043]);
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`a second substrate (210 in Fig. 6, [0072]) opposed to the first substrate (110 in Fig. 6, [0043]);
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`a liquid crystal layer (3 in Fig. 6, [0030]) disposed between the first substrate and the second
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`substrate (Fig. 6, [0030]);
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`a plurality of transistors (Qa and Qb in Fig. 2 and 5, [0034-0035]) provided on the first substrate
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`(110 in Fig. 6, [0043]) in one of the plurality of pixels (Fig. 2 and Fig.5);
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`a first spacer (3635 in Fig. 5-6, [0074-0075]); and
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`a first laminated structure (the portions of 180p, 140 and 121 overlapping with 3635 in Fig. 5-6)
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`provided on the first substrate (110 in Fig. 6, [0043]),
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`wherein
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`in a plan view (Fig. 5), the first spacer (3635 in Fig. 5-6, [0074-0075]) is located between two
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`adjacent transistors (Qa and Qb in Fig. 2 and 5, [0034-0035]) among the plurality of transistors (Qa and
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`Qb in Fig. 2 and 5, [0034-0035]),
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`in the plan view (Fig. 5), the first laminated structure (the portions of 180p, 140 and 121
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`overlapping with 3635 in Fig. 5-6) is located between the two adjacent transistors (Qa and Qb in Fig. 2
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`and 5, [0034-0035]) among the plurality of transistors (Qa and Qb in Fig.2 and 5, [0034-0035]), and is
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`provided opposite to (Fig. 6) the first spacer (3635 in Fig. 5-6, [0074-0075]),
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`each of the plurality of transistors (Qa and Qb in Fig. 2 and 5, [0034-0035]) includes a gate
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`electrode (124a/124b in Fig. 5, [0044]), a semiconductor layer (154a/154b in Fig. 5, [0047-0048]) and a
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`source and drain electrode (173a/173b/175a/175b in Fig. 3, [0049-0053]), and
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`the first laminated structure (the portions of 180p, 140 and 121 overlapping with 3635 in Fig. 5-
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`6) includes a first film (the portions of 121 overlapping with 3635 in Fig. 5-6, [0044]) formed in a same
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`layer as that of the gate electrode (124a/124b in Fig. 3, [0044]).
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`Chang et al. already teaches that the first spacer (3635 in Fig. 5-6, [0074-0075]) is a assistance
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`spacer (Fig. 6, [0074-0075]), and the first spacer (3635 in Fig. 5-6, [0074-0075]) and the first laminated
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`structure (the portions of 180p, 140 and 121 overlapping with 3635 in Fig. 5-6) are located between two
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`adjacent transistors (Qa and Qb in Fig. 2 and 5, [0034-0035]). Chang et al. does not teach that the first
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`spacer provided on the second substrate; and the first laminated structure includes a second film
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`formed in a same layer as that of one of the semiconductor layer and the source and drain electrode.
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`Sasaki teaches that (Fig. 1-7D, Fig. 9) teaches that a first spacer (TPS in Fig. 1 and ZB-ZC, [0079,
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`0080, 0090]) is provided on the second substrate (Fig. ZB-ZC), the first laminated structure (Fig. ZB-ZC) is
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`provided opposite to the first spacer (TPS in Fig. 1 and ZB-ZC, [0079, 0080, 0090]), the first laminated
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`structure (Fig. ZB-ZC) includes a first film (28 in Fig. ZB-ZC, [0073, 0074]) formed in a same layer (Fig. 3A-
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`3D, [0074]) as that of the gate electrode (Fig. 1, 3A and 7A, [0069]) and a second film (Fig. ZB-ZC) formed
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`in a same layer (Fig. 4A-4D) as that of one of the semiconductor layer (24d/52/54/56 in Fig. 1, 4A-4D and
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`7A, [0069, 0111, 0116]) and the source and drain electrode (58 in Fig. 1, 4A-4D and 7A, [0108]).
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`Before the effective filling date of the claimed invention, it would have been obvious to the
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`artisan of ordinary skill to employ that a first spacer is provided on the second substrate, a first
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`laminated structure is provided opposite to the first spacer; the first laminated structure includes a first
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`film formed in a same layer as that of the gate electrode and a second film formed in a same layer as
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`that of one of the semiconductor layer and the source and drain electrode as taught by Sasaki for the
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`system of Chang et al. such that the first spacer is provided on the second substrate, the first laminated
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`structure is provided opposite to the first spacer; the first laminated structure includes a first film
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`formed in a same layer as that of the gate electrode and a second film formed in a same layer as that of
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`one of the semiconductor layer and the source and drain electrode since this would help to provide a
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`touch-type liquid crystal display apparatus with a built-in contact through the same manufacturing steps
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`as those of the thin film transistor during the formation of the thin film transistors (Sasaki, [0038, 0103]).
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`Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. in view of
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`Sasaki as applied to claim 1 above, and further in view of Son at al. (US 2014/0168554).
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`Re claim 7, Chang et al. in view of Sasaki teaches the liquid crystal display panel as recited above
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`in claim 1.
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`Sasaki also teaches that a second spacer (16 in Fig. 1 and 2A, abs, [0060]) provided on the
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`second substrate (Fig. 2A), a second laminated structure (Fig. 1 and 2A, abs, [0060]) provided on the first
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`substrate (Fig. 2A) at a position opposed to the second spacer (16 in Fig. 1 and 2A, abs, [0060]), wherein
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`the second laminated structure (Fig. 1 and 2A, abs, [0060]) has a structure (Fig. 2A) in which a step
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`height layer (30b in Fig. 2A, [0120]) is further laminated on a laminated structure (the laminated
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`stricture of 28, 52, 54, 56 and 58 in Fig. 2A, or the laminated stricture of 28, 50, 52, 54, 56, 58, 60 and 62
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`in Fig. 2A) identical to that (the laminated stricture of 28, 52, 54, 56 and 58 in Fig. 23-2C, or the
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`laminated stricture of 28, 50, 52, 54, 56, 58, 60 and 62 in Fig. 23-2C) of the first laminated structure (Fig.
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`ZB-ZC).
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`Son et al. teaches that a common electrode (172 in Fig. 6A, [0065]) is provided on the first
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`substrate (Fig. 5-6A), and a step height layer (174 and the portions of 180 covering 174 in Fig. 6A-6B,
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`[0060, 0064, 0078]) includes a metal layer (174 in Fig. 6A-6B) of a common line (Fig. 6A-6B, [0060, 0064,
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`0078]) provided above the common electrode (172 in Fig. 6A, [0065]) and electrically connected to the
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`common electrode (172 in Fig. 6A, [0065]).
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`Before the effective filling date of the claimed invention, it would have been obvious to the
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`artisan of ordinary skill to employ that a second spacer provided on the second substrate, a second
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`laminated structure provided on the first substrate at a position opposed to the second spacer, wherein
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`the second laminated structure has a structure in which a step height layer is further laminated on a
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`laminated structure identical to that of the first laminated structure as taught by Sasaki and employ that
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`a common electrode is provided on the first substrate, a step height layer includes a metal layer of a
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`common line provided above the common electrode and electrically connected to the common
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`electrode as taught by Son et al. for the system of Chang et al. in view of Sasaki such that a common
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`electrode is provided on the first substrate, a metal layer of a common line provided above the common
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`electrode and electrically connected to the common electrode is provided, a second spacer is provided
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`on the second substrate, a second laminated structure is provided on the first substrate at a position
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`opposed to the second spacer, wherein the second laminated structure has a structure in which the
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`metal layer is further laminated on a laminated structure identical to that of the first laminated
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`structure since this would help to support the first and second substrates in such a manner as to
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`separate the first and second substrates from each other in parallel to each other for a touch-type liquid
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`crystal display ap