www.uspto.gov
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`PO. Box 1450
`Alexandria, Virginia 2231371450
`
`16/154,300
`
`10/08/2018
`
`Daisuke KAJITA
`
`20295.0025U301
`
`4022
`
`53148
`
`759°
`
`10’1””
`
`HAMRE, SCHUMANN, MUELLER & LARSON RC.
`45 South Seventh Street
`Suite 2700
`
`MINNEAPOLIS, MN 55402-1683
`
`LIU' SHAN
`
`PAPER NUMBER
`
`ART UNIT
`2871
`
`NOTIFICATION DATE
`
`DELIVERY MODE
`
`10/10/2019
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above—indicated "Notification Date" to the
`
`following e—mail address(es):
`PTOMail@hsml.eom
`
`PTOL-90A (Rev. 04/07)
`
`

`

`0/7709 A0170” Summary
`
`Application No.
`16/154,300
`Examiner
`SHAN LIU
`
`Applicant(s)
`KAJITA, Daisuke
`Art Unit
`AIA (FITF) Status
`2871
`Yes
`
`- The MAILING DA TE of this communication appears on the cover sheet wit/7 the correspondence address -
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE g MONTHS FROM THE MAILING
`DATE OF THIS COMMUNICATION.
`Extensions of time may be available under the provisions of 37 CFR 1.136(a). In no event, however, may a reply be timely filed after SIX (6) MONTHS from the mailing
`date of this communication.
`|f NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any earned patent term
`adjustment. See 37 CFR 1.704(b).
`
`Status
`
`1). Responsive to communication(s) filed on 10/8/2018.
`[:1 A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/were filed on
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`2a)D This action is FINAL.
`
`2b)
`
`This action is non-final.
`
`3)[:] An election was made by the applicant in response to a restriction requirement set forth during the interview on
`; the restriction requirement and election have been incorporated into this action.
`
`4)[:] Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Expat/7e Quay/e, 1935 CD. 11, 453 O.G. 213.
`
`Disposition of Claims*
`5)
`Claim(s)
`
`1—15 is/are pending in the application.
`
`5a) Of the above claim(s)
`
`is/are withdrawn from consideration.
`
`E] Claim(s)
`
`is/are allowed.
`
`Claim(s) fl is/are rejected.
`
`[:1 Claim(s) _ is/are objected to.
`
`) ) ) )
`
`6 7
`
`8
`
`
`
`are subject to restriction and/or election requirement
`[j Claim(s)
`9
`* If any claims have been determined aflowabie. you may be eligible to benefit from the Patent Prosecution Highway program at a
`
`participating intellectual property office for the corresponding application. For more information, please see
`
`http://www.uspto.gov/patents/init events/pph/index.jsp or send an inquiry to PPeredback@uspto.gov.
`
`Application Papers
`10)[:] The specification is objected to by the Examiner.
`
`11). The drawing(s) filed on 10/8/2019 is/are: a). accepted or b)E] objected to by the Examiner.
`
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`12). Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
`Certified copies:
`
`a). All
`
`b)D Some**
`
`C)D None of the:
`
`1.. Certified copies of the priority documents have been received.
`
`2.[:] Certified copies of the priority documents have been received in Application No.
`
`3:] Copies of the certified copies of the priority documents have been received in this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`
`** See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`1)
`
`Notice of References Cited (PTO-892)
`
`Information Disclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`2)
`Paper No(s)/Mail Date_
`U.S. Patent and Trademark Office
`
`3) C] Interview Summary (PTO-413)
`Paper No(s)/Mail Date
`4) CI Other-
`
`PTOL-326 (Rev. 11-13)
`
`Office Action Summary
`
`Part of Paper No./Mai| Date 20191003
`
`

`

`Application/Control Number: 16/154,300
`Art Unit: 2871
`
`Page 2
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`Notice of Pre-AIA or AIA Status
`
`The present application, filed on or after March 16, 2013, is being examined under the first
`
`inventor to file provisions of the AIA.
`
`Claim Rejections - 35 USC § 112
`
`The following is a quotation of 35 U.S.C. 112(b):
`(b) CONCLUSION—The specification shall conclude with one or more claims particularly pointing out
`and distinctly claiming the subject matter which the inventor or a joint inventor regards as the
`invention.
`
`The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph:
`The specification shall conclude with one or more claims particularly pointing out and distinctly
`claiming the subject matter which the applicant regards as his invention.
`
`Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph,
`
`as being indefinite for failing to particularly point out and distinctly claim the subject matter which the
`
`inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
`
`Claim 1, lines 10-11 recites the limitation ”the first video signal line and the second video signal
`
`line". There is insufficient antecedent basis for this limitation in the claim. For examination purposes,
`
`examiner has interpreted this limitation as - - a first video signal line of a pair of the plurality of pairs of
`
`first video signal lines and second video signal lines and a second video signal line of the pair of the
`
`plurality of pairs of first video signal lines and second video signal lines - -.
`
`Claim 15, lines 2-3 recites the limitation ”the light shielding layer". There is insufficient
`
`antecedent basis for this limitation in the claim. For examination purposes, examiner has interpreted
`
`this limitation as - - a light shielding layer - -.
`
`Dependent claims 2-14 are rejected by virtue of their dependency.
`
`In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102
`
`and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory
`
`

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`Application/Control Number: 16/154,300
`Art Unit: 2871
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`Page 3
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`basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and
`
`the rationale supporting the rejection, would be the same under either status.
`
`Claim Rejections - 35 USC § 102
`
`The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis
`
`for the rejections under this section made in this Office action:
`
`A person shall be entitled to a patent unless —
`(a)(2) the claimed invention was described in a patent issued under section 151, or in an application
`for patent published or deemed published under section 122(b), in which the patent or application, as
`the case may be, names another inventor and was effectively filed before the effective filing date of
`the claimed invention.
`
`Claims 1-2, 9 and 15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yamazaki et
`
`al. (US 2018/0203319).
`
`Re claim 1, Yamazaki et al. teaches a liquid crystal display panel (Fig. 1-19, [0075-0190]) having a
`
`plurality of pixels (PIX in Fig. 1-5, [0078]) arranged in a matrix (Fig. 1) comprising:
`
`a plurality of pixel electrodes (21 in Fig. 1-5, [0078]) provided in a corresponding one of the
`
`plurality of pixels (PIX in Fig. 1, [0078]); and
`
`a plurality of pairs of first video signal lines (SLL Fig. 1, [0081], Fig. 2-5) and second video signal
`
`lines (SLR in Fig.1, [0081], Fig. 2-5) provided at a corresponding boundary (Fig. 1-5) between two pixels
`
`adjacent to each other (Fig. 1-5) in a first direction (the horizontal direction in Fig. 1-5), the plurality of
`
`pairs of the first video signal lines (SLL Fig. 1, [0081], Fig. 2-5) and the second video signal lines (SLL Fig.
`
`1, [0081], Fig. 2-5) extending in a second direction (the vertical direction in Fig. 1-5) crossing to the first
`
`direction (the horizontal direction in Fig. 1-5),
`
`wherein at least a part (Fig. 1-5) of the pixel electrode (21 in Fig. 1, [0078], Fig. 3-5) exists
`
`between a first video signal line (the SZ/SLR overlapping 21 in Fig. 1-5, [0095]) of a pair (Fig. 1-5) of the
`
`plurality of pairs of first video signal lines (Fig. 1-5) and second video signal lines (Fig. 1-5) and a second
`
`video signal line (the adjacent Sl/SLL between two neighboring pixels in Fig. 1-5, [0095]) of the pair (Fig.
`
`

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`Application/Control Number: 16/154,300
`Art Unit: 2871
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`Page 4
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`1-5) of the plurality of pairs (Fig. 1-5) of first video signal lines (Fig. 1-5) and second video signal lines
`
`(Fig. 1-5).
`
`Re claims 2I 9I 15, Yamazaki et al. also teaches the following structures:
`
`0
`
`(Claim 2) a plurality of scanning lines (GL/Gl/GZ in Fig. 1-5, [0076]), each of which is disposed at
`
`a boundary between corresponding two pixels adjacent to each other (Fig. 1-5) in the second
`
`direction (the vertical direction in Fig. 1-5) and extends in the first direction (the horizontal
`
`direction in Fig. 1-5); and a plurality of transistors (TFTs 30 in Fig. 1-5, [0101]), formed in a
`
`corresponding one of the plurality of pixels (PIX in Fig. 1-5, [0078]), wherein gate electrodes
`
`([0101], Fig. 1-5) of the plurality of transistors (TFTs 30 in Fig. 1-5, [0101]) are connected to a
`
`corresponding one of the plurality of scanning lines (GL/Gl/GZ in Fig. 1-5, [0076]), first
`
`conductive electrodes (the drain electrode of TFTs in Fig 1-5, [0101-0102]) of the plurality of
`
`transistors (TFTs 30 in Fig. 1-5, [0101]) are connected to a corresponding one of the plurality of
`
`pixel electrodes (21 in Fig. 1-5, [0078]), each two of the plurality of scanning lines (GL/Gl/GZ in
`
`Fig. 1-5, [0076]) are connected to each other (Fig. 1-2, [0076]), a second conductive electrode
`
`(the source electrode of TFTs connected to the SZ/SLR in Fig 1-5, [0101-0102]) of a transistor
`
`(the TFT 30 connected to the SZ/SLR in Fig. 1-5, [0101]) connected to one of the connected two
`
`scanning lines (GL/Gl/GZ in Fig. 1-5, [0076]) is connected to one of the first video signal line (the
`
`SZ/SLR overlapping 21 in Fig. 1-5, [0095]) and the second video signal line (the adjacent Sl/SLL
`
`between two pixels in Fig. 1-5, [0095]), and a second conductive electrode (the source electrode
`
`of TFTs connected to the Sl/SLL in Fig 1-5, [0101-0102]) of a transistor (the TFT 30 connected to
`
`the Sl/SLL in Fig. 1-5, [0101]) connected to the other of the two connected scanning lines (Fig. 3,
`
`5 and 21, [0113, 0266]) is connected to the other of the first video signal line (the SZ/SLR
`
`

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`Application/Control Number: 16/154,300
`Art Unit: 2871
`
`Page 5
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`overlapping 21 in Fig. 1-5, [0095]) and the second video signal line (the adjacent Sl/SLL between
`
`two pixels in Fig. 1-5, [0095]).
`
`0
`
`(Claim 9) a common electrode (23 in Fig. 6-12 and 14-17, [0119-0121, 0133-0135]) formed over
`
`the plurality of pixels (PIX in Fig. 1-5, [0078]), wherein the common electrode (23 in Fig. 6-12 and
`
`14-17, [0119-0121, 0133-0135]) covers (Fig. 6-12 and 14-17, [0119-0121, 0133-0135]) at least
`
`one of the first video signal line (the SZ/SLR overlapping 21 in Fig. 1-5, [0095]) and the second
`
`video signal line (the adjacent Sl/SLL between two pixels in Fig. 1-5, [0095]).
`
`0
`
`(Claim 15) the first video signal line (the SZ/SLR overlapping 21 in Fig. 1-5, [0095]) and the
`
`second video signal line (the adjacent Sl/SLL between two pixels in Fig. 1-5, [0095]) are covered
`
`(Fig. 4B and Fig. 6, [0112, 0114, 0121]) with a light shielding layer (Fig. 4B and Fig. 6, [0112,
`
`0114, 0121]) formed along (Fig. 4B and Fig. 6, [0112, 0114, 0121]) the second direction (the
`
`vertical direction in Fig. 1-5).
`
`Claim Rejections - 35 USC § 103
`
`The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections
`
`set forth in this Office action:
`
`A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is
`not identically disclosed as set forth in section 102 of this title, if the differences between the claimed
`invention and the prior art are such that the claimed invention as a whole would have been obvious
`before the effective filing date of the claimed invention to a person having ordinary skill in the art to
`which the claimed invention pertains. Patentability shall not be negated by the manner in which the
`invention was made.
`
`Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. as applied
`
`to claim 1 above, and in view of Ono et al. (US 2007/0252936).
`
`Re claim 3, Yamazaki et al. does not teach that at least two of the plurality of pixel electrodes
`
`and at least two of the plurality of transistors are formed in each of the plurality of pixels.
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`

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`Application/Control Number: 16/154,300
`Art Unit: 2871
`
`Page 6
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`Ono et al. teaches that (Fig. 1 and 7) at least two of the plurality of pixel electrodes (PX1 and PX2
`
`in Fig. 1 and 7, [0068, 0087, 0093-0095, 0125]) and at least two of the plurality of transistors (TFT1 and
`
`TF2 in Fig. 1 and 7, [0064]) are formed in each of the plurality of pixels (Fig. 1 and 7).
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that at least two of the plurality of pixel electrodes and at least two of
`
`the plurality of transistors are formed in each of the plurality of pixels as taught by Ono et al. for the
`
`system of Yamazaki et al. since this would help to obtain the image quality which is suitable for the
`
`application to the liquid crystal television receiver set which requires the wide viewing angle (Ono et al.,
`
`[0128, 0010]).
`
`Claims 4-6 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al.
`
`as applied to claim 1 above, and in view of Matsushima (US 2017/0242310).
`
`Re claim 4, Yamazaki et al. teaches that the first video signal line (the SZ/SLR overlapping 21 in
`
`Fig. 1-5, [0095]) is overlapping a pixel electrode (Fig. 1-5) and located at a middle portion of the pixel
`
`(Fig. 1-5) and the second video signal line (the adjacent Sl/SLL between two pixels in Fig. 1-5, [0095]) is
`
`located at the boundary between two adjacent pixels (Fig. 1-5). Yamazaki et al. does not teach that each
`
`pixel electrode includes a plurality of line electrodes, and at least one of the plurality of line electrodes
`
`exists between the first video signal line and the second video signal line.
`
`Matsushima teaches that (Fig. 4, 8, 11 and 12) each pixel electrode (E1 in Fig. 4, 8, 11 and 12,
`
`[0037, 0097]) includes a plurality of line electrodes (40 in Fig. 4, 8, 11 and 12, [0048, 0098]), and at least
`
`one of the plurality of line electrodes (40 in Fig. 4, 8, 11 and 12, [0048, 0098]) exists between a middle
`
`portion of the pixel (Fig. 4, 8, 11 and 12) and a second video signal line (S/Sl/SZ in Fig. 4, 8, 11 and 12,
`
`[0070]) at the boundary between two adjacent pixels (Fig. 4, 8, 11 and 12).
`
`

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`Application/Control Number: 16/154,300
`Art Unit: 2871
`
`Page 7
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`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that each pixel electrode includes a plurality of line electrodes, and at
`
`least one of the plurality of line electrodes exists between a middle portion of the pixel and a second
`
`video signal line at the boundary between two adjacent pixels as taught by Matsushima for the system
`
`of Yamazaki et al. such that each pixel electrode includes a plurality of line electrodes, and at least one
`
`of the plurality of line electrodes exists between the first video signal line and the second video signal
`
`line of the system of Yamazaki et al. since this would help to provide a high-speed response mode type
`
`of liquid crystal display device which can improve a display quality (Matsushima, [0027]).
`
`Re claim 5, Yamazaki et al. does not teach that the plurality of line electrodes extend in the
`
`second direction.
`
`Matsushima teaches that (Fig. 12) the plurality of line electrodes (40 in Fig. 12, [0098]) extend in
`
`the second direction (the vertical direction in Fig. 12).
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that the plurality of line electrodes extend in the second direction as
`
`taught by Matsushima for the system of Yamazaki et al. in view of Matsushima since this would help to
`
`provide a high-speed response mode type of liquid crystal display device which can improve a display
`
`quality (Matsushima, [0027]).
`
`Re claim 6, Yamazaki et al. does not teach that each pixel electrode further includes a
`
`connection electrode connecting the plurality of line electrodes.
`
`Matsushima teaches that (Fig. 4, 8, 11 and 12) each pixel electrode (E1 in Fig. 4, 8, 11 and 12,
`
`[0037, 0097]) further includes a connection electrode (30 in Fig. 4, 8, 11 and 12, [0048]) connecting the
`
`plurality of line electrodes (40 in Fig. 4, 8, 11 and 12, [0048, 0098]).
`
`

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`Application/Control Number: 16/154,300
`Art Unit: 2871
`
`Page 8
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`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that each pixel electrode further includes a connection electrode
`
`connecting the plurality of line electrodes as taught by Matsushima for the system of Yamazaki et al. in
`
`view of Matsushima since this would help to provide a high-speed response mode type of liquid crystal
`
`display device which can improve a display quality (Matsushima, [0027]).
`
`Re claim 13, Yamazaki et al. teaches that an edge portion of the pixel electrode (the edge
`
`portion of the 21 between $2 and the left 51 in Fig. 3-4) between the first video signal line (the SZ/SLR
`
`overlapping 21 in Fig. 1-5, [0095]) and the second video signal line (the adjacent Sl/SLL between two
`
`pixels in Fig. 1-5, [0095]) is not covered (Fig. 3-4) with a light shielding layer (Fig. 4B and Fig. 6, [0112,
`
`0114, 0121]). Yamazaki et al. does not teach that the edge portion of the pixel electrode is the line
`
`electrode.
`
`Matsushima teaches that (Fig. 12) the edge portion of the pixel electrode (Fig. 12) is the line
`
`electrode (40 in Fig. 12, [0098]).
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that the edge portion of the pixel electrode is the line electrode as
`
`taught by Matsushima for the system of Yamazaki et al. in view Matsushima such that the line electrode
`
`existing between the first video signal line and the second video signal line is not covered with a light
`
`shielding layer since this would help to provide a high-speed response mode type of liquid crystal display
`
`device which can improve a display quality (Matsushima, [0027]).
`
`Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. in view
`
`of Matsushima as applied to claim 4 above, and further in view of Kita (US 2017/0045787).
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`

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`Application/Control Number: 16/154,300
`Art Unit: 2871
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`Page 9
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`Re claim 7, Yamazaki et al. does not teach that an interval between two adjacent pixel
`
`electrodes is equal to an interval between two adjacent line electrodes in one pixel electrode.
`
`Matsushima teaches that (Fig. 7, 9, 10, [0068, 0077]) an interval (Dmin in Fig. 7, 9, 10, [0068,
`
`0077]) between two adjacent pixel electrodes (Fig. 7, 9, 10, [0068, 0077]) is 5 pm ([0068, 0077], Dmin=5
`
`um)
`
`Kita teaches that (Fig 1, [0088, 0053], 5:5 um) an interval (S in Fig 1, [0088, 0053], 5:5 um)
`
`between two adjacent line electrodes (Fig. 1) in one pixel electrode (Fig. 1) is 5 pm (Fig 1, [0088, 0053],
`
`5:5 um).
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that an interval between two adjacent pixel electrodes is 5 pm as
`
`taught by Matsushima and employ that an interval between two adjacent line electrodes in one pixel
`
`electrode is 5 pm for the system of Yamazaki et al. in view of Matsushima such that an interval between
`
`two adjacent pixel electrodes is equal to an interval between two adjacent line electrodes in one pixel
`
`electrode since this would help to provide a high-speed response mode type of liquid crystal display
`
`device which can improve a display quality (Matsushima, [0027]), and it helps that occurrence of flickers
`
`can be suppressed when low frequency driving is performed in a liquid crystal display device of a
`
`transverse electric field mode (Kita, [0033, 0089]).
`
`Re claim 8, Yamazaki et al. teaches that a first pixel electrode (the second 21 in the first row of
`
`21 in Fig. 1, [0078], Fig. 2-4) and a second pixel electrode (the first 21 in the first row of 21 in Fig. 1,
`
`[0078], Fig. 2-4) among the plurality of pixel electrodes (21 in Fig. 1-5, [0078]) are adjacent to each other
`
`(Fig. 1-4) in the first direction (the horizontal direction in Fig. 1-5), the first video signal line (the SZ/SLR
`
`overlapping 21 in Fig. 1-5, [0095]) overlaps a middle portion (Fig. 1-5) of the second pixel electrode (the
`
`first 21 in the first row of 21 in Fig. 1, [0078], Fig. 2-4) in planar view (Fig. 1-5), and the second video
`
`

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`Application/Control Number: 16/154,300
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`signal line (the adjacent Sl/SLL between two neighboring pixels in Fig. 1-5, [0095]) is located between
`
`the first pixel electrode (the second 21 in the first row of 21 in Fig. 1, [0078], Fig. 2-4) and the second
`
`pixel electrode (the first 21 in the first row of 21 in Fig. 1, [0078], Fig. 2-4) in planar view (Fig. 1-5).
`
`Yamazaki et al. does not teach that a middle portion of the second pixel electrode in planar view is the
`
`line electrode of the second pixel electrode.
`
`Matsushima teaches that (Fig. 4, 8, 11 and 12) teaches that a middle portion (Fig. 8, 11-12) of
`
`the second pixel electrode (40 in Fig. 4, 8, 11 and 12, [0048, 0098]) in planar view is the line electrode
`
`(Fig. 4, 8, 11 and 12) of the second pixel electrode.
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that a middle portion of the second pixel electrode in planar view is
`
`the line electrode of the second pixel electrode as taught by Matsushima for the system of Yamazaki et
`
`al. in view of Matsushima and Kita such that the first video signal line overlaps the line electrode of the
`
`second pixel electrode in planar view since this would help to provide a high-speed response mode type
`
`of liquid crystal display device which can improve a display quality (Matsushima, [0027]).
`
`Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. as
`
`applied to claim 1 above, and in view of Kim et al. (US 2012/0218199).
`
`Re claim 10, Yamazaki et al. does not explicitly teach that a common line electrically connected
`
`to the common electrode.
`
`Kim et al. teaches that (Fig. 3 and Fig. 10A-1OB, [0047, 0071-0078]) a common line (TY11/TY12 in
`
`Fig. 10A-1OB, [0078, 0075-0077]) electrically connected to the common electrode (common electrode
`
`COM including C11~C33, [0047, 0078, 0071], Fig. 3 and Fig. 10A-1OB).
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that a common line electrically connected to the common electrode
`
`

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`Application/Control Number: 16/154,300
`Art Unit: 2871
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`Page 11
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`as taught by Kim et al. for the system of Yamazaki et al. since this would help to provide a touch sensor
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`integrated display device, thus resulting in a reduced thickness of the display device and improved
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`durability, and a touch sensor integrated display device wherein signal lines for recognizing a touch and
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`data lines overlap each other to thus improve an aperture ratio of the display device (Kim et al., [0014]).
`
`Re claim 11, Yamazaki et al. does not explicitly teach that the common line extends in the
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`second direction, and overlaps the first video signal line or the second video signal line in planar view.
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`Kim et al. teaches that (Fig. 3 and Fig. 10A-103, [0047, 0071-0078]) the common line (TY11/TY12
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`in Fig. 10A-103, [0078, 0075-0077]) extends in the second direction (the vertical direction in Fig. 10A and
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`3), and overlaps the first video signal line (D1 in Fig. 10A, [0074]) or the second video signal line (D2 in
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`Fig. 10A, [0074]) in planar view (Fig. 10A).
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that the common line extends in the second direction, and overlaps
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`the first video signal line or the second video signal line in planar view as taught by Kim et al. for the
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`system of Yamazaki et al. in view of Kim et al. since this would help to provide a touch sensor integrated
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`display device, thus resulting in a reduced thickness of the display device and improved durability, and a
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`touch sensor integrated display device wherein signal lines for recognizing a touch and data lines
`
`overlap each other to thus improve an aperture ratio of the display device (Kim et al., [0014]).
`
`Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. as applied
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`to claim 1 above, and in view of Ryuzaki et al. (US 2009/0273751).
`
`Re claim 12, Yamazaki et al. teaches that a first insulator (the gate insulation layer 34 in Fig. 6-12
`
`and 14-17, [0124]) covering ([0118], Fig. 3, 6-12 and 14-17) the first video signal line (the SZ/SLR
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`overlapping 21 in Fig. 1-5, [0095]) and the second video signal line (the adjacent Sl/SLL between two
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`Application/Control Number: 16/154,300
`Art Unit: 2871
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`Page 12
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`neighboring pixels in Fig. 1-5, [0095]); and a second insulator (81 in Fig. 6-12 and 14-17, [0128]) covering
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`(Fig. 6-12 and 14-17) the first insulator (the gate insulation layer 34 in Fig. 6-12 and 14-17, [0124]).
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`Yamazaki et al. does not explicitly teach that the second insulator containing carbon, wherein a
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`thickness of the second insulator is larger than a thickness of the first insulator.
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`Ryuzaki et al. teaches that the second insulator (30 in Fig. 15b, [0107-0108]) containing carbon
`
`([0106, 0088, 0098]), wherein a thickness of the second insulator (the thickness of 30 in Fig. 15b is
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`2.3um, [0102]) is larger (Fig. 15b, [0102, 0107]) than a thickness of the first insulator (the thickness of
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`gate dielectric film 24 in Fig. 15b is 100nm, [0102]).
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`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that the second insulator containing carbon, wherein a thickness of
`
`the second insulator is larger than a thickness of the first insulator as taught by Ryuzaki et al. for the
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`system of Yamazaki et al. since this would help to provide a liquid crystal display device with high image
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`visibility at low power consumption and produced at low cost by using an interlayer dielectric film,
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`which has low dielectric constant, high heat-resistant property, high optical transmissivity, high film
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`thickness and high flattening property produced at low cost (Ryuzaki et al., Abs, [0039, 0061, 0111]).
`
`Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. as applied
`
`to claim 1 above, and in view of Matsui et al. (US 2011/0234949).
`
`Re claim 14, Yamazaki et al. teaches that the first video signal line (the SZ/SLR overlapping 21 in
`
`Fig. 1-5, [0095]) extending along the second direction (the vertical direction in Fig. 1-5) overlaps middle
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`portions (Fig. 1-5) of the pixels in planar view (Fig. 1-5), and the second video signal line (the adjacent
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`Sl/SLL between two neighboring pixels in Fig. 1-5, [0095]) extending along the second direction (the
`
`vertical direction in Fig. 1-5) is located between two adjacent pixels in planar view (Fig. 1-5). Yamazaki et
`
`al. does not explicitly teach that one of the first video signal line and the second video signal line is
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`Application/Control Number: 16/154,300
`Art Unit: 2871
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`Page 13
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`covered with a light shielding layer formed along the second direction, and the other of the first video
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`signal line and the second video signal line is not covered with the light shielding layer formed along the
`
`second direction.
`
`Matsui et al. teaches that (Fig. 1A, Fig. 5-6, Fig.8 and Fig. 15, [0067], the interconnects DTL
`
`(interconnects 24) are signal lines from the signal output circuit 14 and output the video signals to the
`
`image display panel 11) one of middle portions of the pixels (Fig. 1A, Fig. 5-6, Fig. 8 ) and a second video
`
`signal line (the 24 corresponding to the boundary between the first 6 and W and coved by 40 in Fig. 1A,
`
`Fig. 15, [0067]) is covered (Fig. 1A and Fig.5 and 8) with a light shielding layer (40 in Fig. 1A and Fig.5
`
`and 8, [0081]) formed along the second direction (the vertical direction in Fig.5 and 8), and the other of
`
`the middle portions of the pixels (Fig. 1A, Fig. 5-6, Fig. 8 ) and the second video signal line (the 24
`
`corresponding to the boundary between the first 6 and W and coved by 40 in Fig. 1A, Fig. 15, [0067]) is
`
`not covered (Fig. 1A and Fig.5 and 8) with the light shielding layer (40 in Fig. 1A and Fig.5 and 8, [0081])
`
`formed along the second direction (the vertical direction in Fig.5 and 8).
`
`Before the effective filling date of the claimed invention, it would have been obvious to the
`
`artisan of ordinary skill to employ that one of middle portions of the pixels and a second video signal line
`
`is covered with a light shielding layer formed along the second direction, and the other of the middle
`
`portions of the pixels and the second video signal line is not covered with the light shielding layer
`
`formed along the second direction as taught by Matsui et al. for the system of Yamazaki et al. such that
`
`one of the first video signal line and the second video signal line is covered with a light shielding layer
`
`formed along the second direction, and the other of the first video signal line and the second video
`
`signal line is not covered with the light shielding layer formed along the second direction since this
`
`would help to provide an image display apparatus capable of widening a dynamic range of luminance or
`
`reducing electric power consumption without impairing image quality (Matsui et al., [0020]).
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`Application/Control Number: 16/154,300
`Art Unit: 2871
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`Page 14
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`Conclusion
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`Any inquiry concerning this communication or earlier communications from the examiner
`
`should be directed to SHAN LIU whose telephone number is (571)270-0383. The examiner can normally
`
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`If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ed
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`Glick can be reached on 571-272-2490. The fax phone number for the organization where this
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`application or proceeding is assigned is 571-273-8300.
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`
`/Shan Liu/
`
`Primary Examiner, Art Unit 2871
`
`