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`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and TrademarkOffice
`Address; COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`
`16/172,322
`
`10/26/2018
`
`Teruhisa Nakagawa
`
`20326.0147US01
`
`7080
`
`HAY
`
`M
`
`TLERS
`
`HAMRE, SCHUMANN, MUELLER & LARSON P.C.
`45 South Seventh Street
`Suite 2700
`MINNEAPOLIS, MN 55402-1683
`
`ALMEIDA, CORY A
`
`2622
`
`PAPER NUMBER
`
`NOTIFICATION DATE
`
`DELIVERY MODE
`
`01/07/2020
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
`following e-mail address(es):
`PTOMail @hsml.com
`
`PTOL-90A (Rev. 04/07)
`
`

`

`
`
`Disposition of Claims*
`1-20 is/are pending in the application.
`)
`Claim(s)
`5a) Of the above claim(s) ___ is/are withdrawn from consideration.
`CC) Claim(s)
`is/are allowed.
`Claim(s) 1-20 is/are rejected.
`S)
`) O Claim(s)___is/are objected to.
`C) Claim(s
`are subjectto restriction and/or election requirement
`)
`S)
`* If any claims have been determined allowable, you maybeeligible to benefit from the Patent Prosecution Highway program at a
`participating intellectual property office for the corresponding application. For more information, please see
`http://www.uspto.gov/patents/init_events/pph/index.jsp or send an inquiry to PPHfeedback@uspto.gov.
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`) )
`
`Application Papers
`10)L The specification is objected to by the Examiner.
`11) The drawing(s) filed on 10/26/18 is/are: a)#) accepted or b)( objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`12)(1) Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d)or (f).
`Certified copies:
`cc) None ofthe:
`b)LJ Some**
`a)L) All
`1.2 Certified copies of the priority documents have been received.
`2.2 Certified copies of the priority documents have been received in Application No.
`3.4) Copies of the certified copies of the priority documents have been receivedin this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`* See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`1)
`
`Notice of References Cited (PTO-892)
`
`Information Disclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`2)
`Paper No(s)/Mail Date
`U.S. Patent and Trademark Office
`
`3) (J Interview Summary (PTO-413)
`Paper No(s)/Mail Date
`(Qj Other:
`
`4)
`
`PTOL-326 (Rev. 11-13)
`
`Office Action Summary
`
`Part of Paper No./Mail Date 20191230
`
`Application No.
`Applicant(s)
`16/172,322
`Nakagawa, Teruhisa
`
`Office Action Summary Art Unit|AIA (FITF) StatusExaminer
`CORY A ALMEIDA
`2622
`Yes
`
`
`
`-- The MAILING DATEofthis communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLYIS SET TO EXPIRE 3 MONTHS FROM THE MAILING
`DATE OF THIS COMMUNICATION.
`Extensions of time may be available underthe provisions of 37 CFR 1.136(a). In no event, however, may a reply betimely filed after SIX (6) MONTHSfrom the mailing
`date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHSfrom the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133}.
`Any reply received by the Office later than three months after the mailing date of this communication, evenif timely filed, may reduce any earned patent term
`adjustment. See 37 CFR 1.704(b).
`
`Status
`
`1) Responsive to communication(s) filed on 10/26/18.
`LC} A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/werefiled on
`
`2a)(J This action is FINAL. 2b))This action is non-final.
`3) An election was madeby the applicant in responseto a restriction requirement set forth during the interview
`on
`; the restriction requirement and election have been incorporated into this action.
`4\(Z Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Exparte Quayle, 1935 C.D. 11, 453 O.G. 213.
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 2
`
`DETAILED ACTION
`
`Notice of Pre-AlA or AIA Status
`
`1.
`
`The present application, filed on or after March 16, 2013, is being examined
`
`under the first inventor to file provisions of the AIA.
`
`Claim Rejections - 35 USC § 103
`
`2.
`
`In the event the determination of the status of the application as subject to AIA 35
`
`U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103)is incorrect, any
`
`correction of the statutory basis for the rejection will not be considered a new ground of
`
`rejection if the prior art relied upon, and the rationale supporting the rejection, would be
`
`the same under either status.
`
`3.
`
`The following is a quotation of 35 U.S.C. 103 which forms the basis for all
`
`obviousnessrejections set forth in this Office action:
`
`A patent for a claimed invention may not be obtained, notwithstanding that the claimed
`invention is not identically disclosed as set forth in section 102, if the differences between the
`claimed invention and the prior art are such that the claimed invention as a whole would have
`been obvious before the effective filing date of the claimed invention to a person having
`ordinary skill in the art to which the claimed invention pertains. Patentability shall not be
`negated by the manner in which the invention was made.
`
`4.
`
`Claims 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu,
`
`US-201 70206843in view of Yoon, US-20160189591.
`
`5.
`
`In regards to claim 1, and the associated method of manufacturing claims 17-20,
`
`Liu discloses a liquid crystal display device (Par. 0009-0010 display device utilizing
`
`LCD) comprising: a first display panel (Fig. 3, 08 OLED display panel) comprising a
`
`plurality of first gate lines and a plurality of first data lines in a first display region thereof
`
`(Fig. 3, 03 OLED panel; Fig. 5, data line DL and gate line SL), and a second display
`
`panel (Fig. 3, 01 LCD panel) comprising a plurality of second gate lines and a plurality
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 3
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`of second data lines in a second display region thereof (Fig. 3, 01 LCD panel; Fig. 5,
`
`data line DL and gate line SL; Par. 0076first pixel units of OLED and second pixel units
`
`of LCD are arranged in 1:1 correspondence); andafirst driving circuit for one or more of
`
`the plurality of first gate lines and the plurality of first data lines, wherein the first driving
`
`circuit comprises one or morefirst drivers to provide signals to the one or more of the
`
`plurality of first gate lines and the plurality offirst data lines (Fig. 3, 03 OLED panel; Fig.
`
`5, data line DL and gate line SL; drivers for DL data lines and SL gate lines), wherein
`
`the first display panel and the second display panel overlap each other in plan view (Fig.
`
`3, 03 OLED display panel and 01 LCD display panel ; Par. 0076first pixel units of OLED
`
`and second pixel units of LCD are arranged in 1:1 correspondence), wherein the
`
`plurality of first gate lines and the plurality of first data lines correspond to the plurality of
`
`second gate lines and the plurality of second data lines, respectively, in the first display
`
`region and the second display region ofthe first display panel and the second display
`
`panel (Fig. 3, 03 OLED panel; Fig. 3, 01 LCD panel Fig. 5, data line DL and gate line
`
`SL; Par. 0076first pixel units of OLED and secondpixel units of LCD are arranged in
`
`1:1 correspondence).
`
`Liu does not disclose expressly at least one of two or more adjacent first gate
`
`lines from the plurality of first gate lines and two or more adjacent first data lines from
`
`the plurality of first data lines are provided with same signals at a same instant of time.
`
`Yoon discloses at least one of two or more adjacent first gate lines from the
`
`plurality of first gate lines and two or more adjacent first data lines from the plurality of
`
`first data lines are provided with same signals at a same instant of time (Fig. 7, GL
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 4
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`providing a same gateline signal to Q simultaneously and DL providing a same data
`
`signal to Q simultaneously for 4 pixels 191_1-191_4).
`
`At the time ofthe filing of the invention, it would have been obvious to one of
`
`ordinary skill in the art the OLED display of Liu could be structured and driven in the
`
`manner of Yoon. The motivation for doing so would have been to increase
`
`transmittance, increase refreshing speed, and reduce wiring complexity (Par. 0180-
`
`0182).
`
`Therefore, it would have been obvious to combine Yoon with Liu to obtain the
`
`invention of claims 1 and 17-20.
`
`6.
`
`In regards to claim 10, Liu disclosesa liquid crystal display device (Par. 0009-
`
`0010 display device utilizing LCD) comprising: a first display panel (Fig. 3, 03 OLED
`
`display panel) comprising a plurality of first gate lines and a plurality of first data lines in
`
`a first display region thereof (Fig. 3, 03 OLED display panel; Fig. 5, data line DL and
`
`gate line SL), wherein two adjacentfirst gate lines from the plurality of first gate lines
`
`and two adjacent first data lines from the plurality of first data lines define a first pixel in
`
`the first display region (Fig. 3, 03 OLED panel; Fig. 5, a pixel is defined as being
`
`between two adjacentdata lines DL and two adjacent gate lines SL); a second display
`
`panel (Fig. 3, 01 LCD panel) comprising a plurality of second gate lines and a plurality
`
`of second data lines in a second display region thereof (Fig. 3, 01 LCD panel; Fig. 5,
`
`data line DL and gate line SL; Par. 0076first pixel units of OLED and second pixel units
`
`of LCD are arrangedin 1:1 correspondence), wherein two adjacent second gatelines
`
`from the plurality of second gate lines and two adjacent second data lines from the
`
`plurality of second data lines define a second pixel in the second display region (Fig. 3,
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 5
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`01 LCD panel; Fig. 5, a pixel is defined as being between two adjacent data lines DL
`
`and two adjacentgate lines SL), wherein the first display panel and the second display
`
`panel overlap each otherin plan view (Fig. 3, 03 OLED display panel and 01 LCD
`
`display panel; Par. 0076first pixel units of OLED and second pixel units of LCD are
`
`arranged in 1:1 correspondence), wherein the first display panel and the second display
`
`panel have equal densities offirst pixels and second pixels, respectively, therein (Fig. 3,
`
`03 OLED display panel and 01 LCD display panel; Par. 0076first pixel units of OLED
`
`and second pixel units of LCD are arranged in 1:1 correspondence).
`
`Liu does not disclose expressly the first display panel displays at a lower
`
`definition as compared to the second display panel.
`
`Yoon discloses at least one of two or more adjacent first gate lines from the
`
`plurality of first gate lines and two or more adjacent first data lines from the plurality of
`
`first data lines are provided with same signals at a same instant of time, thereby at a
`
`lower definition (Fig. 7, GL providing a same gate line signal to Q simultaneously and
`
`DL providing a same data signal to Q simultaneously for 4 pixels 191_1-191_4).
`
`At the time of the filing of the invention, it would have been obvious to one of
`
`ordinaryskill in the art the OLED display of Liu could be structured and driven in the
`
`manner of Yoon. The motivation for doing so would have been to increase
`
`transmittance, increase refreshing speed, and reduce wiring complexity (Par. 0180-
`
`0182).
`
`Therefore, it would have been obvious to combine Yoon with Liu to obtain the
`
`invention of claim 10.
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 6
`
`In regards to claim 2 and 11, Liu and Yoon, as combined above, disclose the first
`
`driving circuit comprisesa first gate driving circuit for the plurality of first gate lines and
`
`the one or morefirst drivers comprise one or morefirst gate drivers to provide gate
`
`signals to the plurality offirst gate lines (Liu Fig. 3, 03 OLED panel; Liu Fig. 5, data line
`
`DL and gate line SL; Liu drivers for DL data lines and SL gate lines), wherein two or
`
`more adjacent first gate lines from the plurality of first gate lines are provided with the
`
`same gate signals at the same instant of time (Yoon Fig. 7, GL providing a same gate
`
`line signal to Q simultaneously and DL providing a same data signal to Q
`
`simultaneously for 4 pixels 191_1-191_ 4).
`
`In regards to claims 3 and 12, Liu and Yoon, as combined above, disclose the
`
`two or more adjacent first gate lines from the plurality of first gate lines are electrically
`
`connected to each other by a gate lead connector, and wherein the gate lead connector
`
`is formed outsidethefirst display region (Liu Fig. 3, 03 OLED panel; Liu Fig. 5, data line
`
`DL and gate line SL; Liu drivers for DL data lines and SL gate lines; Liu all the gate lines
`
`are connected to gate driver), and connects between the two or more adjacent first gate
`
`lines and one gate terminal of the one or morefirst gate drivers to receive the gate
`
`signals for the two or more adjacentfirst gate lines (Yoon Fig. 7, GL providing a same
`
`gate line signal to Q simultaneously and DL providing a same data signal to Q
`
`simultaneously for 4 pixels 191_1-191_ 4).
`
`In regards to claims 4 and 13, Liu and Yoon, as combined above, disclose the
`
`plurality offirst gate lines includeafirst gate line group of the two or more adjacent first
`
`gate lines and a second gate line group of the two or more adjacent first gate lines, the
`
`first gate line group and the second gateline group being arranged adjacent to each
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 7
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`other, and whereinafirst gate terminal of the one or morefirst gate drivers electrically
`
`connectsto the first gate line group, a second gate terminal of the one or morefirst gate
`
`drivers electrically connects to the second gate line group, and a third gate terminal of
`
`the one or morefirst gate drivers located between the first gate terminal and the second
`
`gate terminal is voided (Liu Fig. 3, 03 OLED panel; Liu Fig. 5, data line DL and gateline
`
`SL; Liu drivers for DL data lines and SL gatelines; Liu all the gate lines are connected
`
`to gate driver; Yoon Fig. 7, GL providing a same gate line signal to Q simultaneously
`
`and DL providing a same data signal to Q simultaneously for 4 pixels 191_1-191_4;
`
`gate line groups of pixels).
`
`In regards to claims 5 and 14, Liu and Yoon, as combined above, disclose the
`
`first driving circuit comprises a first data driving circuit for the plurality of first data lines
`
`and the one or morefirst drivers comprise one or morefirst data drivers to provide data
`
`signals to the plurality of first data lines (Liu Fig. 3, 03 OLED panel; Liu Fig. 5, data line
`
`DL and gate line SL; Liu drivers for DL data lines and SL gate lines), wherein two or
`
`more adjacent first data lines from the plurality of first data lines are provided with the
`
`same data signals at the same instant of time (Yoon Fig. 7, GL providing a same gate
`
`line signal to Q simultaneously and DL providing a same data signal to Q
`
`simultaneously for 4 pixels 191_1-191_ 4).
`
`In regards to claims 6 and 15, Liu and Yoon, as combined above, disclose the
`
`two or more adjacent first data lines from the plurality of first data lines are electrically
`
`connected to each other by a data lead connector, and wherein the data lead connector
`
`is formed outside thefirst display region (Liu Fig. 3, 03 OLED panel; Liu Fig. 5, data line
`
`DL and gate line SL; Liu drivers for DL data lines and SL gate lines; Liu all the data lines
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 8
`
`are connected to data driver), and connects between the two or more adjacent first data
`
`lines and one data terminal of the one or morefirst data drivers to receive the data
`
`signals for the two or more adjacentfirst data lines (Yoon Fig. 7, GL providing a same
`
`gate line signal to Q simultaneously and DL providing a same data signal to Q
`
`simultaneously for 4 pixels 191_1-191_ 4).
`
`In regards to claims 7 and 16, Liu and Yoon, as combined above, disclose the
`
`plurality of first data lines includeafirst data line group of the two or more adjacent first
`
`data lines and a second dataline group of the two or more adjacentfirst data lines, the
`
`first data line group and the second data line group being arranged adjacent to each
`
`other, and whereinafirst data terminal of the one or morefirst data drivers electrically
`
`connectsto the first data line group, a second data terminal of the one or morefirst data
`
`drivers electrically connects to the second data line group, and a third data terminal of
`
`the one or morefirst data drivers located between the first data terminal and the second
`
`data terminal is voided (Liu Fig. 3, 03 OLED panel; Liu Fig. 5, data line DL and gate line
`
`SL; Liu drivers for DL data lines and SL gatelines; Liu all the data lines are connected
`
`to data driver; Yoon Fig. 7, GL providing a same gate line signal to Q simultaneously
`
`and DL providing a same data signal to Q simultaneously for 4 pixels 191_1-191_4;
`
`data line groupsof pixels).
`
`In regards to claim 8, Liu and Yoon, as combined above, disclose the a second
`
`driving circuit for one or more of the plurality of second gate lines and the plurality of
`
`second data lines, wherein the second driving circuit comprises one or more second
`
`drivers to provide signals to the one or more of the plurality of second gate lines and the
`
`plurality of second data lines, and wherein a number offirst drivers are less than a
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 9
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`number of second drivers (Liu Fig. 3, 01 LCD panel; Liu Fig. 5, data line DL and gate
`
`line SL; Liu drivers for DL data lines and SL gate lines; As combined above with Yoon
`
`number of gate and driving lines for OLED would be less than LCD lines which are
`
`driven independently).
`
`In regards to claim 9, Liu and Yoon, as combined above, disclose the a second
`
`driving circuit for one or more of the plurality of second gate lines and the plurality of
`
`second datalines, wherein the second driving circuit comprises one or more second
`
`drivers to provide signals to the one or more of the plurality of second gate lines and the
`
`plurality of second data lines, and wherein a number of terminals in the one or morefirst
`
`drivers are less than a number of terminals in the one or more second drivers (Liu Fig.
`
`3, 01 LCD panel; Liu Fig. 5, data line DL and gate line SL; Liu drivers for DL data lines
`
`and SL gate lines; As combined above with Yoon number of gate and driving lines for
`
`OLED would beless than LCD lines which are driven independently).
`
`Conclusion
`
`7.
`
`Any inquiry concerning this communication or earlier communications from the
`
`examiner should be directed to CORY A ALMEIDA whosetelephone number is
`
`(571)270-3143. The examiner can normally be reached on M-Th 9AM-730PM.
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 10
`
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`/CORY A ALMEIDA/
`Examiner, Art Unit 2622
`12/30/19
`
`/VIJAY SHANKAR/
`Primary Examiner, Art Unit 2622
`
`