www.uspto.gov
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and TrademarkOffice
`Address; COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`
`16/172,322
`
`10/26/2018
`
`Teruhisa Nakagawa
`
`20326.0147US01
`
`7080
`
`HAY
`
`M
`
`TLERS
`
`HAMRE, SCHUMANN, MUELLER & LARSON P.C.
`45 South Seventh Street
`Suite 2700
`MINNEAPOLIS, MN 55402-1683
`
`ALMEIDA, CORY A
`
`2622
`
`PAPER NUMBER
`
`NOTIFICATION DATE
`
`DELIVERY MODE
`
`06/10/2020
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
`following e-mail address(es):
`PTOMail @hsml.com
`
`PTOL-90A (Rev. 04/07)
`
`

`

`
`
`Disposition of Claims*
`1-11,13-14 and 16-22 is/are pending in the application.
`)
`Claim(s)
`5a) Of the above claim(s) ___ is/are withdrawn from consideration.
`CJ] Claim(s)__ is/are allowed.
`Claim(s) 1-11,13-14 and 16-22 is/are rejected.
`OO Claim(s)__is/are objectedto.
`CC) Claim(s)
`are subjectto restriction and/or election requirement
`* If any claims have been determined allowable, you maybeeligible to benefit from the Patent Prosecution Highway program at a
`participating intellectual property office for the corresponding application. For more information, please see
`http://www.uspto.gov/patents/init_events/pph/index.jsp or send an inquiry to PPHfeedback@uspto.gov.
`
`) ) ) )
`
`Application Papers
`10) The specification is objected to by the Examiner.
`11)0) The drawing(s) filedon__ is/are: a)) accepted or b)() objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`12)0) Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d)or (f).
`Certified copies:
`c)X None ofthe:
`b)L) Some**
`a)L) All
`1... Certified copies of the priority documents have been received.
`2.1.) Certified copies of the priority documents have been received in Application No.
`3.1.) Copies of the certified copies of the priority documents have been received in this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`* See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`1)
`
`Notice of References Cited (PTO-892)
`
`2) (J Information Disclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`Paper No(s)/Mail Date
`U.S. Patent and Trademark Office
`
`3) (J Interview Summary (PTO-413)
`Paper No(s)/Mail Date
`(Qj Other:
`
`4)
`
`PTOL-326 (Rev. 11-13)
`
`Office Action Summary
`
`Part of Paper No./Mail Date 20200401
`
`Application No.
`Applicant(s)
`16/172,322
`Nakagawa, Teruhisa
`
`Office Action Summary Art Unit|AIA (FITF) StatusExaminer
`CORY A ALMEIDA
`2622
`Yes
`
`
`
`-- The MAILING DATEofthis communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLYIS SET TO EXPIRE 3 MONTHS FROM THE MAILING
`DATE OF THIS COMMUNICATION.
`Extensions of time may be available underthe provisions of 37 CFR 1.136(a). In no event, however, may a reply betimely filed after SIX (6) MONTHSfrom the mailing
`date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHSfrom the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133}.
`Any reply received by the Office later than three months after the mailing date of this communication, evenif timely filed, may reduce any earned patent term
`adjustment. See 37 CFR 1.704(b).
`
`Status
`
`1) Responsive to communication(s)filed on 3/9/20.
`LC} A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/werefiled on
`2a)l¥) This action is FINAL.
`2b) (J This action is non-final.
`3) An election was madeby the applicant in responseto a restriction requirement set forth during the interview
`on
`; the restriction requirement and election have been incorporated into this action.
`4\(Z Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Exparte Quayle, 1935 C.D. 11, 453 O.G. 213.
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 2
`
`DETAILED ACTION
`
`The responsefiled 3/9/20 is entered. Claims 1, 4, 7, 10, 11, 13, 14, 16, and 17 are
`
`amended. Claims 12 and 15 are canceled. Claims 21 and 22 are new. Claims 1-11, 13,
`
`14, and 16-22 are pending.
`
`Notice of Pre-AlA or AIA Status
`
`1.
`
`The present application, filed on or after March 16, 2013, is being examined
`
`under the first inventor to file provisions of the AIA.
`
`Responseto Arguments
`
`2.
`
`Applicant's arguments filed on 3/29/20 have been fully considered but they are
`
`directed to newly amended claims and therefore believed to be answered by and thus
`
`moot in view of new grounds ofrejections presented below.
`
`Claim Rejections - 35 USC § 103
`
`3.
`
`In the event the determination of the status of the application as subject to AIA 35
`
`U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103)is incorrect, any
`
`correction of the statutory basis for the rejection will not be considered a new ground of
`
`rejection if the prior art relied upon, and the rationale supporting the rejection, would be
`
`the same under either status.
`
`4.
`
`The following is a quotation of 35 U.S.C. 103 which forms the basis for all
`
`obviousnessrejections setforth in this Office action:
`
`A patent for a claimed invention may not be obtained, notwithstanding that the claimed
`invention is not identically disclosed as set forth in section 102, if the differences between the
`claimed invention and the prior art are such that the claimed invention as a whole would have
`been obvious before the effective filing date of the claimed invention to a person having
`ordinary skill in the art to which the claimed invention pertains. Patentability shall not be
`negated by the manner in which the invention was made.
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 3
`
`5.
`
`Claims 1-11, 13, 14, and 16-22 is/are rejected under 35 U.S.C. 103 as being
`
`unpatentable over Liu, US-201 70206843in view of Yoon, US-20160189591 and n
`
`further view of Shin, US-20120154700.
`
`6.
`
`In regards to claim 1, Liu discloses a liquid crystal display device (Par. 0009-
`
`0010 display device utilizing LCD) comprising: a first display panel (Fig. 3, 03 OLED
`
`display panel) comprising a plurality offirst gate lines extending in a first direction and
`
`arranged in a second direction thatis different from the first direction in a first display
`
`region of the first display panel (Fig. 3, O83 OLED display panel; Fig. 5, gate line SL
`
`which arranged vertically but extend horizontally), and a plurality of first data lines
`
`extending in the second direction and arrangedin the first direction in the first display
`
`region (Fig. 3, 03 OLED display panel; Fig. 5, data line DL which arranged horizontally
`
`but extend vertically), and a second display panel (Fig. 3, 01 LCD panel) comprising a
`
`plurality of second gate lines and a plurality of second data lines in a second display
`
`region thereof (Fig. 3, 01 LCD panel; Fig. 5, data line DL and gate line SL; Par. 0076
`
`first pixel units of OLED and second pixel units of LCD are arrangedin 1:1
`
`correspondence); and a first driving circuit for one or more ofthe plurality of first gate
`
`lines and the plurality of first data lines, wherein the first driving circuit comprises one or
`
`morefirst drivers to provide signals to the one or moreofthe plurality of first gate lines
`
`and the plurality of first data lines (Fig. 3, 03 OLED panel; Fig. 5, data line DL and gate
`
`line SL; drivers for DL data lines and SL gate lines), wherein the first display panel and
`
`the second display panel overlap each other in plan view (Fig. 3, 03 OLED display panel
`
`and 01 LCD display panel ; Par. 0076first pixel units of OLED and secondpixel units of
`
`LCD are arranged in 1:1 correspondence).
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 4
`
`Liu does not disclose expressly at least one of two or more adjacent first gate
`
`lines from the plurality of first gate lines and two or more adjacent first data lines from
`
`the plurality of first data lines are provided with same signals at a same instant of time.
`
`Yoon discloses a first gate lines from the plurality of first gate lines and a data
`
`lines from the plurality offirst data lines provide same signals at a same instant of time
`
`to two adjacent gate rows and two adjacent data columns (Fig. 7, GL providing a same
`
`gate line signal to Q simultaneously and DL providing a same data signal to Q
`
`simultaneously for 4 pixels 191_1-191_ 4).
`
`At the time ofthe filing of the invention, it would have been obvious to one of
`
`ordinaryskill in the art the OLED display of Liu could be structured and driven in the
`
`manner of Yoon. The motivation for doing so would have been to increase
`
`transmittance, increase refreshing speed, and reduce wiring complexity (Par. 0180-
`
`0182).
`
`Liu and Yoon do not disclose expressly at least one of two or more adjacent first
`
`gate lines from the plurality of first gate lines and two or more adjacent first data lines
`
`from the plurality of first data lines are provided with same signals at a same instant of
`
`time.
`
`Shin discloses a single signalline (Fig. 1, GL) can provide a same signalto
`
`transistors of adjacent rows using a single gate line (Fig. 1, GL1; Par. 0051 and 0052
`
`providing a same signal to Qa and Qb) and via two gatelines that are connected (Fig. 1,
`
`GL1 and GL2; Par. 0051 and 0052 providing a same signal to Qa, Qb, and Qc).
`
`At the time ofthe filing of the invention, it would have been obvious to one of
`
`ordinaryskill in the art that the single gate line and single data line of Yoon providing a
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 5
`
`same signal to two adjacent gate rows and two adjacent data columns could instead be
`
`two separate but connected gate lines providing the same signal to two adjacent gate
`
`rows and two adjacent data but connectedlines providing the same signal to two
`
`adjacent data columns utilizing the teaching of Shin that a same signal can be applied
`
`to transistors of adjacent rows via a single gate line and connected gate lines (Shin Fig.
`
`1, GL1 and GL2; Shin Par. 0051 and 0052 providing a same signal to Qa, Qb, and Qc
`
`via a single or connectedline). The motivation for doing so would have been to provide
`
`the same function in a standard pixel matrix layout.
`
`Therefore, it would have been obvious to combine Yoon and Shin with Liu to
`
`obtain the invention of claim 1.
`
`7.
`
`In regards to claim 10 and the associated method of manufacturing claims 17-20,
`
`Liu discloses a liquid crystal display device (Par. 0009-0010 display device utilizing
`
`LCD) comprising: a first display panel (Fig. 3, 08 OLED display panel) comprising a
`
`plurality of first gate lines and a plurality offirst data lines in a first display region thereof
`
`(Fig. 3, 03 OLED display panel; Fig. 5, data line DL and gate line SL), wherein two
`
`adjacent first gate lines from the plurality of first gate lines and two adjacent first data
`
`lines from the plurality of first data lines define a first pixel in the first display region (Fig.
`
`3, O3OLED panel; Fig. 5, a pixel is defined as being between two adjacentdata lines DL
`
`and two adjacentgate lines SL); a second liquid crystal display panel (Fig. 3, 01 LCD
`
`panel) comprising a plurality of second gate lines and a plurality of second datalines in
`
`a second display region thereof (Fig. 3, 01 LCD panel; Fig. 5, data line DL and gateline
`
`SL; Par. 0076first pixel units of OLED and secondpixel units of LCD are arranged in
`
`1:1 correspondence), wherein two adjacent second gatelines from the plurality of
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 6
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`second gate lines and two adjacent second data lines from the plurality of second data
`
`lines define a second pixel in the second display region (Fig. 3, 01LCD panel; Fig. 5, a
`
`pixel is defined as being between two adjacent data lines DL and two adjacent gate
`
`lines SL), wherein the first display panel and the secondliquid crystal display panel
`
`overlap eachother in plan view (Fig. 3, 03 OLED display panel and 01LCD display
`
`panel; Par. 0076first pixel units of OLED and second pixel units of LCD are arrangedin
`
`1:1 correspondence), wherein the first display panel and the second liquid crystal
`
`display panel have equal densities offirst pixels and second pixels, respectively, therein
`
`(Fig. 3, 03 OLED display panel and 01LCD display panel; Par. 0076first pixel units of
`
`OLED and secondpixel units of LCD are arranged in 1:1 correspondence).
`
`Liu does not disclose expressly the first display panel is a liquid crystal display
`
`panel; wherein the first liquid crystal display panel displays at a lower definition as
`
`comparedto the secondliquid crystal display panel.
`
`Yoon discloses the display panel can bealiquid crystal display panel or OLED
`
`display panel with associated pixels (Par. 0006 providing liquid crystal pixels or OLED
`
`pixels); a first gate lines from the plurality offirst gate lines and a data lines from the
`
`plurality of first data lines provide same signals at a same instant of time to two adjacent
`
`gate rows and two adjacent data columns (Fig. 7, GL providing a same gateline signal
`
`to Q simultaneously and DL providing a same data signal to Q simultaneously for 4
`
`pixels 191_1-191_ 4).
`
`Shin discloses a single signalline (Fig. 1, GL) can provide a same signalto
`
`transistors of adjacent rows using a single gate line (Fig. 1, GL1; Par. 0051 and 0052
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 7
`
`providing a same signal to Qa and Qb) andvia two gatelines that are connected (Fig. 1,
`
`GL1 and GL2; Par. 0051 and 0052 providing a same signal to Qa, Qb, and Qc).
`
`At the time ofthe filing of the invention, it would have been obvious to one of
`
`ordinaryskill in the art that the single gate line and single data line of Yoon providing a
`
`same signal to two adjacent gate rows and two adjacent data columns could instead be
`
`two separate but connectedgate lines providing the same signal to two adjacent gate
`
`rows and two adjacent data but connectedlines providing the same signal to two
`
`adjacent data columns utilizing the teaching of Shin that a same signal can be applied
`
`to transistors of adjacent rows via a single gate line and connected gate lines (Shin Fig.
`
`1, GL1 and GL2; Shin Par. 0051 and 0052 providing a same signal to Qa, Qb, and Qc
`
`via a single or connectedline). The motivation for doing so would have been to provide
`
`the same function in a standard pixel matrix layout.
`
`Therefore, it would have been obvious to combine Yoon and Shin with Liu to
`
`obtain the invention of claim 10
`
`In regards to claim 2, Liu, Yoon, and Shin, as combined above, disclosethe first
`
`driving circuit comprisesafirst gate driving circuit for the plurality offirst gate lines and
`
`the one or morefirst drivers comprise one or morefirst gate drivers to provide gate
`
`signals to the plurality of first gate lines (Yoon Fig. 7, data line DL and gate line GL;
`
`Yoon drivers for DL data lines and GL gate lines), wherein two or more adjacentfirst
`
`gate lines from the plurality of first gate lines are provided with the same gate signals at
`
`the same instant of time (Yoon Fig. 7, GL providing a same gate line signal to Q
`
`simultaneously and DL providing a same data signal to Q simultaneously for 4 pixels
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 8
`
`191_1-191_4; Shin Fig. 1, GL1 and GL2; Shin Par. 0051 and 0052 providing a same
`
`signal to Qa, Qb, and Qc via a single or connectedline).
`
`In regards to claim 11, Liu, Yoon, and Shin, as combined above, disclosethefirst
`
`liquid crystal display panel (Yoon Par. 0006 providing liquid crystal pixels or OLED
`
`pixels) comprises a first gate driving circuit for the plurality of first gate lines and the one
`
`or morefirst drivers comprise one or morefirst gate drivers to provide gate signals to
`
`the plurality of first gate lines (Yoon Fig. 7, data line DL and gate line GL; Yoon drivers
`
`for DL data lines and GL gate lines), wherein two or more adjacentfirst gate lines from
`
`the plurality offirst gate lines are provided with the same gate signals at the same
`
`instant of time (Yoon Fig. 7, GL providing a same gateline signal to Q simultaneously
`
`and DL providing a same data signal to Q simultaneously for 4 pixels 191_1-191_ 4;
`
`Yoon Fig. 7, GL providing a same gateline signal to Q simultaneously and DL providing
`
`a same data signal to Q simultaneously for 4 pixels 191_1-191_4; Shin Fig. 1, GL1 and
`
`GL2; Shin Par. 0051 and 0052 providing a same signal to Qa, Qb, and Qcvia a single
`
`or connectedline), the two or more adjacent first gate lines from the plurality of first gate
`
`lines are electrically connected to each other by a gate lead connector, and wherein the
`
`gate lead connector is formed outside the first display region (Yoon Fig. 7, data line DL
`
`and gate line GL; Yoon drivers for DL data lines and GL gate lines; Yoon all the gate
`
`lines are connected to gate driver; Shin Fig. 1, GL1 and GL2; Shin Par. 0051 and 0052
`
`providing a same signal to Qa, Qb, and Qc via a single or connected line), and connects
`
`between the two or more adjacent first gate lines and one gate terminal of the one or
`
`morefirst gate drivers to receive the gate signals for the two or more adjacent first gate
`
`lines (Yoon Fig. 7, GL providing a same gateline signal to Q simultaneously and DL
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 9
`
`providing a same data signal to Q simultaneously for 4 pixels 191_1-191_4; Shin Fig. 1,
`
`GL1 and GL2; Shin Par. 0051 and 0052 providing a same signal to Qa, Qb, and Qc via
`
`a single or connectedline).
`
`In regards to claims 3 and 12, Liu, Yoon, and Shin, as combined above, disclose
`
`the two or more adjacent first gate lines from the plurality of first gate lines are
`
`electrically connected to each other by a gate lead connector, and wherein the gate lead
`
`connector is formed outside the first display region (Yoon Fig. 7, data line DL and gate
`
`line GL; Yoon drivers for DL data lines and GL gate lines; Yoon all the gate lines are
`
`connected to gate driver; Shin Fig. 1, GL1 and GL2; Shin Par. 0051 and 0052 providing
`
`a samesignal to Qa, Qb, and Qcvia a single or connected line), and connects between
`
`the two or more adjacent first gate lines and one gate terminal of the one or morefirst
`
`gate drivers to receive the gate signals for the two or more adjacent first gate lines
`
`(Yoon Fig. 7, GL providing a samegateline signal to Q simultaneously and DL
`
`providing a same data signal to Q simultaneously for 4 pixels 191_1-191_4; Shin Fig. 1,
`
`GL1 and GL2; Shin Par. 0051 and 0052 providing a same signal to Qa, Qb, and Qc via
`
`a single or connectedline).
`
`In regards to claims 4 and 13, Liu, Yoon, and Shin, as combined above, disclose
`
`the plurality of first gate lines includeafirst gate line group of the two or more adjacent
`
`first gate lines and a second gate line group of the two or more adjacent first gate lines,
`
`the first gate line group and the second gate line group being arranged immediately
`
`adjacent to each other, and whereinafirst gate terminal of the one or morefirst gate
`
`drivers electrically connects to the first gate line group, a second gate terminal of the
`
`one or morefirst gate drivers electrically connects to the second gate line group, and a
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 10
`
`third gate terminal of the one or morefirst gate drivers located between the first gate
`
`terminal and the second gate terminal is voided (Yoon Fig. 7, data line DL and gate line
`
`GL; Yoon drivers for DL data lines and GL gate lines; Yoon all the gate lines are
`
`connected to gate driver; Yoon Fig. 7, GL providing a same gate line signal to Q
`
`simultaneously and DL providing a same data signal to Q simultaneously for 4 pixels
`
`191_1-191_4; gate line groups of pixels; Shin Fig. 1, GL1 and GL2; Shin Par. 0051 and
`
`0052 providing a same signal to Qa, Qb, and Qc via a single or connectedline).
`
`In regards to claim 5, Liu, Yoon, and Shin, as combined above, disclosethe first
`
`driving circuit comprisesa first data driving circuit for the plurality of first data lines and
`
`the one or morefirst drivers comprise one or morefirst data drivers to provide data
`
`signals to the plurality of first data lines (Yoon Fig. 7, data line DL and gate line GL;
`
`Yoon drivers for DL data lines and GL gate lines), wherein two or more adjacentfirst
`
`data lines from the plurality of first data lines are provided with the same data signals at
`
`the same instant of time (Yoon Fig. 7, GL providing a same gate line signal to Q
`
`simultaneously and DL providing a same data signal to Q simultaneously for 4 pixels
`
`191_1-191_4; Shin Fig. 1, GL1 and GL2; Shin Par. 0051 and 0052 providing a same
`
`signal to Qa, Qb, and Qc via a single or connected line via a single or connectedline).
`
`In regards to claim 6, Liu, Yoon, and Shin, as combined above, disclose the two
`
`or more adjacentfirst data lines from the plurality of first data lines are electrically
`
`connected to each other by a data lead connector, and wherein the data lead connector
`
`is formed outside thefirst display region (Yoon Fig. 7, data line DL and gate line GL;
`
`Yoon drivers for DL data lines and GL gate lines; Yoon all the data lines are connected
`
`to data driver), and connects between the two or more adjacent first data lines and one
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 11
`
`data terminal of the one or morefirst data drivers to receive the data signals for the two
`
`or more adjacentfirst data lines (Yoon Fig. 7, GL providing a same gateline signal to Q
`
`simultaneously and DL providing a same data signal to Q simultaneously for 4 pixels
`
`191_1-191_4; Shin Par. 0051 and 0052 providing a same signal to Qa, Qb, and Qcvia
`
`a single or connectedline via a single or connectedline).
`
`In regards to claim 14, Liu, Yoon, and Shin, as combined above, disclosethefirst
`
`liquid crystal display panel (Yoon Par. 0006 providing liquid crystal pixels or OLED
`
`pixels) comprises a first data driving circuit for the plurality of first data lines and the one
`
`or morefirst drivers comprise one or morefirst data drivers to provide data signals to
`
`the plurality of first data lines (Yoon Fig. 7, data line DL and gate line GL; Yoon drivers
`
`for DL data lines and GL gate lines), wherein two or more adjacentfirst data lines from
`
`the plurality offirst data lines are provided with the same data signals at the same
`
`instant of time (Yoon Fig. 7, GL providing a same gateline signal to Q simultaneously
`
`and DL providing a same data signal to Q simultaneously for 4 pixels 191_1-191_4;
`
`Shin Par. 0051 and 0052 providing a same signal to Qa, Qb, and Qc via a single or
`
`connectedline via a single or connected line), wherein the two or more adjacent first
`
`data lines from the plurality of first data lines are electrically connected to each other by
`
`a data lead connector, and wherein the data lead connector is formed outside the first
`
`display region (Yoon Fig. 7, data line DL and gate line GL; Yoon drivers for DL data
`
`lines and GL gate lines; Yoon all the data lines are connectedto data driver), and
`
`connects between the two or more adjacentfirst data lines and one data terminal of the
`
`one or morefirst data drivers to receive the data signals for the two or more adjacent
`
`first data lines (Yoon Fig. 7, GL providing a same gateline signal to Q simultaneously
`
`

`

`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 12
`
`and DL providing a same data signal to Q simultaneously for 4 pixels 191_1-191_4;
`
`Shin Par. 0051 and 0052 providing a same signal to Qa, Qb, and Qc via a single or
`
`connected line via a single or connectedline).
`
`In regards to claims 7 and 16, Liu, Yoon, and Shin, as combined above, disclose
`
`the plurality of first data lines includeafirst data line group of the two or more adjacent
`
`first data lines and a second data line group of the two or more adjacent first data lines,
`
`the first data line group and the second data line group being arranged immediately
`
`adjacent to each other, and whereinafirst data terminal of the one or morefirst data
`
`drivers electrically connects to the first data line group, a second data terminal of the
`
`one or morefirst data drivers electrically connects to the second data line group, anda
`
`third data terminal of the one or morefirst data drivers located between the first data
`
`terminal and the second data terminal is voided (Yoon Fig. 7, data line DL and gate line
`
`GL; Yoon drivers for DL data lines and GL gate lines; Yoon all the data lines are
`
`connected to data driver; Yoon Fig. 7, GL providing a same gateline signal to Q
`
`simultaneously and DL providing a same data signal to Q simultaneously for 4 pixels
`
`191_1-191_4; data line groups of pixels; Shin Par. 0051 and 0052 providing a same
`
`signal to Qa, Qb, and Qc via a single or connectedline via a single or connectedline).
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`In regardsto claim 8, Liu, Yoon, and Shin, as combined above, disclose the a
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`second driving circuit for one or more of the plurality of second gate lines and the
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`plurality of second data lines (Liu Fig. 3, 01 LCD panel; Liu Fig. 5, data line DL and gate
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`line SL; Liu drivers for DL data lines and SL gate lines), wherein the second driving
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`circuit comprises one or more second drivers to provide signals to the one or more of
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`the plurality of second gate lines and the plurality of second data lines, and wherein a
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`

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`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 13
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`number offirst drivers are less than a number of second drivers (Liu Fig. 3, 01 LCD
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`panel; Liu Fig. 5, data line DL and gate line SL; Liu drivers for DL data lines and SL gate
`
`lines; Shin Par. 0051 and 0052 providing a same signal to Qa, Qb, and Qcvia a single
`
`or connectedline via a single or connected line; As combined above the number of gate
`
`and driving lines for OLED would be less than LCD lines which are driven
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`independently).
`
`In regards to claim 9, Liu, Yoon, and Shin, as combined above, disclose the a
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`second driving circuit for one or more of the plurality of second gate lines and the
`
`plurality of second data lines (Liu Fig. 3, 01 LCD panel; Liu Fig. 5, data line DL and gate
`
`line SL; Liu drivers for DL data lines and SL gate lines), wherein the second driving
`
`circuit comprises one or more second drivers to provide signals to the one or more of
`
`the plurality of second gate lines and the plurality of second data lines, and wherein a
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`number of terminals in the one or morefirst drivers are less than a number of terminals
`
`in the one or more seconddrivers (Liu Fig. 3, 01 LCD panel; Liu Fig. 5, data line DL and
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`gate line SL; Liu drivers for DL data lines and SL gate lines; Shin Par. 0051 and 0052
`
`providing a same signal to Qa, Qb, and Qc via a single or connectedline via a single or
`
`connectedline; As combined above the number of gate and driving lines for OLED
`
`would be less than LCD lines which are driven independently).
`
`In regards to claim 21, Liu, Yoon, and Shin, as combined above, do not disclose
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`expressly wherein the first display panel isafirst liquid crystal display panel, and the
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`second display panel is a secondliquid crystal display panel.
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`

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`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 14
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`Yoon further discloses the display panel can bealiquid crystal display panel or
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`OLED display panel with associated pixels (Par. 0006 providing liquid crystal pixels or
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`OLED pixels).
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`At the time ofthe filing of the invention, it would have been obvious to one of
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`ordinary skill in the art the OLED display of Liu, Yoon, and Shin could be an LCD
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`display or an OLED as Yoon discloses. The motivation for doing so would have been
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`that LCD panels are cheaper to manufacture and Yoon’s LCD increases transmittance,
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`increases refreshing speed, and reduce wiring complexity (Yoon Par. 0180-0182).
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`Therefore, it would have been obvious to combine Yoon with Liu to obtain the
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`invention of claim 21.
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`In regards to claim 22, Liu, Yoon, and Shin, as combined above, disclose the
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`gate lead connector extendsin the seconddirection (Liu Fig. 3, 03 OLED display panel:
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`Liu Fig. 5, gate line SL which arranged vertically but extend horizontally; Yoon Fig. 7,
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`data line DL and gate line GL; Yoon drivers for DL data lines and GL gate lines; Shin
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`Par. 0051 and 0052 providing a same signal to Qa, Qb, and Qcvia a single or
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`connectedline via a connectedline, i.e. gate lead connectors, which are arranged
`
`vertically).
`
`Conclusion
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`Applicant's amendment necessitated the new ground(s)of rejection presented in
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`this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP
`
`§ 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37
`
`CFR 1.136(a).
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`

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`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 15
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`A shortenedstatutory period for reply to this final action is set to expire THREE
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`
`
`MONTHS from the mailing date of this action. In the eventafirst replyis filed within
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`TWO MONTHS ofthe mailing date ofthis final action and the advisory action is not
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`mailed until after the end of the THREE-MONTH shortenedstatutory period, then the
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`shortened statutory period will expire on the date the advisory action is mailed, and any
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`extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of
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`the advisory action.
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`In no event, however,will the statutory period for reply expire later
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`than SIX MONTHS from the date of this final action.
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`Any inquiry concerning this communication or earlier communications from the
`
`examiner should be directed to CORY A ALMEIDA whosetelephone number is
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`(571)270-3143. The examiner can normally be reached on M-Th 9AM-730PM.
`
`Examiner interviews are available via telephone, in-person, and video
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`conferencing using a USPTO supplied web-based collaboration tool. To schedule an
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`If attempts to reach the examiner by telephone are unsuccessful, the examiner's
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`supervisor, Alexander Eisen can be reached on 571-272-7687. The fax phone number
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`for the organization where this application or proceeding is assigned is 571-273-8300.
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`Information regarding the status of an application may be obtained from the
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`Patent Application Information Retrieval (PAIR) system. Status information for
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`published applications may be obtained from either Private PAIR or Public PAIR.
`
`Status information for unpublished applications is available through Private PAIR only.
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`For more information about the PAIR system, see https://ppair-
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`

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`Application/Control Number: 16/172,322
`Art Unit: 2622
`
`Page 16
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`my.uspto.gov/pair/PrivatePair. Should you have questions on accessto the Private
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`PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197(toll-free).
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`
`/CORY A ALMEIDA/
`Examiner, Art Unit 2622
`6/5/20
`
`/ALEXANDER EISEN/
`Supervisory Patent Examiner, Art Unit 2622
`
`