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`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and TrademarkOffice
`Address; COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`
`16/543,204
`
`08/16/2019
`
`Hiroaki GOTO
`
`20326.0159USW1
`
`1925
`
`HAY
`
`M
`
`TLERS
`
`HAMRE, SCHUMANN, MUELLER & LARSON P.C.
`45 South Seventh Street
`Suite 2700
`MINNEAPOLIS, MN 55402-1683
`
`STONE, ROBERT M
`
`2628
`
`PAPER NUMBER
`
`NOTIFICATION DATE
`
`DELIVERY MODE
`
`06/12/2020
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
`following e-mail address(es):
`PTOMail @hsml.com
`
`PTOL-90A (Rev. 04/07)
`
`

`

`
`
`Disposition of Claims*
`1-12 is/are pending in the application.
`)
`Claim(s)
`5a) Of the above claim(s) ___ is/are withdrawn from consideration.
`CC) Claim(s)
`is/are allowed.
`Claim(s) 1-12 is/are rejected.
`S)
`) O Claim(s)___is/are objected to.
`C) Claim(s
`are subjectto restriction and/or election requirement
`)
`S)
`* If any claims have been determined allowable, you maybeeligible to benefit from the Patent Prosecution Highway program at a
`participating intellectual property office for the corresponding application. For more information, please see
`http://www.uspto.gov/patents/init_events/pph/index.jsp or send an inquiry to PPHfeedback@uspto.gov.
`
`) )
`
`Application Papers
`10)L) The specification is objected to by the Examiner.
`11) The drawing(s) filed on 8/16/2019 is/are: a)(¥) accepted or b)() objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`12) Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d)or (f).
`Certified copies:
`cc) None ofthe:
`b)LJ Some**
`a)Y) All
`1.4) Certified copies of the priority documents have been received.
`2.2 Certified copies of the priority documents have been received in Application No.
`3.4) Copies of the certified copies of the priority documents have been receivedin this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`* See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`1)
`
`Notice of References Cited (PTO-892)
`
`Information Disclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`2)
`Paper No(s)/Mail Date
`U.S. Patent and Trademark Office
`
`3) (J Interview Summary (PTO-413)
`Paper No(s)/Mail Date
`(Qj Other:
`
`4)
`
`PTOL-326 (Rev. 11-13)
`
`Office Action Summary
`
`Part of Paper No./Mail Date 20200607
`
`Application No.
`Applicant(s)
`16/543,204
`GOTOetal.
`
`Office Action Summary Art Unit|AIA (FITF) StatusExaminer
`ROBERT M STONE
`2628
`Yes
`
`
`
`-- The MAILING DATEofthis communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLYIS SET TO EXPIRE 3 MONTHS FROM THE MAILING
`DATE OF THIS COMMUNICATION.
`Extensions of time may be available underthe provisions of 37 CFR 1.136(a). In no event, however, may a reply betimely filed after SIX (6) MONTHSfrom the mailing
`date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHSfrom the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133}.
`Any reply received by the Office later than three months after the mailing date of this communication, evenif timely filed, may reduce any earned patent term
`adjustment. See 37 CFR 1.704(b).
`
`Status
`
`1) Responsive to communication(s) filed on 8/16/2019.
`LC} A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/werefiled on
`
`2a)(J This action is FINAL. 2b))This action is non-final.
`3) An election was madeby the applicant in responseto a restriction requirement set forth during the interview
`on
`; the restriction requirement and election have been incorporated into this action.
`4\(Z Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Exparte Quayle, 1935 C.D. 11, 453 O.G. 213.
`
`

`

`Application/Control Number: 16/543,204
`Art Unit: 2628
`
`Page 2
`
`DETAILED ACTION
`
`Notice of Pre-AlA or AIA Status
`
`1.
`
`The present application, filed on or after March 16, 2013, is being examined under the first
`
`inventor to file provisions of the AIA.
`
`Claim Rejections - 35 USC § 102
`
`2.
`
`In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102
`
`and 103 (or as subject to pre-AlA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory
`
`basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and
`
`the rationale supporting the rejection, would be the same under eitherstatus.
`
`3.
`
`The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis
`
`for the rejections under this section made in this Office action:
`
`A person shall be entitled to a patent unless —
`
`(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale
`or otherwise available to the public before the effective filing date of the claimed invention.
`
`(a)(2) the claimed invention was described in a patent issued under section 151, or in an application
`for patent published or deemed published under section 122(b), in which the patent or application, as
`the case may be, namesanother inventor and was effectively filed before the effective filing date of
`the claimed invention.
`
`4.
`
`Claims 1-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Morita
`
`(20020075248).
`
`As to claim 1, Morita (Fig. 17) discloses a display device (liquid crystal display device
`
`[0191]) comprising:
`
`a plurality of source lines extendingin a first direction (data lines D1-Dn extending in a
`
`vertical direction [0067]);
`
`a plurality of gate lines extending in a second direction (the 5 shown scanninglines of
`
`the display area from (L1,R1) to (L5,R5) extending in the horizontal direction [0067]);
`
`

`

`Application/Control Number: 16/543,204
`Art Unit: 2628
`
`Page 3
`
`a plurality of selection transistors in each of which a first conduction electrode is
`
`electrically connected to each of the plurality of gate lines (plurality of transistors 77a and 78a
`
`each with a first end connected to scanning lines L1-L5 [0122]);
`
`a plurality of selection signal supply lines each electrically connected to a control
`
`electrode of each of the plurality of selection transistors, each of the selection signal supply lines
`
`being electrically connected to the control electrode of at least two of the selection transistors
`
`(judging unit 94a outputs a control signal which is split into two opposing signals using 76a
`
`wherethe first line is connected to the column of transistors 77a at their gate electrodes and
`
`the second line is connected to the column of transistors 78a at their gate electrode
`
`[0122,0193]);
`
`a plurality of gate voltage supply lines each connected to a second conduction electrode
`
`of each of the plurality of selection transistors, each of the gate voltage supply lines being
`
`connected to the second conduction electrode of at least two of the selection transistors
`
`(second terminal of the transistor pair 77a and 78a in the column is connected to gate voltage
`
`lines GL1-GL5 and supplies the voltage to scan lines L1-L5 based on the control signal from
`
`judging unit 94a [0122,0193]);
`
`a gate driver electrically connected to the plurality of selection signal supply lines and
`
`the plurality of gate voltage supply lines (scanning driver 71a outputs gate voltage lines GL1-GL5
`
`to transistor pair 77a and 78a whichis electrically controlled by selection signal lines to transmit
`
`GL1-GL5 to display scan lines L1-L5 [0118,0122]);
`
`a plurality of failure detection transistors in each of which a control electrodeis
`
`electrically connected to each of the plurality of gate lines (control terminal of each transistor
`
`93a of the column oftransistors is connected to a gate voltage line and through 77a/78a to a
`
`start L and end R of the corresponding scan line [0193,0200));
`
`

`

`Application/Control Number: 16/543,204
`Art Unit: 2628
`
`Page 4
`
`a plurality of monitor input signal lines each electrically connected to a first conduction
`
`electrode of each of the plurality of failure detection transistors, each of the monitor input
`
`signal lines being electrically connected to the first conduction electrode of at least two of the
`
`failure detection transistors (input node Lin forks into two input lines which are therefore both
`
`electrically connected to first terminal of each transistor 93a of the column of transistors
`
`[0075,0126,0179,0193,0200]); and
`
`a plurality of monitor output signal lines each electrically connected to a second
`
`conduction electrode of each of the plurality of failure detection transistors, each of the monitor
`
`outputsignal lines being electrically connected to the second conduction electrode ofat least
`
`twoof the failure detection transistors (judging unit 94a receives inputs from 2 monitor output
`
`signal lines which are bothelectrically connected since they are connected to the outputs of
`
`transistor columns 75a and 93a both which are connected to Lin [0076,0125,0126]).
`
`As to claim 8, Morita (Fig. 17) discloses a display device (liquid crystal display device
`
`[0191]) comprising:
`
`a plurality of source lines extendingin a first direction (data lines D1-Dn extending in a
`
`vertical direction [0067]);
`
`a plurality of gate lines extending in a second direction (scanning lines of the display
`
`area from (L1,R1) to (Ln,Rn) extending in the horizontal direction [0067));
`
`a plurality of first selection transistors in each of which a first conduction electrodeis
`
`electrically connected to a first end of each of the plurality of gate lines (plurality of transistors
`
`77a and 78a each with a first end connected to scanninglines L1-Ln [0122));
`
`a plurality of second selection transistors in each of which a first conduction electrode is
`
`electrically connected to a second end of each of the plurality of gate lines (plurality of
`
`transistors 77b and 78b each witha first end connected to scanning lines R1-Rn [0123));
`
`

`

`Application/Control Number: 16/543,204
`Art Unit: 2628
`
`Page 5
`
`a plurality of first selection signal supply lines each electrically connected to a control
`
`electrode of each of the plurality of first selection transistors, each of the first selection signal
`
`supply lines being electrically connected to the control electrode of at least two of the first
`
`selection transistor (judging unit 94a outputs a control signal whichis split into two opposing
`
`signals using 76a wherethefirst line is connected to the column of transistors 77a at their gate
`
`electrodes and the second line is connected to the column of transistors 78a at their gate
`
`electrode [0122,0193));
`
`a plurality of second selection signal supply lines each electrically connected to a control
`
`electrode of each of the plurality of second selection transistors, each of the second selection
`
`signal supply lines being electrically connected to the control electrode of at least two of the
`
`second selection transistor (judging unit 94b outputs a control signal which is split into two
`
`opposing signals using 76b wherethe first line is connected to the column of transistors 77b at
`
`their gate electrodes and the second line is connected to the column of transistors 78b at their
`
`gate electrode [0122,0193));
`
`a plurality of first gate voltage supply lines each connected to a second conduction
`
`electrode of each of the plurality of first selection transistors, each of the first gate voltage
`
`supply lines being electrically connected to the second conduction electrode of at least two of
`
`the selection transistors (second terminal of the transistor pair 77a and 78a in the column is
`
`connected to gate voltage lines GL1-GLn and supplies the voltage to scan lines L1-Ln based on
`
`the control signal from judging unit 94a [0122,0193]);
`
`a plurality of second gate voltage supply lines each connected to a second conduction
`
`electrode of each of the plurality of second selection transistors, each of the second gate
`
`voltage supply lines being electrically connected to the second conduction electrode ofat least
`
`twoof the selection transistors (second terminal of the transistor pair 77b and 78b in the
`
`

`

`Application/Control Number: 16/543,204
`Art Unit: 2628
`
`Page 6
`
`column is connected to gate voltage lines GR1-GRn and supplies the voltage to scan lines R1-Rn
`
`based on the control signal from judging unit 94b [0123,0193]);
`
`a first gate driver electrically connected to the plurality of first selection signal supply
`
`lines and the plurality of first gate voltage supply lines (scanning driver 71a outputs gate voltage
`
`lines GL1-GLnto transistor pair 77a and 78a which is electrically controlled by selection signal
`
`lines to transmit GL1-n to display scan lines L1-Ln [0118,0122));
`
`a second gatedriver electrically connected to the plurality of second selection signal
`
`supply lines and the plurality of second gate voltage supply lines (scanning driver 71b outputs
`
`gate voltage lines GR1-GRn totransistor pair 77b and 78b whichis electrically controlled by
`
`selection signal lines to transmit GR1-GRn to display scan lines L1-Ln [0118,0123)]);
`
`a plurality of first failure detection transistors in each of which a control electrodeis
`
`electrically connected to the second end of each of the plurality of gate lines (control terminal of
`
`each transistor 93a of the column of transistors is connected to a gate voltage line and through
`
`77a/78a to a start Land end R of the corresponding scan line [0193,0200]);
`
`a plurality of second failure detection transistors in each of which a control electrode is
`
`electrically connected to the first end of each of the plurality of gate lines (control terminal of
`
`each transistor 93b of the column of transistors is connected to a gate voltage line and through
`
`77b/78b to a start L and end R of the corresponding scan line [0193,0200]);
`
`a plurality of first monitor input signal lines each electrically connected toafirst
`
`conduction electrode of each of the plurality of first failure detection transistors, each of the
`
`first monitor input signal lines being electrically connected to the first conduction electrode of
`
`eachofat least two ofthe first failure detection transistors (input node Lin forks into two input
`
`lines which are therefore both electrically connected to first terminal of each transistor 93a of
`
`the column of transistors [0075,0126,0179,0193,0200));
`
`

`

`Application/Control Number: 16/543,204
`Art Unit: 2628
`
`Page 7
`
`a plurality of second monitor input signal lines each electrically connected to a first
`
`conduction electrode of each of the plurality of second failure detection transistors, each of the
`
`second monitor input signal lines being electrically connected to the first conduction electrode
`
`of each of at least two of the second failure detection transistors (input node Rin forks into two
`
`input lines which are therefore both electrically connectedto first terminal of each transistor
`
`93b of the column of transistors [(0075,0126,0179,0193,0200));
`
`a plurality of first monitor output signal lines each electrically connected to a second
`
`conduction electrode of each of the plurality of first failure detection transistors, each of the
`
`first monitor output signal lines being electrically connected to the second conduction electrode
`
`of each of at least two ofthe first failure detection transistors (judging unit 94a receives inputs
`
`from 2 monitor output signal lines which are both electrically connected since they are
`
`connected to the outputs of transistor columns 75a and 93a both which are connectedto Lin
`
`[0076,0125,0126]); and
`
`a plurality of second monitor output signal lines each electrically connected to a second
`
`conduction electrode of each of the plurality of second failure detection transistors, each of the
`
`second monitor output signal lines being electrically connected to the second conduction
`
`electrode of each of at least two of the second failure detection transistors (judging unit 94b
`
`receives inputs from 2 monitor outputsignal lines which are both electrically connected since
`
`they are connected to the outputs of transistor columns 75b and 93b both which are connected
`
`to Lin [(0076,0125,0126]).
`
`As to claim 2, Morita (Fig. 17) discloses each of the plurality of failure detection
`
`transistors electrically connected to one monitor input signal line included in the plurality of
`
`monitor input signal lines, among the plurality of failure detection transistors, is electrically
`
`connected to one monitor outputsignal line included in the plurality of monitor output signal
`
`

`

`Application/Control Number: 16/543,204
`Art Unit: 2628
`
`Page 8
`
`lines (each failure detection transistor 93a is connected between monitor inputlines, receiving
`
`the input check signal from terminal Lin, and output lines which connect to judging unit 94a to
`
`transmit Lin to 94a based on the control signal [0193,0200]).
`
`As to claim 3, Morita (Fig. 17) discloses a determination part that determinesa failure of
`
`at least one of the plurality of gate lines, the plurality of gate voltage supply lines, and the
`
`plurality of selection signal supply lines based on a voltage level of a monitor output signal
`
`output from the plurality of monitor outputsignal lines (judging unit 94a receives check signal
`
`from terminal Lin in accordance with control of transistors 93a by the gate line voltage to
`
`determine, identify, and autocorrect gate signal abnormalities [0080,0129,0153,0193]).
`
`As to claim 4, Morita (Fig. 17) discloses the determination part detects a position of the
`
`failure when the failure is generated in at least one of the plurality of gate lines, the plurality of
`
`gate voltage supply lines, and the plurality of selection signal supply lines (identifies which gate
`
`line, which has a designated location, has abnormalities [0080,0129,0153,0193]).
`
`As to claim 5, Morita (Fig. 17) discloses the determination part determines the failure
`
`based on a pattern for one frame of the voltage level of the monitor output signal (counts pulses
`
`based ona frame to output the resulting value [0156,0174,0184)]).
`
`As to claim 6, Morita (Fig. 17) discloses the number of the plurality of gate voltage
`
`supply lines is not an integral multiple of the number of the plurality of monitor output signal
`
`lines (two monitor outputsignal lines is not an integral multiple of 5 gate voltage lines GL1-GL5).
`
`As to claim 7, Morita (Fig. 17) discloses a least common multiple of the number of the
`
`plurality of gate voltage supply lines, the number of the gate lines included in one block, and the
`
`number of the plurality of monitor output signal lines is greater than or equal to a total number
`
`of the plurality of gate lines (5 gate voltage supply lines GL1-GL5; NANDs 73a connect adjacent
`
`

`

`Application/Control Number: 16/543,204
`Art Unit: 2628
`
`Page 9
`
`gate lines forming a block of 2; 2 monitor output signal lines; so least common multiple of 10 is
`
`greater than the 5 gate lines L1-L5).
`
`As to claim 9, Morita (Fig. 17) discloses the display device includes: a first mode in which
`
`the plurality of gate lines are driven by the plurality of first selection transistors, the plurality of
`
`first selection signal supply lines, the plurality of first gate voltage supply lines, and the first gate
`
`driver while a failure of at least one of the plurality of gate lines, the plurality of first gate
`
`voltage supply lines, and the plurality of first selection signal supply lines is determined based on
`
`a voltage level of a first monitor output signal output from the plurality of first monitor output
`
`signal lines, and a second mode in which the plurality of gate lines are driven by the plurality of
`
`second selection transistors, the plurality of second selection signal supply lines, the plurality of
`
`second gate voltage supply lines, and the second gate driver while a failure of at least one of the
`
`plurality of gate lines, the plurality of second gate voltage supply lines, and the plurality of
`
`second selection signal supply lines is determined based on a voltage level of a second monitor
`
`output signal output from the plurality of second monitor output signal lines (multiple driving
`
`modesare defined depending on abnormalities detected by the judging units 94a/94bincluding
`
`disabling the individual line or an entire left or right side [0079,0080,0129,0144,0153,0224]).
`
`As to claim 10, Morita (Fig. 17) discloses the first mode and the second mode are
`
`mutually switched in a predetermined period (the left and right sides are sequentially driven at a
`
`predetermined timing [0136,0142,0179]).
`
`As to claim 11, Morita (Fig. 17) discloses when the failure is generated in at least one of
`
`the plurality of first gate voltage supply lines and the plurality of first selection signal supply lines
`
`in the first mode, subsequent operation is performed in the second mode, and when the failure
`
`is generated in at least one of the plurality of second gate voltage supply lines and the plurality
`
`of second selection signal supply lines in the second mode, subsequent operation is performed
`
`

`

`Application/Control Number: 16/543,204
`Art Unit: 2628
`
`Page 10
`
`in the first mode (when abnormalities are detected by the left judging unit 94a, driving is
`
`performedby the right side driver and when abnormalities are detected by the right judging unit
`
`94b, driving is performed by the left side driver [0079,0080,0153,0224)]).
`
`As to claim 12, Morita (Fig. 17) discloses when the failure is generated in at least one of
`
`the plurality of first gate voltage supply lines and the plurality of first selection signal supply lines
`
`in the first mode, subsequent operation is performed in the second mode, and when the failure
`
`is generated in at least one of the plurality of second gate voltage supply lines and the plurality
`
`of second selection signal supply lines in the second mode, subsequent operation is performed
`
`in the first mode (when abnormalities are detected by the left judging unit 94a, driving is
`
`performedby the right side driver and when abnormalities are detected by the right judging unit
`
`94b, driving is performed by the left side driver [0079,0080,0153,0224)).
`
`Conclusion
`
`Any inquiry concerning this communication or earlier communications from the examiner
`
`should be directed to ROBERT M STONE whosetelephone number is (571)270-5310. The examiner can
`
`normally be reached on 9:30am-6pm.
`
`Examiner interviewsare available via telephone, in-person, and video conferencing using a
`
`USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use
`
`the USPTO Automated Interview Request(AIR) at http://www.uspto.gov/interviewpractice.
`
`If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor,
`
`Nitin Patel can be reached on (571) 272-7677. The fax phone numberfor the organization where this
`
`application or proceeding is assigned is 571-273-8300.
`
`Information regarding the status of an application may be obtained from the Patent Application
`
`Information Retrieval (PAIR) system. Status information for published applications may be obtained
`
`

`

`Application/Control Number: 16/543,204
`Art Unit: 2628
`
`Page 11
`
`from either Private PAIR or Public PAIR. Status information for unpublished applications is available
`
`through Private PAIR only. For more information about the PAIR system, see https://ppair-
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`my.uspto.gov/pair/PrivatePair. Should you have questions on accessto the Private PAIR system, contact
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`the Electronic Business Center (EBC) at 866-217-9197(toll-free). If you would like assistance from a
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`9199 (IN USA OR CANADA)or 571-272-1000.
`
`/ROBERT M STONE/
`Examiner, Art Unit 2628
`
`/NITIN PATEL/
`Supervisory Patent Examiner, Art Unit 2628
`
`