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`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and TrademarkOffice
`Address; COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`
`16/694,428
`
`11/25/2019
`
`Yugo TAKEDA
`
`20295 .0056US01
`
`4015
`
`HAY
`
`iM
`
`TEER!
`
`HAMRE, SCHUMANN, MUELLER & LARSON P.C.
`45 South Seventh Street
`Suite 2700
`
`MINNEAPOLIS, MN 55402-1683
`
`MAZUMDER, DIDARUL A
`
`2819
`
`09/01/2021
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
`following e-mail address(es):
`PTOMail @hsml.com
`
`PTOL-90A (Rev. 04/07)
`
`

`

`Application No.
`Applicant(s)
`16/694,428
`TAKEDAet al.
`
`Office Action Summary Art Unit|AIA (FITF) StatusExaminer
`DIDARUL A MAZUMDER
`2819
`Yes
`
`
`
`-- The MAILING DATEofthis communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLYIS SET TO EXPIRE 3 MONTHS FROM THE MAILING
`DATE OF THIS COMMUNICATION.
`Extensions of time may be available underthe provisions of 37 CFR 1.136(a). In no event, however, may a reply betimely filed after SIX (6) MONTHSfrom the mailing
`date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHSfrom the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133}.
`Any reply received by the Office later than three months after the mailing date of this communication, evenif timely filed, may reduce any earned patent term
`adjustment. See 37 CFR 1.704(b).
`
`Status
`
`1) Responsive to communication(s) filed on 06/17/2021.
`C} A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/werefiled on
`
`2a)L) This action is FINAL. 2b)¥)This action is non-final.
`3)02 An election was madeby the applicant in responseto a restriction requirement set forth during the interview
`on
`; the restriction requirement and election have been incorporated into this action.
`4\0) Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Exparte Quayle, 1935 C.D. 11, 453 O.G. 213.
`
`
`
`Disposition of Claims*
`1-20 is/are pending in the application.
`)
`Claim(s)
`5a) Of the above claim(s) 11-15 and 17-20 is/are withdrawn from consideration.
`1) Claim(s)__ is/are allowed.
`Claim(s) 1-2 and 16 is/are rejected.
`)
`Claim(s) 3-10 is/are objected to.
`O Claim(s
`are subject to restriction and/or election requirement
`)
`“ If any claims have been determined allowable, you maybeeligible to benefit from the Patent Prosecution Highway program at a
`participating intellectual property office for the corresponding application. For more information, please see
`http:/Awww.uspto.gov/patents/init_events/pph/index.jsp or send an inquiry to PPHfeedback@uspto.gov.
`
`Application Papers
`10)C) The specification is objected to by the Examiner.
`11) The drawing(s) filed on 11/25/2019 is/are: a) accepted or b)C) objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`12) Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
`Certified copies:
`—_c)LJ None ofthe:
`b)LJ Some**
`a)Y) All
`1.4) Certified copies of the priority documents have been received.
`2.1) Certified copies of the priority documents have been received in Application No.
`3.2.) Copies of the certified copies of the priority documents have been receivedin this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`* See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`1)
`
`Notice of References Cited (PTO-892)
`
`Information Disclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`2)
`Paper No(s)/Mail Date
`U.S. Patent and Trademark Office
`
`3) (J Interview Summary (PTO-413)
`Paper No(s)/Mail Date
`(Qj Other:
`
`4)
`
`PTOL-326 (Rev. 11-13)
`
`Office Action Summary
`
`Part of Paper No./Mail Date 20210817
`
`

`

`Application/Control Number: 16/694,428
`Art Unit: 2819
`
`Page 2
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`Notice of Pre-AlA or AIA Status
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`1.
`
`The present application, filed on or after March 16, 2013, is being examined
`
`under the first inventor to file provisions of the AIA.
`
`2.
`
`This action is responsive to the application No. 16/694,428 filed on June 17, 2021.
`
`DETAILED ACTION
`
`Priority
`
`3.
`
`Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which
`
`papers have been placedof recordin the file.
`
`Information Disclosure Statement
`
`4.
`
`Acknowledgementis made of Applicant’s Information Disclosure Statement (IDS)
`
`form PTO-1449. These IDS has been considered.
`
`Election/Restrictions
`
`5.
`
`Applicant’s election of claims 1-10, 16 w.r.t. species | (Fig. 1) in the reply filed on
`
`06/17/2021 is acknowledged. Because applicant did not distinctly and specifically point
`
`out the supposederrors in the restriction requirement, the election has been treated as
`
`an election without traverse (MPEP § 818.01(a)).
`
`6.
`
`Claims 11-15, 17-20 are withdrawn from further consideration pursuant to 37
`
`CFR 1.142(b) as being drawn to a nonelected species claims, there being no allowable
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`generic or linking claim.
`
`

`

`Application/Control Number: 16/694,428
`Art Unit: 2819
`
`Page 3
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`Claim Objections
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`7.
`
`Claims 1, 3, 4, 5, 6, 7 are objected to because ofthe following informalities:
`
`The following quoted claims to be recited as follows to makecorrections that
`
`would avoid indefiniteness due to lack of antecedent basis and/or proper alignmentof
`
`the claim limitations. Therefore, the examiner suggests the following amendments as
`
`underlined:
`
`Claim 7. (As interoreied} A thin film transistor substrate including 4pixel region
`
`constructed with a plurality of pixels and a frame region surrounding the pixel region, the
`
`thin fim transistor substrate comprising:
`
`thin film transistors and pixel electrades provided in each of the plurality of pels
`
`respectively:
`
`a oluralily of gate signal ines extencing in a first direction in the pixel region and
`
`supplying @ gate signal to the thin film transistors in the plurality of pixels:
`
`& plurality of gate leac-out lines and a plurality of dummy gate leac-oul ines
`
`exiending in a second direction different from the first direction in the pixel regiori:
`
`a tlurality af common lines extending in atleast one of the first direction and the
`
`second direction in the pixel region, a common potential being applied to the plurality of
`
`common lines: and
`
`a common elecirace provided oppasite to the pixel electrodes and electrically
`
`connected to ine plurality of common lines,
`
`

`

`Application/Control Number: 16/694,428
`Art Unit: 2819
`
`Page 4
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`wherein the glurality of gate lead-out lines are connected to the plurality of gate
`
`signal ines atleast ai one paint of a plurality of intersections oetween the plurality af
`
`gate signal lines and the plurahty of gate lead-out lines, anc ihe common potential is
`
`apolied to the plurality of dummy gate lead-out lines.
`
`Claim 3. (As interpreted) The thin film transistor substrate according to claim 2,
`
`further comprising:
`
`a shield electrode formed in the frame region, the common potential being
`
`applied to the shield electrode; and
`
`a plurality of first connection wirings respectively connecting the plurality of
`
`dummy gate lead-out lines and the shield electrode through respective first contact
`
`holes made in the frame region.
`
`Claim 4. (As interpreted) The thin film transistor substrate according to claim 3,
`
`wherein the plurality of first connection wirings are formedin a layer identical te+hat of
`
`the pixel electrodes.
`
`Claim 5. (As interpreted) The thin film transistor substrate according to claim 3,
`
`wherein the plurality of first connection wirings are formed in a layer identical to thatef
`
`the common electrode.
`
`Claim 6. (As interpreted) The thin film transistor substrate according to claim 3,
`
`wherein the plurality of first connection wirings are formedin a layer identical to thatef a
`
`source-drain electrode of the thin film transistor.
`
`

`

`Application/Control Number: 16/694,428
`Art Unit: 2819
`
`Page 5
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`Claim 7. (As interpreted) The thin film transistor substrate according to claim 3,
`
`wherein the shield electrode is formed in a layer identical to #hatef the plurality of
`
`dummy gate lead-outlines.
`
`Appropriate corrections are required.
`
`Claim Rejections - 35 USC § 103
`
`8.
`
`In the event the determination of the status of the application as subject to AIA 35
`
`U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103)is incorrect, any
`
`correction of the statutory basis for the rejection will not be considered a new ground of
`
`rejection if the prior art relied upon, and the rationale supporting the rejection, would be
`
`the same under either status.
`
`9.
`
`The following is a quotation of 35 U.S.C. 103 which forms the basis for all
`
`obviousnessrejections setforth in this Office action:
`
`A patent for a claimed invention may not be obtained, notwithstanding that
`the claimed invention is not identically disclosed as set forth in section
`102, if the differences between the claimed invention and the prior art are
`such that the claimed invention as a whole would have been obvious
`before the effective filing date of the claimed invention to a person having
`ordinaryskill in the art to which the claimed invention pertains.
`Patentability shall not be negated by the manner in which the invention
`was made.
`
`10.
`
` =This application currently names joint inventors. In considering patentability of the
`
`claims under pre-AlA 35 U.S.C. 103(a), the examiner presumesthat the subject matter
`
`of the various claims was commonly ownedatthe time any inventions covered therein
`
`were made absent any evidenceto the contrary. Applicant is advised of the obligation
`
`

`

`Application/Control Number: 16/694,428
`Art Unit: 2819
`
`Page 6
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`under 37 CFR 1.56 to point out the inventor and invention dates of each claim that was
`
`not commonly ownedat the time a later invention was made in order for the examiner to
`
`consider the applicability of pre-AIA 35 U.S.C. 103(c) and potential pre-AIA 35 U.S.C.
`
`102(e), (f) or (g) prior art under pre-AlA 35 U.S.C. 103(a).
`
`11.+‘The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148
`
`USPQ 459 (1966), that are applied for establishing a background for determining
`
`obviousness under 35 U.S.C. 103 are summarized as follows:
`
`a. Determining the scope and contentsof the prior art.
`
`b. Ascertaining the differences between the prior art and the claims at issue.
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`c. Resolving the level of ordinary skill in the pertinent art.
`
`d. Considering objective evidence presentin the application indicating
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`obviousness or nonobviousness.
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`12.
`
`Claims 1-2, 16 are rejected under 35 U.S.C. 103 as being unpatentable over
`
`Kawamuraetal. (2016/0093261 A1) in view of Yang etal. (2017/0294172 A1).
`
`Regarding independentclaim 1, Kawamura etal. teachesa thin film transistor
`
`substrate (230 shownin Fig. 7, 459) including a pixel region (800 shownin Fig. 1, 448)
`
`constructed with a plurality of pixels (PA, 950) and a frame region (410/420/430/440
`
`shownin Fig. 1, 443) surrounding the pixel region (300), the thin film transistor substrate
`
`(231, 959, Fig. 7) comprising:
`
`thin film transistors (TRs, Fig. 4) and pixel electrodes (PEs, Fig. 4) provided in
`
`eachof the plurality of pixels (Y49) respectively;
`
`

`

`Application/Control Number: 16/694,428
`Art Unit: 2819
`
`Page 7
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`a plurality of gate signal lines (GL1....GL3, 952, Fig. 4) extending in a first
`
`direction (horizontal or X direction) in the pixel region (300) and supplying a gate signal
`
`to the thin film transistors (TRs) in the plurality of pixels (see Fig. 4);
`
`a plurality of gate lead-out lines (GD1....GD6, 946, see Fig. 3) andaplurality of
`
`dummy gate lead-out lines (GDs to which the gate signal is not output, 487) extending
`
`in a second direction (vertical or Y direction) different from the first direction (horizontal
`
`or X direction) in the pixel region (300);
`
`a plurality of common lines (Vcom) extending in at least one of the first direction
`
`and the second direction (perpendicular or vertical direction, see Fig. 4) in the pixel
`
`region (300),
`
`a common electrode (CE, 950) provided opposite to the pixel electrode (PE, 950)
`
`and electrically connected to the plurality of common lines (Vcom),
`
`wherein
`
`the plurality of gate lead-out lines (GD1....GD6) are connected to the gate signal
`
`lines (GL1....GL3) at least at one point of a plurality of intersections (CP1, CP2, CP3....)
`
`between the plurality of gate signal lines (GL1....GL3) and the plurality of gate lead-out
`
`lines (GD1....GD6).
`
`Kawamura etal. is explicitly silent of disclosing wherein a common potential
`
`being applied to the plurality of common lines;
`
`the common potential is applied to the plurality of dummy gate lead-out lines.
`
`

`

`Application/Control Number: 16/694,428
`Art Unit: 2819
`
`Page 8
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`Yang et al. teaches wherein (Figs. 6-7) a common potential (104’: Vcom, 951,
`
`see Fig. 6) being applied to the plurality of common lines (Vcom);
`
`the commonpotential (104’) is applied to the plurality of dummy gate lead-out
`
`lines (128 an extending portion of 120, 468).
`
`It would have been obvious to a person of ordinary skill in the art before the
`
`effective filing date of the invention to apply the teaching as taught by Yang etal. while
`
`forming the display panel of Kawamuraetal., in order to distribute a common electrode
`
`voltage such as common electrode voltage Vcom to nodes such as node 104 in each
`
`pixel 90 of array 92 (60).
`
`Regarding claim 2, Kawamura et al. and Yang et al. teach all of the limitations
`
`of claim 1 from which this claim depends.
`
`Kawamuraet al. teaches wherein (Fig. 4), further comprising:
`
`a plurality of source signal lines (SL, 445) extending in the second direction
`
`(vertical or Y direction) in the pixel region (300) and supplying a data signal to the thin
`
`film transistors (TRs, see Fig. 4) in the plurality of pixels (PA).
`
`Kawamura etal. is explicitly silent of disclosing wherein a gate terminal including
`
`a plurality of gate terminal electrodes connected to the plurality of gate lead-out lines
`
`respectively; and
`
`

`

`Application/Control Number: 16/694,428
`Art Unit: 2819
`
`Page 9
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`a source terminal including a plurality of source terminal electrodes connected to
`
`the plurality of source signallines respectively,
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`wherein the gate terminal and the source terminal are provided in one of a pair of
`
`long sides in the frame region of the thin film transistor substrate.
`
`Yang et al. teaches wherein (Fig. 7) a gate terminal (122, 964) including a
`
`plurality of gate terminal electrodes (see figure below) connectedto the plurality of gate
`
`lead-outlines (128, 968) respectively; and
`
`a source terminal (124, 465) including a plurality of source terminal electrodes
`
`(see figure below) connectedto the plurality of source signal lines respectively,
`
`wherein the gate terminal (122) and the source terminal (124) are provided in
`
`one of a pair of long sides (bottom side) in the frame region (IAL border, 463) of the thin
`
`film transistor substrate (150, 971, see Fig. 9).
`
`

`

`Application/Control Number: 16/694,428
`Art Unit: 2819
`
`Page 10
`
`
`
`BA
`
`Aectrodeag
`
`Source
`terminal
`
`It would have been obvious to a person of ordinary skill in the art before the
`
`effective filing date of the invention to apply the teaching as taught by Yang etal. while
`
`forming the display panel of Kawamuraetal., in order to minimize by locating display
`
`driver circuitry 126 along the lower edge of display 14 in lower edge inactive area IAL
`
`(63), and to conveniently control/supply signals by the display driver circuitry 126 (464-
`
`65).
`
`Regarding claim 16, Kawamura et al. and Yang et al. teach all of the limitations
`
`of claim 1 from which this claim depends.
`
`Kawamuraet al. teaches wherein (Fig. 4) a display panel comprising:
`
`a thin film transistor substrate (230 shownin Fig. 7, 459) according to claim 1.
`
`

`

`Application/Control Number: 16/694,428
`Art Unit: 2819
`
`Page 11
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`a counter substrate (240 CF substrate, 759) opposedto the thin film transistor
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`substrate (230).
`
`Allowable Subject Matter
`
`14.
`
`Claims 3-10 are objected to as being dependent upon a rejected base claim, but
`
`would be allowable if rewritten in independent form including all of the limitations of the
`
`base claim and any intervening claims.
`
`Regarding claim 3, the prior art of record, either singularly or in combination,
`
`does notdisclose or suggest the combination of limitations including “....further
`
`comprising:
`
`a shield electrode formed in the frame region, the common potential being
`
`applied to the shield electrode; and
`
`a plurality of first connection wirings respectively connecting the plurality of
`
`dummy gate lead-out lines and the shield electrode through respective first contact
`
`holes made in the frame region’.
`
`Conclusion
`
`15.=Anyinquiry concerning this communication or earlier communications from the
`
`examiner should be directed to DIDARUL A MAZUMDER whosetelephone number is
`
`(571)272-8823. The examiner can normally be reached on M-F 9-5.
`
`

`

`Application/Control Number: 16/694,428
`Art Unit: 2819
`
`Page 12
`
`Examiner interviews are available via telephone, in-person, and video
`
`conferencing using a USPTO supplied web-based collaboration tool. To schedule an
`
`interview, applicant is encouraged to use the USPTO Automated Interview Request
`
`(AIR) at http:/Awww.uspto.gov/interviewpractice.
`
`16.
`
`‘If attempts to reach the examiner by telephone are unsuccessful, the examiner's
`
`supervisor, Allen Parker can be reached on 303-297-4722. The fax phone number for
`
`the organization where this application or proceeding is assigned is 571-273-8300.
`
`Information regarding the status of an application may be obtained from the
`
`Patent Application Information Retrieval (PAIR) system. Status information for
`
`published applications may be obtained from either Private PAIR or Public PAIR.
`
`Status information for unpublished applications is available through Private PAIR only.
`
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`
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`272-1000.
`
`/DIDARUL A MAZUMDER/
`Primary Examiner, Art Unit 2819
`
`