* NOTICE*
`
`dPO and INPIT ave not responsible for any damages caused by the use of this translation.
`
`1. Thie document has been transiaied by computer. So the translation may not reflect the original precisely.
`2. "* shows a word which cannot he translated.
`
`3. in the drawings, any wards are not translated.
`
`Publication Number
`
`JP20042 144524
`
`Bibliography
`(18) [Publication country] JP
`
`(12) [Rind of official gazette] A
`(11) [Publication number] 2004214452
`(43) (Date of publication of application] 20040722
`
`($4) [Title of the invention] SEMICONDUCTOR MODULE FOR POWER AND METHOD
`FOR CONNECTING TO EXTERNAL ELECTRODE
`
`(51) {international Patent Classification 7ih Edition]
`HOIL 23/48
`HOTL 25/07
`HOTL 25/18
`
`[Fa
`HOIL 23/48
`
`HOIL 25/04
`
`Pp
`
`C
`
`(21) [Application number] 2609000414
`
`(22) [Filing date} 20030106
`
`(71) fAppiicant]
`
`[Name] FUJI ELECTRIC DEVICE TECHNOLOGY CO LTD
`
`(72} [inventor]
`
`iFull name] TAKIZAWA AKITAKE
`
`Abstract
`
`{67} (Overview)
`
`PROBLEM TO BE SOLVED: To reduce the surge vollage generated at the switching
`
`time of a semiconductor element for a power for constituting an inverter, etc. as
`
`compared with a prior art.
`
`SOLUTION: An electrode bar 32 connected fo a first power source polential output
`
`electrode 8, etc, an electrode bar 35 connected to a load electrode (6.g., U phase} 19,
`
`

`

`etc. and an electrode bar 34 connected to a second power saurce potential output
`
`electrode 9, etc. are formed each in a plate state in a semiconductor element module for
`
`the power which has ihe series connection circuit of the semiconductor element UGBT}
`
`for the power and a diode (FWD) connected in an anti-paraliel with the semiconductor
`
`element (GBT). These electrode bars are disposed near at hand via insulators with each
`
`other. Thus, the inductance value in the semiconductor element module for the poweris
`
`set ic substantially zero, and the surge vallage can be remarkably lowered.
`
`c} igim
`
`{Patent Claims]
`
`Claim 1]
`The power semiconductor module is constituted by connecting a plurality of power
`
`semiconductor elaments and diodes connected in anti-parallel to the element m series
`ina plurality of 1 arngs, or connecting them in parallel.
`
`The semiconductor module for electric power forming the first power-supply-patential
`output electrode and load electrode which constitute the internal electrode, and a second
`power-supply-potential auiput electrode in plate-like form, respectively, and approaching
`
`and arranging on bath sides of an insulating material each other.
`
`(Claim 2}
`
`The power semiconductor module is constituted by connecting a plurality of power
`
`semiconductor elements and diodes connected in anti-parallel to the element in series
`
`in a plurality of 1 arms, or connecting them in parailel.
`
`The power semiconductor module is characterized in that a 1 power supply potential
`
`output electrode, a load electrode, and a 2 power supply potential output electrode and
`
`a foad electrode constituting the internal slectrode are formed in a plate shape, and an
`
`insulator is sandwiched between the first power supply potential output electrode and
`
`the load electrode to be closely arranged.
`
`(Claim 3}
`
`The power semiconductor module is constituted by connecting a pluralty of power
`
`semiconductor elements and diodes connected in anti-parallel to the element in series
`
`ina plurality of 1 arms, or connecting them in parallel,
`
`The power semiconductor module is characterized in that a 1 sewer source potential
`
`output electrode as an output electrode and a 2 power source potential output electrode
`
`are respectively formed in a plate shape and arranged substantially in parallel with a
`
`certain space distance.
`
`fCiaim 4]
`
`

`

`The method of connecting an external electrade of a power semiconductor module to an
`
`external electrode according to claim 3, wherein a plate-shaped extemal wiring electrade
`
`bar is inserted belbveen the 1 power source potential output electrode and the 2 power
`
`source potential output alectrade and is alectrically corimected fo the first power source
`
`potential output electrode and the 2 power source potential cutput electrode.
`
`Claim 5]
`
`An external witing electrode bar inserted between the 1 power source potential cutout
`
`élactrode and the 2 power source potential output electrode : The method of connecting
`an external electrode of a power semiconductor module to an extemal electrode of a
`
`power semiconductor module according to claim 4, wherein a screw made of an insulator
`
`ora mamber equivalent thereto is fixed by passing through between the electrodes, or a
`screw of a conductor coated with an insudator or an equivalent member thereof is passed
`
`through between the slectrodes.
`
`Description
`
`[Detailed description of the invention]
`{0004}
`
`fPechnical field of invention}
`
`The present invention relates to a power semiconductor module such as an [GBT
`
`(insulated gate bipolar transistor) and a method of connecting the power semiconductor
`
`module fo an external electrode.
`
`(a0a2}
`
`iPrior art]
`
`FIG. 10 shows 4 main circull diagram of an inverter.
`
`Reference numeral
`
`1 denotes a commercial AC power supply, reference numeral 2
`
`denotes 3 diode rectifier module for converting AC to DC, reference numeral 3 denotes
`
`a capacitor having a large capacity, reference numeral 4 denotes a load such as a motor,
`
`and reference numeral 5 denotes an inverter module comprising a power semiconductor
`
`and converting direct current inte alternating current,
`
`in the inverter module 5, 6 is an
`
`GBT and 7 is a diode connected in antiparallel to the |GBT, and these are composed of
`
`6 circuits (6 arms}.
`
`in general, the inverter module 5 has 1 upper and lower arm 2
`
`elements or 7 sets of 6 alernents, and in the case of an inverter, a module containing 2
`
`elements is connected In parallel, or a module having 6 * is used as itis, and a module
`
`having siements is used as it is. 3.
`
`{0003}
`
`FIG. 11 shows a general appearance of an inverter module with 2 slements. & is a
`
`

`

`positive power source potential output electrode (P output electrode}. 9 is a negative
`
`power source potential output electrode (output electrede}, and 10 is load.
`
`An output electrode (U output electrode) connected to the side, @ 11,12,19,14 and a gate
`
`terminal and an emitter terminal of the upper armside and the lower arm side ISBT are
`SHOW.
`
`[ood]
`FiG. 12 shows a schematic cross-sectional view of a module with 2 elements.
`
`15 is @ copper base substrate, 16 is an insulating ceramic substrate, and 17,1819 is a
`
`copper pattern for wiring and semiconductor chip connection. Reference numeral 20,21
`
`denotes an iGBT chip of an upper and lowerarm (actually, an FWD chip is also mounted,
`but omitted), 22.23 denotes @ semiconductor chip and an electrade for connecting
`
`copper paitern, and 24.25.26 denotes 4 copper electrode bar for carmecting each copper
`pattern and each output electrode P, U.N.
`
`(9005)
`FIG. 13 shows an equivalent circuit of an inductance component in the module of FIG.
`12, An inductanceL 1 28 between an upper arm side collector and 4 positive side power
`
`source potential cutout electrode is an inductance L 2 between an emitter of an upper
`
`arm and a connection point 29 (copper pattern 18 and copper electrode bar 25), and an
`
`inductance L 27 between a connection point 25 and a lower arm collector on the lower
`
`arm side collector. 3 30 Reference numeral 31 denotes an inductance L 4 between the
`
`lower arm side emitter anc the lower side power source potential output electrade.
`
`{0008}
`
`in a circuit of an inverter of FIG. 10, normaily, an IGBT is operated by switching at about
`
`10 kHz. in this case, the surge voltage VCE (peak) applied between the collector and
`
`the emitter of the IGBT chip when the IGBTis turned off is expressed as follows :.
`
`VCE (peak) = Ed (LI+L2+L3+L4) - di/ dt(4}
`
`Ed : Voltage of capacitor 3 (BC voltage).
`
`Current change rate of IGBT at turn-off time
`
`[G07]
`FIG. 14 showa the vollage VCE and the IC waveform of the KOBT at the time of IGBT
`turn-off,
`
`The surge volfage A V from the DC voltage Ed is caused by ihe value of Li fo L 4. and
`
`when the value of Li to L 4 is large from the above equation (1), the peak voltage value
`
`applied to the HSBT chip at the time of turn-off becomes higher. An iGBT chip and a
`
`connected FWD dreewheeling diode) chip require a high voltage tolerance. in general,
`
`

`

`a chip having high voltage endurance has a large chip area, which leads to an increase
`
`in size and cost of a module. Further, when the surge voltage is high, noise which is
`
`supplied to the outside becomes large, which causes a malfunction of an external device.
`
`Therefore, there has bean proposed a technique of reducing inductance by arranging
`
`the 1 2 and 2 wiring patierns connected to the frstand 1 power supply terminalis close
`
`to each other dor example, refer to Patent Document 1).
`
`{o00g}
`
`{Patent document 1]
`
`U.S. Pat, No. 2725952 (page 4-5, FIG. 1}.
`
`{0009}
`
`[Problem to be solved by the invention]
`However, in the above proposed technique, attention is focused only on the portions L 1
`
`and L 4 of FIG. 13, and sincethe portions L 2 and LS remain intact, a surge voliage is
`generated at this portion during switching.
`
`Accordingly, it is an object of the present invention te further reduce the surge voltage
`and to reduce the size and cost of the module.
`
`{0040}
`
`Means for salving the problem]
`
`in order to solve this problem, in the 1 aspect of the present invention, there is provided
`
`a power semiconductor module in which a plurality of power semiconductor elements
`
`and diedes connected in antiparailel to the elarnent are conmected In series as 1 arms,
`
`or a plurality of diodes are connected in parallel].
`
`The 7? power source potential output electrode, the load electrode, and the 2 power
`
`source potential output electrode constituting the internal electrode are provided,
`
`in this case, each of them is formed into a plate shape, and an insulating material is
`
`sandwiched between the plates to be closely arranged.
`
`{0074}
`
`ina 2 aspect of the present invention, there is provided 4 power semiconductor module
`
`in which 2 plurality of power semiconductor elements and diodes connected in
`
`antiparallel to the element are connected in series as 1 arms, or a plurality of such diodes
`
`are cannected in parailel.
`
`A 1 power supply potential output electrode, a load slectrode, and a 2 power supply
`
`potential output electrode and a load electrode constituting the internal electrode are
`
`formed in a plate shape, and an insulator is sandwiched between the first power supply
`
`potential output electrode and the foad electrode to be closely arranged.
`
`

`

`{0012}
`
`in addition,
`
`in the 3 aspect of the present
`
`invention,
`
`there is provided a power
`
`semiconductor module in which a plurality of power semiconductor elements anc diodes
`
`connected in antiparaliel to the element are connected in series as | arms, ora plurality
`
`of such diodes are connected in parallel,
`
`A 7 power supply potential cutout electrode and a 2 power supply potential output
`
`electrode, which are output electrodes, are formed in a plate shape, and arranged
`
`substantially in parallel with a certain space distance.
`(6073
`
`in the 3 aspect of the present invention, it is possible to electrically connect the 7 power
`
`supply potential output electrode and the 2 power supply potential output electrode to
`each other by inserting a plate-like extemal wiring electrode bar which is arranged close
`
`io each other between the 2 power supply potential output electrode ard the 4 power
`supply potential output electrode (invention of Claim 4). An external wiring electrode bar
`
`inserted between the 1 power source potential autpul electrode and the 2 pawer source
`potential cutout electrode ; A screw made of an insulating material or an equivalent
`member may be fixed by passing through between the electrodes, or a screw of a
`
`conductor coated with an insulating material or an equivalent member may be fixed by
`
`passing through between the electrodes (Claim 5).
`
`[0044]
`
`Embodiment of invention]
`
`FIG. 1 is a block diagram showing a 1 embodiment of the present invention. FIG. 4 a is
`
`a top view, and FIG. 4 6 is a perspective view (bird’s eye view).
`
`This is a P electrode bar 32 connected to the collector potential of the P output electrode
`
`8 and the upper arm [GBT, and a Uelectrade bar 33 connected to the emitter potential
`
`of the upper arm IGBT, the collector potential of the lower arm IGBT and the U output
`
`electrode 16. An emitter potential of a lower arm IGBT and an N-electrode bar 34
`
`connected to an output electrode 9 are overlapped and formed into a platelike a laminate
`
`structure and closely {closely} arranged. However, since electrical insulation is required
`
`between the electrode bars, the insulator is sandwiched befween the electrode bars as
`
`shown in FG. 1b. With such a configuration, when the GBT or the FWD is switched at
`
`the everlapping portion of each of the electrode bars 32,3334, the current al the time of
`
`switching the IGGBT or the FWDflows te the opposite side, so thal the inductance value
`
`at that time can be made substantially 0.
`
`(0045)
`
`FIG, 2 is an equivaient circuit diagram of FIG. 7.
`
`

`

`For example, when the IGBT of the upper arm is turned on in FiG. 1 a4, a current flows
`
`from the P output electrode 8 through the P electrode bar 32 te a copper pattern having
`
`the same potential as that of the collector of the upper arm GBT, and flows to the U
`
`ouiput electrode 16 via the U output electrade bar 3S connected to the emitter of the
`
`fGBT. At this tine, current flows in the overlapping portions of the electrodes 3¢ and 33:
`
`and currents of the sare size How in opposite directions. in the time of the turn-off when
`
`it is not Necessary to take an inductance value inte consicteration at all but since the rate
`
`af change of currant is very small reqularly, and the current change rate out af which the
`
`influence of an inductance value comes is large,
`
`By flowing currents of the same
`
`magnitude in oppasite directions, an action of canceling out the magnetic field generated
`
`fram each electrode has occurred, and the inductance value becomes almost G. This is
`
`also true of the case of the lower arm IGET.
`
`in other words, as shawn in FRG. 2,
`
`inductances of L 7 and | 2 (electrodes 32 and 33} and L.3 and L 4 (electrodes 33 and
`34} cancel each other out.
`
`{0046}
`FIG. 3 shows a 2 ambodiment of the present invention. The figure (a) is a plan and the
`(b) is & perspective view(bird).
`
`itis a * figure.
`
`in this embodiment, each electrode is formed into a plate shape ike a laminate structure,
`
`and an electrode bar 35 which connects the emitter potential of the LU ouput efectrode
`
`10 and the upper arm GBT and the collector potential of the lower arm iGBT is
`
`individually superposed on the P electrode bar 36 and the electrode bar 37, respectively,
`
`and is arranged in close contact with each other. As a result, current when the IGBT or
`
`the FYYD switches at the overlapping portion of the electrode bars 35 and 36 and the
`
`electrode bars 35 and 37 flows to the opposite side, so that the inductance value at that
`time becomes almost 0.
`
`FIG. 4 is an equivalent circuit diagram of FIG. 3. L td and L 2 (inductance of overlapping
`
`portions of electrodes 35 and 36) and L 3 and L 4 G@nductance of overlapping portions of
`
`electrodes 35 and 37) cancel each other out.
`
`{0017}
`
`Meanwhile, in ihe conventional semiconductor maduls, since the P-side output electrode
`
`and the N-side oufput electrode are separated from each other, as shown in FIG. 15, the
`
`connection between fhe output electrode portion and the external wiring cannot be made
`
`in a plate-like proximity wiring such as @ laminate wiring See 4 dotted fine partion in FIG.
`
`15). As a result, an inductance is generated in this portion. In FiG, 15, reference numeral
`
`

`

`3 denotes a large-capacity capacitor : 38, a wiring ber having a pasitive potential ; 39, 4
`
`wiring bar having a negative potential
`
`; 40, a semiconductor module including 6
`
`elements ; and 41, a ratiator for cooling.
`
`FIG, 16 shows an. equivalent circuit
`
`including the madule in FG. 15. Although the
`
`inductances La and Lb, Lc, and Ld are substantially made fo zere by plate-like contiguity
`
`wiring-ization in Fig.16, The inductance value Le of the connection part of an cutput
`electrode part and external wiring and Lf (Le<:Lf=10nH degree) wil remain, and as
`
`described by previous (1) formula, surge voltage will occur.
`(G0 78}
`
`FIG. 5 shows another embodiment which addresses such problems. FIG. 5 (a) isa
`
`perspective viewand FIG. 3 () is a cross-sectional view.
`As shown in FiG. & (a), the P-side output electrode 42 and the N-side output electrode
`
`43. of ihe module 40 are formed inie.a plate shape like a laminate structure, and are
`afranged in parallel with a certain space distance apart as shown in the drawing.
`
`in the module 40, as shown in FIG. 5 b, an electrode 42 (P side} and an electrode 43
`(side) are closely wired in a plate shape with an insulator 44 interposed therebetween.
`in addition, an example is shown in which the electrode 43 (N-side) is connected to the
`
`emitter side of the lower arm side IGBT chip 46, and the electrode 42 (P side} is
`
`connected to the copper pattern 48 having the same potential as the collector of the
`
`upper arm side IGRT chip 47.
`
`in FIG. 5, the output portion of the electrode is formed horizontally with respect to the
`
`module, but i may be formed vertically as shown in FIG. 6.
`
`{0049}
`
`FiG. 7 shows an application of FIG. 5. FIG. 7 (a}is a perspective view and FIG. 3 {b} is
`@ cross-sectional view.
`
`As is apparent from FIG. 7 (a) and FIG. 4 (b}, an external electrode wiring bar 38,39 is
`
`inserted into 4 space between the P-side output electrode 42 and the N-side output
`
`electrode 43 of the module 40 in a state in which 2 of them are closely wired in a plate
`
`shape, and the P-side and the N-side are brought into contact with each other to
`
`electrically short-circuit each other.
`
`As aresull, since the inductance value of the coupling portian between the P-side output
`
`electrode portion of the module and the external electrode wiring bar becomes
`
`substantially 0, the surge arnount becomes (Le Lf}: ci/ dt = 0. Thus, the vollage applied
`
`to the KGBT can be reduced to about 100 V in comparison with the conventional method.
`
`(0020)
`
`FIG. 8 shows another application of FIG. &.
`
`

`

`in FIG. 7, itis characterized in that the electrode 42,38 39,43 is electrically short-circuited
`
`only by contact, whereas the electrode shaft is fixed by a screw 49. However, in order to
`
`elecirically insulate the P-side electrace and the N-side electrode, the screw 48 is an
`insulator,
`
`FIG. @ is a sectional view showing an example of utilizing a canductor screw. In other
`
`words, instead of using the screw 49 as an insulator, the conductor screw is coated with
`
`an insulator 50 to provide an electrical insulation.
`
`[0024]
`
`fEffect of the Invention]
`
`According to the present invention, since tis possible to further reduce the surge voltage
`generated when the KGBT and the FWD switch. tt is possible to use an IGBT and an
`
`FWD. with a low voltage rating, and thus i is possible to configure a small and
`inexpensive power semiconductor module. As a result,
`it
`is possible to reduce the
`amount of noise that affecis an external device.
`
`[Brief Description of the Drawings]
`{Fig. 1}The configuration diagram showing the firet embodiment of this invention
`
`[Fig. 2]The representative circuil schematic of Fig1
`
`[Fig. 3]The configuration diagram showing the second embodiment of this invention
`
`{[Fig. 4]The representative circuit schematic of Fig.3
`
`{[Fig. 8iThe configuration diagram showing 2 Srd embodiment of this invention
`
`(Fig. GiThe configuration diagram showing the modification of Fig 4
`
`{Fig. 7iThe configuration diagram showing the first application of Fig.6
`
`[Fig. 8]The configuration diagram showing the second application of Fig.5
`
`{[Fig. 2'The cross sectional view showing the modification of Fig.8
`
`(Fig. 10}General inverter main circuit
`
`[Fig. F7]A common inverter module outline view
`
`[Fig. 12}inverter module section schematic view
`
`[Fig. 13]inside representative circuil schematic of a module
`
`[Fig. 14]The turn-off wave form chart of IGBT
`
`{Fig. 15]The example figure of wiring structure of an inverter module and exterior
`electrodes
`
`{Fig. 16]The representative circuit schematic of Fig. 15
`
`[Explanation of laters or numerats}
`
`+. AC power supply, 2. diode rectifier module, 3. large capacitance capacitor, 4. motor
`
`(load), 5. "| &. IGBT (insulated gate bipolar transistor), 7. diede, 8,42. P output
`
`

`

`electrode, 9,43. output electrode, 10, U output electrade. 11.15. gate terminal, 12,14.
`
`emitter terminal, 15. copper base substrate, 16. ceramic substrate, 17,18,19,48. sopper
`
`pattern, 20,21,46,47. KGBT chip 22,23. connecting electrode. 24, 25, and 26 ~~ a copper
`
`electrode bar, 27,28,20,30,31, -- Inductance, anc 32,33,34,35,36,37 -- electrode bars,
`
`and 38 and 39 -- an exterior-electrodes wiring bar and 40 -- a power semiconductor
`
`module and 47 -- a radiator, and 44 and 45 -- an insulating material and 49 -- a screw
`
`and 30 - aninsulating material.
`
`

`

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`2
`
`O04. 7. 29
`
`
`

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`JP 2004-274452 A
`
`2
`
`O04. 7. 29
`
`nfPecccceeceefine
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`]a
`
`Ae4ostodii
`
`
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`