* NOTICE*
`
`dJPO and INPIT are not responsible for any damages caused by the use of this trangiation.
`
`4. This document has been translated by camputer. So the translatiar: may not reflect the original precisely.
`
`2. *** shows a wordwhich cannot be transiated.
`
`3. in the drawings, any wards are not translated.
`
`Publication Number
`
`JP20042 144524
`
`Bibliography
`(19) [Publication country] JP
`
`(2) [Kind of official gazette] A
`(11) [Publication number] 2004214452
`{43} [Date of publication of application) 20040729
`
`(54) [Title of the invention] SEMICONDUCTOR MODULE FOR POWER AND METHOD
`
`FOR CONNECTING TO EXTERNAL ELECTRODE
`
`(51) finternational Patent Classification 7th Edition]
`HOIL 23/48
`HOTL 25/07
`HOTL 25/18
`
`[Fa
`
`HOWL 23/48
`
`HO1L 25/04
`
`Pp
`
`CG
`
`(21) [Application number] 2003000414
`
`(22) [Filing date] 20030706
`
`(71) [Applicant]
`
`iNamel FUGL ELECTRIC DEVICE TECHNOLOGY COLTD
`
`(72) finventor]
`
`fFull named TAKIZAWA AKITAKE
`
`Abstract
`
`(67) [Overview]
`
`PROBLEM TO BE SOLVED: Te reduce the surge vollage generated at the switching
`
`tine of a semiconductor element for a power for constituting an inverter, etc. as
`
`compared with a prior art.
`
`SOLUTION: An electrode bar 32 connected to a first power source potential output
`
`electrode &, éic., an electrode bar 33 connected to a load elecirode (e.g., U phase} 10,
`
`

`

`ete. and an electrode bar 34 connected to a second power source potential output
`
`electrode 9, etc. are formed each in a plate state in a semiconductor element module for
`
`the power whichhas the series connection circuit of the semiconductor element (IGBT}
`
`for the power and a diode (FWD) connected in an anti-parallel with the semiconductor
`
`element (GBT). These electrode bars are disposed near at hand via insulators with each
`
`other. Thus, the inductance value in the semiconductor element module for the paweris
`
`setio subsianiially zero, and the surge vallage can be remarkably lowered.
`
`Oo laim
`
`[Patent Claims]
`
`iCiaim 4]
`The power semiconductor module is constituted by connecting a plurality of power
`
`semiconductor elements and diodes connected in anti-parallel to the element in series
`
`in. a plurality of 1 arms, or connecting them in paraliel.
`The semiconductor module for electric power forming the first pawer-supply-potential
`
`ouiput electrode and load electrode which constitute the internal electrode, and a second
`power-supply-potential output electrode in plate-like form, respectively, and approaching
`
`and arranging on bath sides of an insulating material each other.
`
`Claim 2]
`
`The power semiconductor module is constituted by connecting a plurality of power
`
`semiconductor elements and diodes conmected in anti-parallel to the element in series
`
`in aplurality of ( arms, or connecting them in parallel.
`
`The power semiconductor module is characterized in that a 1 power supply potential
`
`output electrode, a load electrode, and a 2 power supply potential output electrode and
`
`a foad electrode constituting the internal electrode are formed in a plate shape, and an
`
`insulator is sandwiched between the first power supply potential culput electrode and
`
`the load electrode to be closely arranged.
`
`[Claim 3]
`
`The power semiconductor module is constituted by connecting a plurality of power
`
`semiconductor elements and diodes connected in anti-parallel to the element in series
`
`ina plurality of 1 arms, or connecting them in parallel.
`
`The power semiconductor module is characterized in that 4 1 pawer source potential
`
`output electrode as an output electrode and a 2 power source potential output electrode
`
`are respectively formed in a plate shape and arranged substantially in parallel with a
`
`cerlain space distance.
`
`fClains 4]
`
`

`

`The method of connecting an external electrade of a power semiconductor module to an
`
`external electrode according to clalm 3, wherein a plate-shaped extemal wiring electrode
`
`baris inserted between the 1 power source potential output electrode and the 2 power
`
`source potential output electrode and is alectrically conmacted to the first power source
`
`potential ouiput electrode and the 2 power source potential cuiput electrode.
`
`{Clair 5]
`
`An extemal wiring electrode bar inserted betveen the 1 pawer source potential autput
`
`electrode and the 2 power source potential output electrode ; The method of connecting
`an external electrode of a power semiconductor module to an extemal electrode of a
`
`power semiconductor module according to claim 4, wherein a screw made of an insulator
`
`of a member equivalent thereto is fixed by passing through between the electrodes, or a
`screw of a conductor coated with an insulator ar an equivalent memberthereof is passed
`
`through between the electrodes.
`
`Description
`
`[Detailed description of the invention]
`{0004}
`
`frechnical field of invention]
`
`The present invention relates to a power semiconductor module such as an GST
`
`(insulated gate bipolar transistor) and a method of connecting the power semiconductor
`
`module to an external electrode.
`
`{0002}
`
`iPrior art]
`
`FIG, 10 shows a main circult diagram of an inverter.
`
`Reference numeral 1 denotes a commercial AC power supply, reference numeral 2
`
`denotes a diode rectifier module for converting AC to DC, reference numeral 3 denotes
`
`a capacitor having a large capacity, reference numeral 4 denotes a load such as a motor,
`
`and reference numeral § denotes an inverter module comprising a power semiconductor
`
`and converting direct current inte alternating current. In the inverter module 5, 6 is an
`
`iGHT and 7 is a diode connected in antiparallel to the IGBT, and these are composed of
`
`6 circuits (6 arms).
`
`In general, the inverter module 5 has 1 upper and lower arm 2
`
`elements or 1 sets of 6 elaments, and in the case of an inverter, a module containing 2
`
`elements is connected in parallel, or a module having 6 * is used as itis, and a module
`
`having elements is used as itis. 3.
`
`fO003}
`
`FIG. 11 shows a general appearance of an inverter module with 2 slements. & is a
`
`

`

`positive power source potential output electrode (P output electrode}, 9 is a negative
`
`power source potential output electrade (output electrode), and 10 is load,
`
`An cutpul electrode (U output electrode) commected to the side, a 11,12,13,74 and a gate
`
`terminal and an emitier terminal of the upper arm side and the lower arm side IGBT are
`shown,
`
`jo004]
`FIG. 12 shows a schematic cross-sectional view of a module with 2 elements.
`
`15 is a copper base substrate, 16 is an insulating ceramic substrate, and 17,18. 19 is a
`
`copper pattern for wiring and semiconductor chip cannection. Reference numeral 20,21
`
`denotes an iGRT chip of an upper and lower arm (actually, an FWD chip is aiso mounted,
`but omitted), 22.23. denotes a semiconductor chip and an electrade for connecting
`
`copper pattern, and 24,25,26 denotes 4 copper electrode bar for cormecting each copper
`
`pattern and each output electrode P, U, N.
`{0005}
`
`FIG. 13 shows an equivalent circuit of an inductance component in the module of FIG.
`72. An inductanceL 1 28 between an upper arm side callector and a positive side power
`
`source potential output electrode is an inductance L 2 between an emitter of an upper
`
`arm and a connection point 29 (copperpatiern 18 and copper electrode bar 25), and an
`
`inductance L 27 between a connection point 29 and a lower arm collector on the lower
`
`arm side collector. 3 30 Reference numeral 31 denotes an inductance L 4 between the
`
`lower armside emitter and the lower side power source potential output electrode.
`
`{0006}
`
`in a circuit of an inverter of FIG. 10, normaly, an IGBT is operated by switching at about
`
`10 kHz. in this case, the surge voltage VCE (peak) applied between the collector and
`
`the emitter of the IGBT chip when the [GBTis turned off is expressed as fallows :.
`
`VCE (peak) = Ed (LI+L2+L3+L4) - di/ dt (4)
`
`Ed : Voltage of capacitor 3 (DC voltage}.
`
`Current change rate of IGBY at turn-off time
`
`[0007]
`FIG. 14 shows the vollage VCE and the IC waveform of the }GBT at the time of [GBT
`
`turn-off,
`
`The surge voltage A V from the DC voltage Ed is caused by the value of LI fo L 4, and
`
`when the value of Li to L 4 is large from the above equation (1}, the peak voliage value
`
`applied fo the GBT chip at the time of turn-off becomes higher. An IGBT chip and a
`
`connected FWD (freewheeling diode} chip require a high voltage tolerance. in general,
`
`

`

`a chip having high voltage endurance has a large chip area, which leads to an increase
`
`in size and cast of a module. Further, when the surge voltage is high, noise which is
`
`supplied to the outside becomeslarge, which causes a malfunction of an external device.
`
`Therefore, there has been proposed a technique of reducing Inductance by arranging
`
`the 12 and 2 wiring patierns connected to the firsiand 1 power supply ferminais close
`
`to each other (for example, refer to Patent Dacument 1).
`
`{O00g]
`
`{Patent document 1]
`
`US. Pat. No. 2725952 (page 4-5, FIG. 1}.
`
`{O09}
`
`[Problem to be solved by theinvention]
`However, in the above proposed technique, attention is focused only on the partions L 4
`
`and L 4 of FIG. 13, and since the portions L 2 and L S remain intact, a surge voltage is
`
`generated at this portion during switching.
`Accordingly, it is an object of the present invention to further reduce the surge voltage
`
`and to reduce the size and cost of the module.
`
`{0040}
`
`iMeans for saiving the problem]
`
`in order to solve this problem, in the 1 aspect of the present invention, there is provided
`
`a power semiconductor module in which a plurality of power semiconductor elements
`
`and diodes cannected in antiparallel to the elament are connected in series as 1 arms,
`
`or a plurality of diodes are connected in parallel].
`
`The 1 power source potential output electrode, the load electrode, and the 2 power
`
`source potential output electrode canstituling the internal electrode are provided.
`
`in this case, each of them is formed into a plate shape, and an insulating material is
`
`sandwiched between the plates to be closely arranged.
`
`{0044}
`
`in a 2 aspect of the present invention, there is provided 4 power semiconductor module
`
`in which a plurality of power semiconductor elements and diodes connected in
`
`antiparaliel to ihe element are connected in series as 1 arms, or a plurality of such diodes
`
`are connected in parallel.
`
`A 1 power supply potential oufput electrode, a foad electrode, and a 2 power supply
`potential output electrode and a load electrode constituting the internal electrode are
`
`formed in 4 plate shape, and an insulator is sandwiched between the first power supply
`
`potential output electrode and the load electrode to be closely arranged.
`
`

`

`[0042]
`
`in addition,
`
`in the 3 aspect of the present
`
`invention,
`
`there is provided a@ power
`
`semiconductor module in which a plurafity of power semiconductor elements and diodes
`
`connected in antiparallel to the element are connected in series as 1 arms, or a plurality
`
`of such diodes are connected in parallel.
`
`A 7? power supply potential output electrode and a 2 power supply potential output
`
`electrade, which are oulput electrodes, are formed in a plate shape, and arranged
`
`substantially in paraflel with a certain space distance.
`[0043]
`
`in the 3 aspect of the present invention, itis possible to electrically conneci the 1 power
`
`supply potential output electrode and the 2 power supply potential output electrode to
`each other by inserting a plate-like extemal wiring electrode bar which is arranged close
`
`to each other between ihe 2 power supply potential output electrode and the 4 power
`
`supply potential output electrode (Invention of Claim 4). An external wiring electrode bar
`inserted between the 1 power source potential outoul electrode and the 2 pawer source
`
`potential output electrode . A screw made of an insulating material or an equivalent
`member may befixed by passing through between the electrodes, or a screw of a
`
`conductor coated with an insulating material or an equivalent member may be fixed by
`
`passing through between the electrodes (Claim 5).
`
`{O01}
`
`[Embodiment of invention]
`
`FIG. 1 is a block diagram showing a 7 embodiment of the present invention. FIG, 4 a is
`
`a top view, and FIG. 4 b is a perspective view (bird’s eye view).
`
`This is a P electrade bar 32 connected to the collector potential of the P output electrode
`
`8 and the upper arm IGBT, and a Uelectrade bar 33 connected to the emitter potential
`
`of the upper arm IGBT, the collector potential of the lower arm IGBT and the U output
`
`electrode 10. An eamitier potential of a lower arm [GBT and an N-electrode bar 34
`
`connected fo an output electrode 9 are overlapped and formedinto a plate like a laminate
`
`structure and closely (closely) arranged. However, since electrical insulation is required
`
`between the electrode bars, the insulator is sandwiched between the electrode bars as
`
`shown in FIG. 1b. With such a configuration, when the IGBT or the FWD is switched at
`
`the overlapping portian of each of the electrode bars 32,3334, the current af the time of
`
`switching the IGBT or the FWDflows to the opposite side, so that the inductance value
`
`at that time can be made substantially 0.
`
`{0015}
`
`FIG, 2 is an equivaient circuit diagram of FIG. 4.
`
`

`

`For example, when the IGBT of the upper arm is turned on in FIG. 7 a, a current flows
`
`from the P output electrode 8 through theP electrode bar 32 to a copper patiern having
`
`the same potential as that of the collector of the upper arm IGBT, and Hows to the U
`
`ouiput electrode 10 via the Uoutput electrode bar 33 connected to the emitter of the
`
`iGBT. At this tine, current flows in the overlapping portions of the electrodes 32 and 33,
`
`and currents of the same size How in opposite directions. in the time of the turn-off when
`
`it js not necessary to take an inductance value into consideration at all but since the rate
`
`of change of current is very small regularly, and the current change rate out of which the
`
`influence of an inductance value comes is large. By flowing currents of ihe same
`
`magnitude in oppasite directions, an action of canceling out the magnetic field generated
`
`from each electrode has occurred, and the inductance value becomes almost 0. This is
`
`also. true of the case of the lower arm IGBT.
`
`In other words, as shawn in FIG. 2,
`
`inductances of L t and | 2 (electrades 32 and 33) and L 3 and L 4 (electrodes 33 and
`
`34) cancel each other out.
`fO0%6)
`
`FIG. 3 shows a 2 embodiment of the present invention. The figure (a) is a plan and the
`{b} is @ perspective view (bird).
`
`iis a * figure.
`
`in this embodiment, each electrode is formed into a piste shape fike a laminate structure,
`
`and an electrode bar 35 which connects the emitter potential of the U output electrode
`
`10 and the upper arm IGBT and the collector potential of the lower arm iGBT is
`
`individually superposed on the P electrode bar 36 and the electrode bar 37, respectively,
`
`and is arranged in close contact with each other. As @ result, current when the IGBT or
`
`the FYYD switches at the overlapping portion of the electrode bars 35 and 36 and the
`
`electrode bars 35 and 37 Hows to the opposite side, so that the inductance value at that
`
`time becomes almost 0.
`
`FIG. 4 is an equivalent circuit diagram of FIG. 3. L 1 and L 2 (inductance of overlapping
`
`portions of electrodes 35 and 36) and L 3 and L 4 (inductance of overlapping portions of
`
`electrodes 35 and 37) cancel each other out.
`
`[O047}
`
`Meanwhile, in the conventional semiconductor module, since the P-side output electrode
`
`and the N-side output electrode are separated from each other, as shown in FIG. 75, the
`
`connection between the output electrode portion and ihe external wiring cannot be made
`
`in a plate-like proximity wiring such as a laminate wiring (See a dotted line portion in FIG.
`
`15}. As a result, an inductance is generated in this portion. In FXG. 15, reference numeral
`
`

`

`3 denotes a large-capacity capacitor ; 38, a wiring bar having a positive potential | 39, 4
`
`wiring bar having a negative potential
`
`;: 40, a semiconductor module including 6
`
`elements ; and 41, a radiator for cooling.
`
`FIG, 16 shows. an. equivalent circuit including the madule in FIG. 15. Although the
`
`inductances La and Lb, Lc, and Ld are substantially made fo zere by plate-like contiguity
`
`wiring-ization in Fig.16, The inductance value Le of the connection part of an output
`electrode part and external wiring and Lf (Le<sLI=tOnH degree) will remain. and as
`
`described by previous (1) formula, surgevoltage will occur.
`[0048]
`
`FIG. & shows another embodiment which addresses such problems. FIG. 5 (a) is.a
`
`perspective viewand FIG. 3 (b) is @ cross-sectional view.
`As shown in Fic. 5 (3), the P-side output electrode 42 and the N-side output dlectrade
`
`43 of the module 40 are formed into a plate shape hike @ laminate structure, and are
`
`afranged in parallel with a ceriain space distance apart as shown in the drawing.
`in the module 40, as shown in FIG. 5 b, an electrode 42 (P side) and an electrode 43
`
`{side} are closely wired in a plate shape with an insulator 44 interposed therebetween.
`in addition, an exampleis shown in which the electrode 43 (N-side)} is connected to the
`
`emitter side of the lower arm side IGBT chip 46, and the electrode 42 (P side) is
`
`connected to the copper pattern 48 having the same potential as the collector of the
`
`upper arm side IGBT chip 47.
`
`in FIG. 5, fhe output portion of the electrode is formed horizontally with respect fo the
`
`module, but h may be formed vertically as shown in FIG. 6.
`
`{0049}
`
`FIG, 7 shows an application of FIG. 5. FIG. 7 (a) is a perspective view and FIG. 3 (b} is
`& cross-sectional view.
`
`As is apparent from FIG. 7 (a) and FIG. 4 (9), an external electrode wiring bar 38,39 is
`
`inserted info a space between the P-side output electrode 42 and the N-side output
`
`electrode 43 of the madule 40 in a state in which 2 of them are closely wired in a plate
`
`shape, and the P-side and the N-side are brought into contact with each other to
`
`electrically short-circuit each other.
`
`As a result, since the inductance value of the coupling portion between the P-side output
`
`electrode partion of the module and the external electrode wiring bar becornes
`
`substantially 0, the surge amount becomes (Le LA) - di/ dt= 0. Thus, the vollage applied
`
`to the GBT can be reduced to about 100V in comparison with the conventional method.
`
`{O020)
`
`FIG. 8 shows another application of FIG. 5.
`
`

`

`In FIG. 7, itis characterized in that the electrode 42,38 39.43 is electrically short-circuited
`
`ory by contact, whereas the electrode shaft is fixed by a screw 49. However, in order to
`
`electrically insulate the P-side electrode and the N-side electrode, the screw 49 is an
`
`insulator,
`
`FIG. 2 is a sectional view showing an example of ubhzing a conductor screw. In other
`
`words, instead of using the screw 49 as an insulator, the conductor ecrew is coated with
`
`an insulator 50 ta provide an electrical insulation.
`
`{002 4]
`
`{Effect of the Invention]
`
`According to the present invention, since it is possible to further reduce the surge voltage
`generated when the KSBT and the FWD switch, it is possible to use an GBT and an
`
`FWD with a law voltage rating, and thus it
`
`is possible to configure a small and
`
`inexpensive power semiconductor module. As a resulf,
`
`it
`
`is possible to reduce the
`
`amount of noise that affecis an external device.
`
`[Brief Description of the Drawings]
`{Fig. 1]The configuration diagram showing the first embodiment of this invention
`
`{[Fig. 2]The representative circuil schematic of Fig.4
`
`[Fig. 3]The configuration diagram showing the second embociment of this invention
`
`{[Fig. 4]The representative circuit schematic of Fig.3
`
`[Fig. 8]The configuration diagram showing a 3rd embodiment of this Invention
`
`{[Fig. G]The configuration diagram showing the modification of Fig.4
`
`{Fig. 7]The configuration diagrarn showing the first application of Fig.6
`
`[Fig. 8fThe configuration diagram showing the second application of Fig.5
`
`[Fig. QThe cross sectional view showing the modification of Fig.8
`
`{Fig. 10}General inverter main circuit
`
`[Fig. TT]A common inverter module outline view
`
`[Fig. 12]inverter module section schematic wew
`
`[Fig. 13}inside representative circuit schematic of a madule
`
`[Fig. 14]The turn-off wave form chart of iGBT
`
`{Fig. 15]The example figure of wiring structure of an inverter module and exterior
`
`electrodes
`
`{[Fig. 16]The representative circuit schematic of Fig. 15
`
`fExplanation of letters or numerals]
`
`+. AC power supply, 2. diode rectifier module, 3. large capacitance capacifor, 4. motor
`
`(oad), 5."6 IGET (insulated gate bipolar transistor), 7. diode, 8.42. P ouiput
`
`

`

`electrode, 9,43. output electrode, 10, U output electrade. 11.79. gate terminal, 12,14.
`
`emitter terminal, 15. copper base substrate, 16. ceramic substrate, 17,18,19,48. copper
`
`patiern, 20,21,46,47. KOBT chip 22,23. connecting electrode. 24, 25, and 26 -- a copper
`
`electrode bar, 27,26,29.30,31, -- Inductance, and 32,33,54,35,38,37 — electrode bars,
`
`and 38 and 39 ~- ar exteriorelectrades wiring bar and 40 -- a power semiconductor
`
`module and 41 -- a radiator, and 44 and 45 -- an insulating material and 49 ~ a screw
`
`and 80 -- aninsulating material,
`
`

`

`JP 2004-274452 A 2004. 7.29
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