www.uspto.gov
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and TrademarkOffice
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`
`17/190,261
`
`03/02/2021
`
`Hidekazu NAKAMURA
`
`070469-1056
`
`4036
`
`Rimon PC - MWE
`423 WashingtonStreet
`Suite 600
`San Francisco, CA 94111
`
`SABUR,ALIA
`
`2812
`
`PAPER NUMBER
`
`NOTIFICATION DATE
`
`DELIVERY MODE
`
`10/26/2023
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`Thetime period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
`following e-mail address(es):
`USPTOmail@rimonlaw.com
`
`PTOL-90A (Rev. 04/07)
`
`

`

`Office Action Summary
`
`Application No.
`17/190,261
`Examiner
`ALIA SABUR
`
`Applicant(s)
`NAKAMURAetal.
`Art Unit
`AIA (FITF) Status
`2812
`Yes
`
`-- The MAILING DATEof this communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLYIS SET TO EXPIRE 3 MONTHS FROM THE MAILING
`DATE OF THIS COMMUNICATION.
`Extensions of time may be available underthe provisions of 37 CFR 1.136(a). In no event, however, may a reply betimely filed after SIX (6) MONTHSfrom the mailing
`date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHSfrom the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, evenif timely filed, may reduce any earned patent term
`adjustment. See 37 CFR 1.704(b).
`
`Status
`
`
`
`1) Responsive to communication(s) filed on 10/13/23.
`C} A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/werefiled on
`2a)[¥) This action is FINAL.
`2b) (J This action is non-final.
`3)02 An election was madeby the applicant in responseto a restriction requirement set forth during the interview
`on
`; the restriction requirement and election have been incorporated into this action.
`4)\0) Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Exparte Quayle, 1935 C.D. 11, 453 O.G. 213.
`
`Disposition of Claims*
`1-26 is/are pending in the application.
`)
`Claim(s)
`5a) Of the above claim(s) ___ is/are withdrawn from consideration.
`C) Claim(s)__ is/are allowed.
`Claim(s) 1-26 is/are rejected.
`1) Claim(s)__is/are objectedto.
`Cj} Claim(s)
`are subjectto restriction and/or election requirement
`* If any claims have been determined allowable, you maybeeligible to benefit from the Patent Prosecution Highway program at a
`participating intellectual property office for the corresponding application. For more information, please see
`http://Awww.uspto.gov/patents/init_events/pph/index.jsp or send an inquiry to PPHfeedback@uspto.gov.
`
`) ) ) )
`
`Application Papers
`10) The specification is objected to by the Examiner.
`11)0) The drawing(s) filedon__ is/are: a)(J accepted or b)( objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`12)1) Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
`Certified copies:
`c)Z None ofthe:
`b)() Some**
`a)C All
`1... Certified copies of the priority documents have been received.
`2.1) Certified copies of the priority documents have beenreceived in Application No.
`3.1.) Copies of the certified copies of the priority documents have been receivedin this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`* See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`1) ([] Notice of References Cited (PTO-892)
`
`2) (J Information Disclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`Paper No(s)/Mail Date
`U.S. Patent and Trademark Office
`
`3)
`
`(LJ Interview Summary (PTO-413)
`Paper No(s)/Mail Date
`4) (J Other:
`
`PTOL-326 (Rev. 11-13)
`
`Office Action Summary
`
`Part of Paper No./Mail Date 20231020
`
`

`

`Application/Control Number: 17/190,261
`Art Unit: 2812
`
`Page 2
`
`DETAILED ACTION
`
`Claim Rejections - 35 USC § 103
`
`Inthe event the determination of the status of the application as subject to AIA35 U.S.C. 102
`
`and 103 (or as subject to pre-AlA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory
`
`basis for the rejection will not be considered a new ground ofrejection if the prior art relied upon, and
`
`the rationale supporting the rejection, would be the same under either status.
`
`The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections
`
`set forth in this Office action:
`
`A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is
`not identically disclosed as set forthin section 102 ofthis title, ifthe differences between the claimed
`invention and the prior art are such that the claimed invention as a whole would have been obvious
`before the effective filing date of the claimed invention to a person having ordinary skill inthe art to
`which the claimed invention pertains. Patentability shall not be negated by the mannerin which the
`invention was made.
`
`The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966),
`
`that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are
`
`summarizedas follows:
`
`1. Determining the scope and contents of the prior art.
`2. Ascertaining the differences between the prior art and the claims at issue.
`3. Resolving the level of ordinary skill in the pertinent art.
`4. Considering objective evidence present in the application indicating obviousness or
`nonobviousness.
`
`This application currently names joint inventors. In considering patentability of the claims the
`
`examiner presumesthat the subject matter of the various claims was commonly ownedas of the
`
`effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised
`
`of the obligation under 37 CFR 1.56 to point out the inventor and effectivefiling dates of each claim that
`
`was not commonly ownedas of the effective filing date of the later invention in order for the examiner
`
`

`

`Application/Control Number: 17/190,261
`Art Unit: 2812
`
`Page 3
`
`to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art
`
`against the later invention.
`
`Claims 1, 4, 7-10, 13-15, 17-22, and 24-26 are rejected under 35 U.S.C. 103 as being
`
`unpatentable over Ikeda (U.S. PGPub 2014/0183547)in view of Wilson (JP $62259462A), Israel (U.S.
`
`PGPub 2016/0005680), and Sutardja (U.S. Pat. 7528013).
`
`Regarding claim1, Ikeda teaches a semiconductor device (Fig. 1A, [0011]) comprising a nitride
`
`semiconductor chip including a silicon substrate having a first thermal expansion coefficient and an
`
`In(x)Ga(y)Al(1-x-y)N layer in contact with a surface of the substrate (Fig. 1B, 23, 25, 27, [0020]; Fig. 4A,
`
`[0050], [0029], [0048]), the nitride semiconductorchip including a heterojunction interface including a
`
`two-dimensional electron gas layer (Fig. 1B, [0020], GaN layer 25 and AlGaN layer 27 form a
`
`heterojunction with a 2DEG); a plurality of pads including a gate pad, a source pad, and a drain pad, the
`
`plurality of pads being provided on a top side of the nitride semiconductorchip (Fig. 1A, 21a-c, [0014)]), a
`
`die pad having a second thermal expansion coefficient (13, [0013]); a plurality of terminals including a
`
`gate terminal, a plurality of source terminals, and a plurality of drain terminals (15d, 15a-c, 15e-h,
`
`[0015]); a first electrode which is electrically connected to the plurality of source terminals and the die
`
`pad (Fig. 3A, 53a, [0032]); the semiconductordevice is a rectangular package having a first side and a
`
`second side that are two opposed sides, the gate terminal and the plurality of source terminals are
`
`disposed along the first side of the semiconductor device, the plurality of drain terminals are disposed
`
`along the second side of the semiconductor device, the plurality of drain terminals are separated from
`
`the die pad, the plurality of source terminals are each connected to the source pad with a plurality of
`
`first bonding wires, and an end of eachof the plurality of first bonding wires is provided at a position
`
`overlapping the plurality of source terminals in the plan view, and the plurality of drain terminals are
`
`each connected tothe drain pad witha plurality of second bonding wires, andan end of each of the
`
`

`

`Application/Control Number: 17/190,261
`Art Unit: 2812
`
`Page 4
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`second plurality of bonding wiresis provided at a position overlapping the plurality of drain terminals in
`
`the plan view (Fig. 1A, Fig. 3A).
`
`Ikeda does not explicitly teach wherein each source terminal amongthe plurality of source
`
`terminals is connected to the source pad by a plurality of first bonding wires including gold and each
`
`drain terminal amongthe plurality of drain terminals is connected to the drain pad by a plurality of
`
`second bonding wires including gold, and each drain terminal among the plurality of drain terminals is
`
`connected to the drain pad by four of the plurality of second bonding wires.
`
`Sutardja teaches connecting source and drain pads to respective terminals where each terminal
`
`is connected by a plurality of bonding wires(Fig. 8, Fig. 7, col. 6, |. 33-37), wherein the bonding wires
`
`may be gold (col. 1,
`
`|. 52-56; col. 3, |. 22-24; col. 5, |. 4-6) and where the plurality of bonding wiresis
`
`defined as at least two(col. 2, |. 1-4) and may be at least four (col. 4, |. 4-9).
`
`Therefore it would have been obvious to a person having ordinaryskill in the art at the time of
`
`the effectivefiling date to combine the teachings of Sutardja with Ikeda such that each source terminal
`
`amongthe plurality of source terminals is connected to the source pad by a plurality of first bonding
`
`wires including gold and each drain terminal among the plurality of drain terminals is connected to the
`
`drain pad by a plurality of second bonding wires including gold, and eachdrain terminal among the
`
`plurality of drain terminals is connected to the drain pad by four of the plurality of second bonding wires
`
`(Fig. 8, Fig. 7, col. 6, |. 33-37).
`
`Ikeda does not explicitly teach wherein the nitride semiconductor chip has a thickness of at least
`
`0.250 mm and at most 0.350 mm; the die pad includes Cu, and the second thermal expansion coefficient
`
`of the die pad including Cuis greater than the first thermal expansion coefficient of the silicon substrate;
`
`an adhesive that joins a backside of the nitride semiconductor chip and the die pad; and whereina
`
`distance from the second side to a center of the die pad in a plan view of the semiconductordeviceis
`
`longer than a distance from thefirst side to the center of the die pad.
`
`

`

`Application/Control Number: 17/190,261
`Art Unit: 2812
`
`Page5S
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`Israel teaches a semiconductor device ([0005]) with a silicon-based semiconductor device chip
`
`({0003], 320, [0035]), a die pad (310, [(0035]); an adhesive that joins a backside of the semiconductor
`
`chip and the die pad (330, [0035]); wherein a thickness of the semiconductorchip falls within a range of
`
`Small to Large which comprises thicknesses of 0.2 mm and 0.4mm (Table 1). In the case where the
`
`claimed ranges overlap orlie inside ranges disclosed by the prior art a prima facie case of obviousness
`
`exists. See MPEP 2144.05.
`
`Wilson teaches a semiconductordevice (Fig. 6) comprising a semiconductorchip ([0019, 42]) on
`
`a die pad including Cu ([0016]), and wherein the semiconductor chip comprises a first side and opposite
`
`second side which are wire bonded to a plurality of terminals (Fig. 4, 50, 53, 55, [0019]), wherein a
`
`distance from the second side to a center of the die pad in a plan view of the semiconductor deviceis
`
`longer than a distance from thefirst side to the center of the die pad (Fig. 2, C/D, [0015]).
`
`Therefore it would have been obvious to a person having ordinary skill in the art to combine the
`
`teachings of Wilson and Israel with Ikeda and Sutardja such that the nitride semiconductor chip has a
`
`thickness of at least 0.250 mm and at most 0.350 mm;the die pad includes Cu, and the second thermal
`
`expansion coefficient of the die pad including Cuis greater than thefirst thermal expansion coefficient
`
`of the silicon substrate; an adhesive that joins a backside of the nitride semiconductor chip and the die
`
`pad; and wherein a distance from the second side to a center of the die pad ina plan view of the
`
`semiconductor device is longer than a distance from thefirst side to the center of the die pad for the
`
`purpose of controlling the bonding wire length and improving efficiency (Wilson, [0019]), and mounting
`
`a semiconductor chip of an appropriate thickness on a die pad of an appropriate material because the
`
`prior art teaches every element, a person of ordinary skill could have combined them as claimed and in
`
`combination each element performs the same function, and the combination would have yielded
`
`predictable results toone of ordinary skill in the art the time of the invention. See MPEP 2143 (I)A.
`
`

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`Application/Control Number: 17/190,261
`Art Unit: 2812
`
`Page 6
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`The combination of Ikeda, Wilson, Israel, and Sutardja as cited above teaches wherein the chip
`
`comprises a silicon substrate and Cudie pad. The silicon substrate has a first thermal expansion
`
`coefficient and the die pad including Cu has a second thermal expansion coefficient which areintrinsic
`
`properties of the materialand are known to be such that the second thermal expansion coefficientis
`
`greater thanthefirst thermal expansion coefficient (See Spec at p. 9, |. 7-13).
`
`Regarding claim 4, the combination of Ikeda, Wilson, Israel, and Sutardja teaches wherein the
`
`first electrode includes a materialsameas a material of the die pad (Ikeda, [0031], Fig. 3A). It would
`
`have been obvious to a person having ordinaryskill in the art to further combine the teachingsof Ikeda,
`
`Wilson, Israel, and Sutardja for the reasons set forthin the rejection of claim 1.
`
`Regarding claim 7, the combination of Ikeda, Wilson, Israel, and Sutardja teaches wherein the
`
`gate terminalis separated fromthe die pad (Ikeda, [0013], [0032]). It would have been obvious toa
`
`person having ordinaryskill in the art to further combine the teachings of Ikeda, Wilson, Israel, and
`
`Sutardja for the reasons set forth in the rejection of claim 1.
`
`Regarding claim 8, the combination of Ikeda, Wilson, Israel, and Sutardja teaches wherein the
`
`plurality of source terminals and the plurality of drain terminals are disposed respectively at two
`
`opposed sides of the rectangular package(Ikeda, Figs. 1A, 3A). It would have been obvious toa person
`
`having ordinaryskill in the art to further combine the teachings of Ikeda, Wilson, Israel, and Sutardja for
`
`the reasons set forthin the rejection of claim 1.
`
`Regarding claim 9, the combination of Ikeda, Wilson, Israel, and Sutardja teaches wherein the
`
`first side of the semiconductor device and the second side of the semiconductor device have asame
`
`number of terminals (Ikeda, Figs. 1A, 3A). It would have been obvious to a person having ordinaryskill in
`
`the art to further combine the teachings of Ikeda, Wilson, Israel, and Sutardja for the reasons set forthin
`
`the rejection of claim 1.
`
`

`

`Application/Control Number: 17/190,261
`Art Unit: 2812
`
`Page 7
`
`Regarding claim 10, the combination of Ikeda, Wilson, Israel, and Sutardja teaches wherein four
`
`drain terminals each of which is a drain terminal of the plurality of drain terminals and disposed along
`
`the second side of the semiconductor device (Ikeda, Figs. 1A, 3A). It would have been obvious toa
`
`person having ordinaryskill in the art to further combine the teachings of Ikeda, Wilson, Israel, and
`
`Sutardja for the reasons set forth in the rejection of claim 1.
`
`Regarding claim 13, the combination of Ikeda, Wilson, Israel, and Sutardja teaches wherein the
`
`nitride semiconductor chip has a first side and a secondside t hat are two opposedsides, thefirst side of
`
`the nitride semiconductorchip is parallel with the first side of the semiconductor device, the second side
`
`of the nitride semiconductor chip is parallel with the second side of the semiconductor device, and the
`
`plurality of pads are disposed at the first side and the secondside of the nitride semiconductor chip
`
`(Ikeda, Figs. 1A, 3A). It would have been obvious to a person having ordinaryskill in the art to further
`
`combine the teachings of Ikeda, Wilson, Israel, and Sutardja for the reasons set forth in the rejection of
`
`claim 1.
`
`Regarding claim 14, the combination of Ikeda, Wilson, Israel, and Sutardja teaches wherein the
`
`source pad is disposed along thefirst side of the nitride semiconductor chip and the drain pad is
`
`disposed along the secondside of the nitride semiconductorchip (Ikeda, Figs. 1A, 3A). It would have
`
`been obvious to a person having ordinaryskill in the art to further combine the teachingsof Ikeda,
`
`Wilson, Israel, and Sutardja for the reasons set forthin the rejection of claim 1.
`
`Regarding claim 15, the combination of Ikeda, Wilson, Israel, and Sutardja does not explicitly
`
`teach wherein the plurality of the source terminals are each connected with asame number of the
`
`plurality of first bonding wires. Sutardja teaches wherein the number is “at least two”(col. 2, |. 1-3) and
`
`wherein a tradeoff exists between increased bonding area required for increased number of wires(col.
`
`2, |. 5-15). Where the general conditions of a claimare disclosedin the priorart, it is not inventive to
`
`discover the optimum or workable ranges by routine experimentation. See MPEP 2144. 05(II)A. It would
`
`

`

`Application/Control Number: 17/190,261
`Art Unit: 2812
`
`Page 8
`
`there have been obvious to a person having ordinaryskill in the art to further combine the teachings of
`
`Ikeda, Wilson, Israel, and Sutardja such that the plurality of the source terminals are each connected
`
`with a same number ofthe plurality of first bonding wires.
`
`Regarding claim 17, the combination of Ikeda, Wilson, Israel, and Sutardja teaches wherein out
`
`of twoopposed main surfaces of the die pad, a main surface not joined to the nitride semiconductor
`
`chip is exposed from the semiconductor device (Israel, Fig. 2F, [0005]). It would have been obvious toa
`
`person having ordinaryskill in the art to further combine the teachingsof Ikeda, Wilson, Israel, and
`
`Sutardja for the purpose of providing an exposed heat sink for thermal coupling (Israel, [0005)).
`
`Regarding claim 18, the combination of Ikeda, Wilson, Israel, and Sutardja teaches wherein the
`
`plurality of terminals are substantially flush with a lateral surface of the rectangular package(Israel, Fig.
`
`2F, 240, [0029]). It would have been obvious to a person having ordinary skill in the art to further
`
`combine the teachings of Ikeda, Wilson, Israel, and Sutardja for the purpose of providing exposed area
`
`for contacts (Israel, [0029)]).
`
`Regarding claim 19, the combination of Ikeda, Wilson, Israel, and Sutardja teaches wherein ina
`
`plan view of the semiconductordevice, the plurality of terminals are mutually equal in size (Ikeda, Figs.
`
`1A, 3A; Israel, Fig. 3B). It would have been obvious to a person having ordinaryskill in the art to further
`
`combine the teachingsof Ikeda, Wilson, Israel, and Sutardja for the reasons set forth in the rejection of
`
`claim 1.
`
`Regarding claim 20, the combination of Ikeda, Wilson, Israel, and Sutardja teaches wherein the
`
`plurality of terminals provided on thefirst side of the semiconductor device and the plurality of
`
`terminals provided on the second side of the semiconductor device are provided to be line-symmetrical
`
`to each other (Ikeda, Figs. 1A, 3A; Israel, Fig. 3B). It would have been obvious to a person having
`
`ordinary skill in the art to further combine the teachings of Ikeda, Wilson, Israel, and Sutardja for the
`
`reasonsset forth in the rejection of claim 1.
`
`

`

`Application/Control Number: 17/190,261
`Art Unit: 2812
`
`Page 9
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`Regarding claim 21, the combination of Ikeda, Wilson, Israel, and Sutardja teaches wherein a
`
`distance between adjacent ones of the plurality of terminals provided on thefirst side of the
`
`semiconductor device and a distance between adjacentonesof the plurality of terminals provided on
`
`the second side of the semiconductor device are equal (Ikeda, Figs. 1A, 3A; Israel, Fig. 3B). It would have
`
`been obvious to a person having ordinaryskill in the art to further combine the teachingsof Ikeda,
`
`Wilson, Israel, and Sutardja for the reasons set forthin the rejection of claim 1.
`
`Regarding claim 22, the combination of Ikeda, Wilson, Israel, and Sutardja teaches wherein no
`
`bonding wire is connected to the die pad (Ikeda, Figs. 1A, 3A). It would have been obvious toa person
`
`having ordinaryskill in the art to further combine the teachings of Ikeda, Wilson, Israel, and Sutardja for
`
`the reasons set forthin the rejection of claim 1.
`
`Regarding claim 24, the combination of Ikeda, Wilson, Israel, and Sutardja teaches wherein the
`
`nitride semiconductor chip is joined at a center portion of the die pad (Ikeda, Figs. 1A, 3A; Wilson, Fig. 4,
`
`[0019]). It would have been obvious to a person having ordinary skill in the art to further combine the
`
`teachings of Ikeda, Wilson, Israel, and Sutardja for the reasonsset forthin the rejection of claim 1.
`
`Regarding claim 25, the combination of Ikeda, Wilson, Israel, and Sutardja teaches wherein a
`
`thickness tm (mm) of the die pad and a lengthL (mm) of the nitride semiconductorchip satisfies a
`
`relationship of tm22.00x10-3xL2+b (b>0) (Israel, Table 1; Medium Dimensions has L=4, 2.00x10-3xL2 =
`
`0.032, Height of Heatsink HHS = 0.5 mm; Large Dimensions has L=8, 2.00x10-3xL2 = 0.128; Height of
`
`Heatsink HHS= 1.2 mm). It would have been obvious to a person having ordinary skill in the art to
`
`further combine the teachingsof Ikeda, Wilson, Israel, and Sutardja for the reasons set forthin the
`
`rejection of claim 1.
`
`Regarding claim 26, the combination of Ikeda, Wilson, Israel, and Sutardja teaches wherein a
`
`base area anda side areaofthe plurality of terminals are equal (Ikeda, Figs. 1A, 3A; Israel, Fig. 3B). It
`
`

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`Application/Control Number: 17/190,261
`Art Unit: 2812
`
`Page 10
`
`would have been obvious to a person having ordinary skill in the art to further combine the teachings of
`
`Ikeda, Wilson, Israel, and Sutardja for the reasonsset forthin the rejection of claim 1.
`
`Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Ikeda(U.S. PGPub
`
`2014/0183547) in view of Wilson (JP $62259462 A) and Israel(U.S. PGPub 2016/0005680), and further
`
`in view of Harnden (U.S. PGPub 2003/0062601).
`
`Regarding claim 2, the combination of Ikeda, Wilson, Israel, and Sutardja does not explicitly
`
`teacha second electrode which mutually and electrically connects the plurality of drain terminals.
`
`Harnden teaches an electrode which mutually and electrically connects a plurality of drain
`
`terminals ([0217]).
`
`Therefore it would have been obvious to a person having ordinaryskill in the art at the time of
`
`the effective filing date to combine the teachings of Harnden with Ikeda, Wilson, Israel, and Sutardja
`
`such that the device includes a second electrode which mutually and electrically connects the plurality
`
`of drain terminals for the purpose of forming a low-resistance contact and allowing more uniform
`
`placement of bond wires ([0217], Fig. 8B).
`
`Regarding claim 3, the combination of Ikeda, Wilson, Israel, and Harnden teaches wherein the
`
`second electrode includes a materialsameas a material of the die pad (Ikeda, Fig. 3A; Harnden, [0217],
`
`Fig. 8B). lt would have been obvious to a person having ordinaryskill in the art to further combine the
`
`teachings of Ikeda, Wilson, Israel, and Sutardja for the reasons set forthin the rejection of claim 2.
`
`Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Ikeda(U.S. PGPub
`
`2014/0183547)in view of Wilson (JP S62259462A), Israel (U.S. PGPub 2016/0005680), Sutardja (U.S.
`
`Pat. 7528013), and furtherin view of Chia (U.S. PGPub 2007/0130759).
`
`Regarding claim 5, the combination of Ikeda, Wilson, Israel, and Sutardja does not explicitly
`
`teacha third electrode electrically connected to the gate terminal.
`
`

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`Application/Control Number: 17/190,261
`Art Unit: 2812
`
`Page 11
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`Chia teaches wherein a leadframe terminal comprises an electrode electrically connected to the
`
`gate terminal ([0023], [0026], [0056], [0072]; second lead frame layer).
`
`Therefore it would have been obvious to a person having ordinaryskill in the art at the time of
`
`the effectivefiling date to combine the teachings of Chia with Ikeda, Wilson, Israel, and Sutardja such
`
`that a third electrode is electrically connected to the gate terminal for the purpose of defining raised
`
`features to increase adhesion and package strength ([0020], [0023)).
`
`Regarding claim6, the combination of Ikeda, Wilson, Israel, and Chia teaches wherein thethird
`
`electrode includes a materialsameas a material of the die pad (Chia, [0057]-[0058]). It would have been
`
`obvious to a person having ordinaryskill in the art to further combine the teachingsof Ikeda, Wilson,
`
`Israel, and Chia for the reasons set forth in the rejection of claim 1.
`
`Claims 11-12, 16, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Ikeda
`
`(U.S. PGPub 2014/0183547)in view of Wilson (JP S62259462A), Israel(U.S. PGPub 2016/0005680),
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`Sutardja (U.S. Pat. 7528013), and further in view of Otremba (U.S. PGPub 2014/0097528).
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`Regarding claim 11, the combination of Ikeda, Wilson, Israel, and Sutardja does not explicitly
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`teacha source sensor terminal disposed alongthe first side of the semiconductor device.
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`Otremba teaches a source sensor terminal disposed adjacent to source terminals of a
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`semiconductor package(Fig. 3A, 212, [0024], [0039]).
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`Therefore it would have been obvious to a person having ordinaryskill in the art at the time of
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`the effective filing date to combine the teachings of Otremba with Ikeda, Wilson, Israel, and Sutardja
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`such that a source sensor terminal is disposed along thefirst side of the semiconductor device for the
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`purpose of providing a sensing terminal ([0049]).
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`Regarding claim 12, the combination of Ikeda, Wilson, Israel, and Otremba teaches wherein the
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`source sensor terminal is separated from the die pad (Otremba, Figs. 3-4). It would have been obvious to
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`

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`Application/Control Number: 17/190,261
`Art Unit: 2812
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`Page 12
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`a person having ordinary skill in the art to further combine the teachings of Ikeda, Wilson,Israel,
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`Sutardja, and Otrembafor the reasonsset forthin the rejection of claim 11.
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`Regarding claim 23, the combination of Ikeda, Wilson, Israel, Sutardja, and Otremba teaches
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`wherein t wherein all bonding wires connected to the source pad are connected to the source terminal
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`or the source sensor terminal (Otremba, Figs. 3C-4, Ikeda Figs. 1A, 3A). It would have been obvious toa
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`person having ordinaryskill in the art to further combine the teachings of Ikeda, Wilson, Israel, Sutardja,
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`and Otremba for the reasons set forthin the rejection of claim 11.
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`Regarding claim 16, the combination of Ikeda, Wilson, Israel, Sutardja, and Otremba teaches
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`wherein the source sensor terminal and the source pad are connected with a plurality of bonding wires
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`(Ikeda, Fig. 8). It would have been obvious to a person having ordinaryskill in the art to further combine
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`the teachings of Ikeda, Wilson, Israel, Sutardja, and Otremba for the reasons setforth in the rejection of
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`claim 11.
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`Conclusion
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`All claims are either identical to or patentably indistinct from claims in the application prior to
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`the entry of the submission under 37 CFR 1.114 (that is, restriction would not be proper) and all claims
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`could have been finally rejected on the grounds and art of record in the next Office action if they had
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`been entered in the application prior to entry under 37 CFR 1.114. Accordingly, THIS ACTION IS MADE
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`FINAL even though it is a first action after the filing of a request for continued examination and the
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`submission under 37 CFR 1.114. See MPEP § 706.07(b). Applicant is reminded of the extension of time
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`policy as set forth in 37 CFR 1.136(a).
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`A shortened statutory period for reply to this final action is set to expire THREE MONTHS from
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`the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date
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`of this final action and the advisory action is not mailed until after the end of the THREE-MONTH
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`shortened statutory period, then the shortened statutory period will expire on the date the advisory
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`

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`Application/Control Number: 17/190,261
`Art Unit: 2812
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`Page 13
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`action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing
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`date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX
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`MONTHSfrom the mailing date of this final action.
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`Anyinquiry concerning this communication or earlier communications from the examiner
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`should be directed to ALIA SABUR whose telephone number is (571)270-7219. The examiner can
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`Charles Garber can be reached on 571-272-2194. The fax phone number for the organization wherethis
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`application or proceeding is assigned is 571-273-8300.
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`file and manage patent submissionsin Patent Center,visit: https://patentcenter.us pto.gov.Visit
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`/ALIA SABUR/
`Primary Examiner, Art Unit 2812
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`