www.uspto.gov
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`
`17/190,261
`
`03/02/2021
`
`Hidekazu NAKAMURA
`
`070469-1056
`
`4036
`
`Rimon PC - Panasonic Corporation
`8300 Greensboro Dr.
`Suite 500
`McLean, VA 22102
`
`SABUR, ALIA
`
`2812
`
`PAPER NUMBER
`
`NOTIFICATION DATE
`
`DELIVERY MODE
`
`03/14/2024
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
`following e-mail address(es):
`USPTOmail@rimonlaw.com
`
`PTOL-90A (Rev. 04/07)
`
`

`

`
`
`Disposition of Claims*
`1-11,13-15 and 17-27 is/are pending in the application.
`)
`Claim(s)
`5a) Of the above claim(s) _ is/are withdrawn from consideration.
`C} Claim(s)__ is/are allowed.
`Claim(s) 1-11,13-15 and 17-27 is/are rejected.
`(] Claim(s)__ is/are objectedto.
`C] Claim(s
`are subjectto restriction and/or election requirement
`)
`* If any claims have been determined allowable, you maybeeligible to benefit from the Patent Prosecution Highway program at a
`participating intellectual property office for the corresponding application. For more information, please see
`http://www.uspto.gov/patents/init_events/pph/index.jsp or send an inquiry to PPHfeedback@uspto.gov.
`
`) ) ) )
`
`Application Papers
`10) The specification is objected to by the Examiner.
`11)0) The drawing(s) filedon__ is/are: a)(J accepted or b)( objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121(d).
`
`Priority under 35 U.S.C. § 119
`12)7) Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d)or (f).
`Certified copies:
`c)Z None ofthe:
`b)() Some**
`a)C All
`1.1.) Certified copies of the priority documents have been received.
`2.2) Certified copies of the priority documents have been received in Application No.
`3.1.) Copies of the certified copies of the priority documents have been receivedin this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`*“ See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`1)
`
`Notice of References Cited (PTO-892)
`
`2) (J Information Disclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`Paper No(s)/Mail Date
`U.S. Patent and Trademark Office
`
`3)
`
`4)
`
`(LJ Interview Summary (PTO-413)
`Paper No(s)/Mail Date
`(Qj Other:
`
`PTOL-326 (Rev. 11-13)
`
`Office Action Summary
`
`Part of Paper No./Mail Date 20240308
`
`Application No.
`Applicant(s)
`17/190,261
`NAKAMURAet al.
`
`Office Action Summary Art Unit|AIA (FITF)StatusExaminer
`ALIA SABUR
`2812
`Yes
`
`
`
`-- The MAILING DATEof this communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`A SHORTENED STATUTORYPERIOD FOR REPLYIS SET TO EXPIRE 3 MONTHS FROM THE MAILING
`DATE OF THIS COMMUNICATION.
`Extensionsof time may be available underthe provisions of 37 CFR 1.136(a). In no event, however, may a reply betimely filed after SIX (6) MONTHSfrom the mailing
`date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHSfrom the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, evenif timely filed, may reduce any earned patent term
`adjustment. See 37 CFR 1.704(b).
`
`Status
`
`1) Responsive to communication(s) filed on 2/22/24.
`C} A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/werefiled on
`
`2a)() This action is FINAL. 2b)¥)This action is non-final.
`3) An election was madeby the applicant in responseto a restriction requirement set forth during the interview
`on
`; the restriction requirement and election have been incorporated into this action.
`4)(2) Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Exparte Quayle, 1935 C.D. 11, 453 O.G. 213.
`
`

`

`Application/Control Number: 17/190,261
`Art Unit: 2812
`
`Page 2
`
`DETAILED ACTION
`
`Claim Rejections - 35 USC § 103
`
`Inthe event the determination of the status of the application as subject to AIA 35 U.S.C. 102
`
`and 103 (or as subject to pre-AlA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory
`
`basis for the rejection will not be considered a new ground ofrejection if the prior art relied upon, and
`
`the rationale supporting the rejection, would be the same under either status.
`
`The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections
`
`set forth in this Office action:
`
`A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is
`not identically disclosed as set forthin section 102 ofthis title, if the differences between the claimed
`invention and the prior art are such that the claimed invention as a whole would have been obvious
`before the effective filing date of the claimed invention to a person having ordinary skill in the art to
`which the claimed invention pertains. Patentability shall not be negated by the mannerin which the
`invention was made.
`
`The factual inquiries set forth in Graham v. John Deere Co. , 383 U.S. 1, 148 USPQ 459 (1966),
`
`that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are
`
`summarizedas follows:
`
`1. Determining the scope and contents of the priorart.
`2. Ascertaining the differences between the prior art and the claims at issue.
`3. Resolving the level of ordinary skill in the pertinent art.
`4. Considering objective evidence present in the application indicating obviousness or
`nonobviousness.
`
`This application currently names joint inventors. In considering patentability of the claims the
`
`examiner presumesthat the subject matter of the various claims was commonly ownedas of the
`
`effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised
`
`of the obligation under 37 CFR 1.56 to point out the inventor and effectivefiling dates of each claim that
`
`was not commonly ownedas of the effective filing date of the later invention in order for the examiner
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`

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`Application/Control Number: 17/190,261
`Art Unit: 2812
`
`Page 3
`
`to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art
`
`against the later invention.
`
`Claims 1, 4, 7-11, 13-16, and 17-26 are rejected under 35 U.S.C. 103 as being unpatentable
`
`over Ikeda (U.S. PGPub 2014/0183547)in view of Wilson (JPS62259462 A), Israel(U.S. PGPub
`
`2016/0005680), Otremba (U.S. PGPub 2014/0097528), and Sutardja (U.S. Pat. 7528013).
`
`Regarding claim1, Ikeda teaches a semiconductor device (Fig. 1A, [0011]) comprising a nitride
`
`semiconductor chip including a silicon substrate having a first thermal expansion coefficient and an
`
`In(x)Ga(y)Al(1-x-y)N layer in contact with a surface of the substrate (Fig. 1B, 23, 25, 27, [0020]; Fig. 4A,
`
`[0050], [0029], [0048]), the nitride semiconductorchip including a heterojunction interface including a
`
`two-dimensional electron gas layer (Fig. 1B, [0020], GaN layer 25 and AlGaN layer 27 form a
`
`heterojunction with a 2DEG); a plurality of pads including a gate pad, a source pad, and a drain pad, the
`
`plurality of pads being provided on a top side of the nitride semiconductorchip (Fig. 1A, 21a-c, [0014)), a
`
`die pad having a second thermal expansion coefficient (13, [(0013]); a plurality of terminals including a
`
`gate terminal, twosource terminals, anda plurality of drain terminals (15d, 15a-c, 15e-h, [0015]): a first
`
`electrode which is electrically connected to the two source terminals and the die pad (Fig. 3A, 53a,
`
`[0032]); the semiconductordevice is a rectangular package havingafirst side and a secondside that are
`
`two opposed sides and longer sides of the package, the plurality of drain terminals are disposed along
`
`the second side of the semiconductor device, the plurality of drain terminals are separated from the die
`
`pad, the two source terminals are each connected to the source pad witha plurality of first bonding
`
`wires, and an end of eachofthe plurality of first bonding wires is provided at a position overlapping the
`
`two source terminals in the plan view, and the plurality of drain terminals are each connected to the
`
`drain pad with a plurality of second bonding wires, and an end of eachof the second plurality of bonding
`
`wires is provided ata position overlapping the plurality of drain terminals in the plan view (Fig. 1A,Fig.
`
`3A).
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`

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`Application/Control Number: 17/190,261
`Art Unit: 2812
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`Page 4
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`Ikeda does not explicitly teach wherein each source terminal among the two source terminals is
`
`connected to the source pad by a plurality of first bonding wires including gold and eachdrain terminal
`
`amongthe plurality of drain terminals is connected to the drain pad by a plurality of second bonding
`
`wires including gold, and eachdrain terminal amongthe plurality of drain terminals is connected to the
`
`drain pad by four of the plurality of second bonding wires; and a source sensor terminal disposed along
`
`the first side of the semiconductor device, wherein the source sensor terminal is separated from the die
`
`pad; the twosource terminals, the source sensor terminal and the gate terminal are disposed along the
`
`first side of the semiconductor device in this order, the source sensor terminal and the source pad are
`
`connected with at least one third bonding wire, and anumber of the first bonding wires connecting each
`
`source terminal among the two source terminals and the source pad is greaterthana number of the at
`
`least one third bonding wire.
`
`Otremba teaches a source sensor terminal of a semiconductor device, separated from the die
`
`pad (Fig. 3C, 212, [0036]), wherein one or more source terminals, the source sensorterminal, and the
`
`gate terminalare disposed along a side of the semiconductordevice in this order (Fig. 3C, source leads
`
`206, [0024]; gate terminal 356, [0037]); wherein the source sensor terminal and the source pad are
`
`connected with at least one third bonding wire ([0035], [0027]).
`
`Sutardja teaches connecting source and drain pads to respective terminals where each terminal
`
`is connected by a plurality of bonding wires(Fig. 8, Fig. 7, col. 6, |. 33-37), wherein the bonding wires
`
`may be gold (col. 1, |. 52-56; col. 3, |. 22-24; col. 5, |. 4-6), where the plurality of bonding wiresis defined
`
`as at least two(col. 2, |. 1-4) and may beat least four (col. 4, |. 4-9), and wherein the source terminals
`
`are connected via multiple wires(col. 6, |. 33-38).
`
`

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`Application/Control Number: 17/190,261
`Art Unit: 2812
`
`Page5S
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`Therefore it would have been obvious to a person having ordinaryskill in the art at the time of
`
`the effective filing date to combine the teachings of Otremba and Sutardja with Ikeda such that each
`
`source terminal among the two source terminals is connected to the source pad by a plurality offirst
`
`bonding wires including gold and each drain terminalamongthe plurality of drain terminals is connected
`
`to the drain pad by a plurality of second bonding wires including gold, and each drain terminal among
`
`the plurality of drain terminals is connected to the drain pad by four of the plurality of second bonding
`
`wires; and a source sensorterminal disposed along thefirst side of the semiconductor device, wherein
`
`the source sensor terminal is separated from the die pad; the two source terminals, the source sensor
`
`terminal and the gate terminal are disposed along thefirst side of the semiconductor device in this
`
`order, the source sensor terminal and the source pad are connected with at least one third bonding
`
`wire, and a number of the first bonding wires connecting each source terminal among the twosource
`
`terminals and the source pad is greater thana number of the at least one third bonding wire for the
`
`purpose of providing a sensing terminal (Otremba, [0049]) and lowering resistance, supporting high
`
`current flow, and minimizing power dissipation (Sutardja, Fig. 8, Fig. 7, col. 6, |. 33-37).
`
`Ikeda does not explicitly teach wherein the nitride semiconductor chip has a thickness of at least
`
`0.250 mm and at most 0.350 mm; the die pad includes Cu, and the second thermal expansion coefficient
`
`of the die pad including Cuis greater thanthefirst thermal expansion coefficient of the silicon substrate;
`
`an adhesive that joins a backside of the nitride semiconductorchip and the die pad; and wherein a
`
`distance from the second side to a center of the die pad in a plan view of the semiconductor device is
`
`longer than a distance from thefirst side to the center of the die pad.
`
`Israel teaches a semiconductor device ([0005]) with a silicon-based semiconductor device chip
`
`({0003], 320, [0035]), a die pad (310, [(0035]); an adhesive that joins a backside of the semiconductor
`
`chip and the die pad (330, [0035]); wherein a thickness of the semiconductorchip falls within a range of
`
`Small to Large which comprises thicknesses of 0.2 mm and 0.4mm (Table 1). In the case where the
`
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`claimed ranges overlap orlie inside ranges disclosed by the prior art a prima facie case of obviousness
`
`exists. See MPEP 2144.05.
`
`Wilson teaches a semiconductordevice (Fig. 6) comprising a semiconductorchip ([0019], 42) on
`
`a die pad including Cu ([0016]), and wherein the semiconductor chip comprisesa first side and opposite
`
`second side which are wire bonded to a plurality of terminals (Fig. 4, 50, 53,55, [0019]), whereina
`
`distance from the second side to a center of the die pad in a plan view of the semiconductor device is
`
`longer than a distance from thefirst side to the center of the die pad (Fig. 2, C/D, [0015]).
`
`Therefore it would have been obvious to a person having ordinary skill in the art to combine the
`
`teachings of Wilson and Israel with|keda and Sutardja such that the nitride semiconductorchip has a
`
`thickness of at least 0.250 mm and at most 0.350 mm; the die pad includes Cu, and the second thermal
`
`expansion coefficient of the die pad including Cuis greater thanthefirst thermal expansion coefficient
`
`of the silicon substrate; an adhesive that joins a backside of the nitride semiconductor chip and the die
`
`pad; and wherein a distance from the second side to a center of the die pad ina plan view of the
`
`semiconductor device is longer than a distance from the first side to the center of the die pad for the
`
`purpose of controlling the bonding wire length and improving efficiency (Wilson, [0019]; Ikeda teaches
`
`wherein the wires are bonded to the longsides, resulting in adjusting the distance of the die from the
`
`first/second sides), and mounting a semiconductorchip of an appropriate thickness on adie pad of an
`
`appropriate material because the prior art teaches every element, a personof ordinary skill could have
`
`combined them as claimed and in combination each element performs the same function, and the
`
`combination would have yielded predictable results to one of ordinary skill inthe art the time of the
`
`invention. See MPEP 2143 (IA.
`
`The combination of Ikeda, Wilson, Israel, Otremba, and Sutardja as cited above teaches wherein
`
`the chip comprisesa silicon substrate and Cu die pad. The silicon substrate has a first thermal expansion
`
`coefficient and the die pad including Cu has a second thermal expansion coefficient which are intrinsic
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`

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`
`Page 7
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`properties of the material and are known to be such that the second thermal expansion coefficientis
`
`greater thanthefirst thermal expansion coefficient (See Spec at p. 9, |. 7-13).
`
`Regarding claim 4, the combination of Ikeda, Wilson, Israel, Otremba, and Sutardja teaches
`
`wherein thefirst electrode includes a material same as a material of the die pad (Ikeda, [0031], Fig. 3A).
`
`It would have been obvious to a person having ordinary skill in the art to further combine the teachings
`
`of Ikeda, Wilson, Israel, Otremba, and Sutardja for the reasonsset forth in the rejection of claim 1.
`
`Regarding claim 7, the combination of Ikeda, Wilson, Israel, Otremba, and Sutardja teaches
`
`wherein the gate terminal is separated fromthedie pad (Ikeda, [0013], [0032]). It would have been
`
`obvious to a person having ordinary skill in the art to further combine the teachings of Ikeda, Wilson,
`
`Israel, Otremba, and Sutardja for the reasons set forth in the rejection of claim 1.
`
`Regarding claim 8, the combination of Ikeda, Wilson, Israel, Otremba, and Sutardja teaches
`
`wherein the two source terminals and the plurality of drain terminals are disposed respectively at two
`
`opposed sides of the rectangular package(Ikeda, Figs. 1A, 3A). It would have been obvious toa person
`
`having ordinaryskill in the art to further combine the teachings of Ikeda, Wilson, Israel, Otremba, and
`
`Sutardja for the reasons set forth in the rejection of claim 1.
`
`Regarding claim 9, the combination of Ikeda, Wilson, Israel, Otremba, and Sutardja teaches
`
`wherein the first side of the semiconductor device and the second side of the semiconductor device
`
`have a same number of terminals (Ikeda, Figs. 1A, 3A). It would have been obvious to a person having
`
`ordinary skill in the art to further combine the teachings of Ikeda, Wilson, Israel, Otremba, and Sutardja
`
`for the reasons set forth in the rejection of claim1.
`
`Regarding claim 10, the combination of Ikeda, Wilson, Israel, Otremba, and Sutardja teaches
`
`wherein four drain terminals each of which is a drain terminal of the plurality of drain terminals and
`
`disposed along the secondside of the semiconductor device (Ikeda, Figs. 1A, 3A). It would have been
`
`

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`Application/Control Number: 17/190,261
`Art Unit: 2812
`
`Page 8
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`obvious to a person having ordinaryskill in the art to further combine the teachings of Ikeda, Wilson,
`
`Israel, Otremba, and Sutardja for the reasons set forth in the rejection of claim 1.
`
`Regarding claim 11, the combination of Ikeda, Wilson, Israel, Otremba, and Sutardja teaches
`
`wherein the source sensor terminal is used for detecting a voltage level (Otremba, [0043]) It would have
`
`been obvious to a personhaving ordinary skill in the art to further combine the teachings of Ikeda,
`
`Wilson, Israel, Otremba, and Sutardja for the reasons set forth in the rejection of claim 1.
`
`Regarding claim 13, the combination of Ikeda, Wilson, Israel, Otremba, and Sutardja teaches
`
`wherein the nitride semiconductorchip has a first side and a second side that are two opposedsides,
`
`the first side of the nitride semiconductor chip is parallel with the first side of the semiconductor device,
`
`the second side of the nitride semiconductor chip is parallel with the second side of the semiconductor
`
`device, and the plurality of pads are disposed at thefirst side and the second side of the nitride
`
`semiconductor chip (Ikeda, Figs. 1A, 3A). It would have been obvious toa person having ordinaryskill in
`
`the art to further combine the teachings of Ikeda, Wilson, Israel, Otremba, and Sutardja for the reasons
`
`set forth in the rejection of claim 1.
`
`Regarding claim 14, the combination of Ikeda, Wilson, Israel, Otremba, and Sutardja teaches
`
`wherein the source pad is disposed along the first side of the nitride semiconductor chip and the drain
`
`pad is disposed along the second side of the nitride semiconductorchip (Ikeda, Figs. 1A, 3A). It would
`
`have been obvious to a person having ordinaryskill in the art to further combine the teachingsof Ikeda,
`
`Wilson, Israel, Otremba, and Sutardja for the reasons set forth in the rejection of claim 1.
`
`Regarding claim 15, the combination of Ikeda, Wilson, Israel, Otremba, and Sutardja does not
`
`explicitly teach wherein the plurality of the two source terminals are each connected with asame
`
`number of the plurality of first bonding wires. Sutardja teaches wherein the number is “at least two”
`
`(col. 2, |. 1-3) and wherein a tradeoff exists between increased bonding area required for increased
`
`number of wires(col. 2, |. 5-15). Where the generalconditions of a claimare disclosed in the priorart,it
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`

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`Application/Control Number: 17/190,261
`Art Unit: 2812
`
`Page 9
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`is not inventive to discover the optimum or workable ranges by routine experimentation. See MPEP
`
`2144.05(IIJA. It would there have been obvious to a person having ordinaryskill in the art to further
`
`combine the teachings of Ikeda, Wilson, Israel, Otremba, and Sutardja such that the two source
`
`terminals are each connected with asame number of the plurality of first bonding wires.
`
`Regarding claim 17, the combination of Ikeda, Wilson, Israel, Otremba, and Sutardja teaches
`
`wherein out of two opposed main surfaces of the die pad, a main surface not joined to the nitride
`
`semiconductor chip is exposed from the semiconductordevice (Israel, Fig. 2F, [0005]). It would have
`
`been obvious to a person having ordinaryskill in the art to further combine the teachings of Ikeda,
`
`Wilson, Israel, Otremba, and Sutardja for the purpose of providing an exposed heat sink for thermal
`
`coupling (Israel, [0005)]).
`
`Regarding claim 18, the combination of Ikeda, Wilson, Israel, Otremba, and Sutardja teaches
`
`wherein the plurality of terminals are substantially flush with a lateral surface of the rectangular
`
`package (Israel, Fig. 2F, 240, [0029]). It would have been obvious to a person having ordinary skill in the
`
`art to further combine the teachingsof Ikeda, Wilson, Israel, Otremba, and Sutardja for the purpose of
`
`providing exposed area for contacts (Israel, [0029]).
`
`Regarding claim 19, the combination of Ikeda, Wilson, Israel, Otremba, and Sutardja teaches
`
`wherein in a plan view of the semiconductor device, the plurality of terminals are mutually equal in size
`
`(Ikeda, Figs. 1A, 3A; Israel, Fig. 3B). It would have been obvious to a person having ordinaryskill in the
`
`art to further combine the teachings of Ikeda, Wilson, Israel, Otremba, and Sutardja for the reasons set
`
`forth in the rejection of claim 1.
`
`Regarding claim 20, the combination of Ikeda, Wilson, Israel, Otremba, and Sutardja teaches
`
`wherein the plurality of terminals provided on thefirst side of the semiconductor device and the
`
`plurality of terminals provided on the second side of the semiconductor device are provided to beline -
`
`symmetrical to each other (Ikeda, Figs. 1A, 3A; Israel, Fig. 3B). It would have been obvious to a person
`
`

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`Application/Control Number: 17/190,261
`Art Unit: 2812
`
`Page 10
`
`having ordinaryskill in the art to further combine the teachings of Ikeda, Wilson, Israel, Otremba, and
`
`Sutardja for the reasons set forth in the rejection of claim 1.
`
`Regarding claim 21, the combination of Ikeda, Wilson, Israel, Otremba, and Sutardja teaches
`
`wherein a distance between adjacent onesof the plurality of terminals provided on thefirst side of the
`
`semiconductor device and a distance between adjacentones of the plurality of terminals provided on
`
`the second side of the semiconductor device are equal (Ikeda, Figs. 1A, 3A; Israel, Fig. 3B). It would have
`
`been obvious to a person having ordinaryskill in the art to further combine the teachings of Ikeda,
`
`Wilson, Israel, Otremba, and Sutardja for the reasonsset forth in the rejection of claim 1.
`
`Regarding claim 22, the combination of Ikeda, Wilson, Israel, Otremba, and Sutardja teaches
`
`wherein no bonding wire is connected to the die pad (Ikeda, Figs. 1A, 3A). It would have been obvious to
`
`a person having ordinary skill in the art to further combine the teachings of Ikeda, Wilson,Israel,
`
`Otremba, and Sutardja for the reasons set forthin the rejection of claim 1.
`
`Regarding claim 23, the combination of Ikeda, Wilson, Israel, Sutardja, and Otremba teaches
`
`wherein all bonding wires connected to the source pad are connected to the source terminal or the
`
`source sensor terminal (Otremba, Figs. 3C-4, Ikeda Figs. 1A, 3A). It would have been obvious to a person
`
`having ordinaryskill in the art to further combine the teachings of Ikeda, Wilson, Israel, Sutardja, and
`
`Otremba for the reasonsset forth in the rejection of claim 1.
`
`Regarding claim 24, the combination of Ikeda, Wilson, Israel, Otremba, and Sutardja teaches
`
`wherein the nitride semiconductorchip is joined at a center portion of the die pad (Ikeda, Figs. 1A, 3A;
`
`Wilson, Fig. 4, [0019]). It would have been obvious to a person having ordinaryskill in the art to further
`
`combine the teachings of Ikeda, Wilson, Israel, Otremba, and Sutardja for the reasons set forthin the
`
`rejection of claim 1.
`
`Regarding claim 25, the combination of Ikeda, Wilson, Israel, Otremba, and Sutardja teaches
`
`wherein a thickness tm (mm) of the die pad anda length L (mm) of the nitride semiconductorchip
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`satisfies a relationship of tm22.00x10-3xL2+b (b>0) (Israel, Table 1; Medium Dimensionshas L=4,
`
`2.00x10-3xL2 = 0.032, Height of Heatsink HHS= 0.5 mm; Large Dimensions has L=8, 2.00x10-3xL2 =
`
`0.128; Height of Heatsink HHS= 1.2 mm). It would have been obvious to a person having ordinaryskill in
`
`the art to further combine the teachingsof Ikeda, Wilson, Israel, Otremba, and Sutardja for the reasons
`
`set forth in the rejection of claim 1.
`
`Regarding claim 26, the combination of Ikeda, Wilson, Israel, Otremba, and Sutardja teaches
`
`wherein a base area and a side area of the plurality of terminals are equal (Ikeda, Figs. 1A, 3A; Israel, Fig.
`
`3B). It would have been obvious to a person having ordinaryskill in the art to further combine the
`
`teachings of Ikeda, Wilson, Israel, Otremba, and Sutardja for the reasons set forth in the rejection of
`
`claim 1.
`
`Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Ikeda(U.S. PGPub
`
`2014/0183547)in view of Wilson (JP S62259462 A), Israel (U.S. PGPub 2016/0005680), Otremba (U.S.
`
`PGPub 2014/0097528), Sutardja (U.S. Pat. 7528013), and further in view of Harnden (U.S. PGPub
`
`2003/0062601).
`
`Regarding claim 2, the combination of Ikeda, Wilson, Israel, Otremba, and Sutardja does not
`
`explicitly teach a second electrode which mutually and electrically connects the plurality of drain
`
`terminals.
`
`Harnden teaches an electrode which mutually and electrically connects a plurality of drain
`
`terminals ([0217]).
`
`Therefore it would have been obvious to a person having ordinaryskill in the art at the time of
`
`the effective filing date to combine the teachings of Harndenwith Ikeda, Wilson, Israel, Otremba, and
`
`Sutardja suchthat the device includes a second electrode which mutually and electrically connects the
`
`plurality of drain terminals for the purpose of forming a low-resistance contact and allowing more
`
`uniform placementof bond wires ([0217], Fig. 8B).
`
`

`

`Application/Control Number: 17/190,261
`Art Unit: 2812
`
`Page 12
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`Regarding claim 3, the combination of Ikeda, Wilson, Israel, and Harndenteaches wherein the
`
`second electrode includes a materialsameas a material of the die pad (Ikeda, Fig. 3A; Harnden, [0217],
`
`Fig. 8B). lt would have been obvious to a person having ordinary skill in the art to further combine the
`
`teachings of Ikeda, Wilson, Israel, Otremba, and Sutardja for the reasons set forth in the rejection of
`
`claim 2.
`
`Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Ikeda(U.S. PGPub
`
`2014/0183547)in view of Wilson (JP S62259462 A), Israel (U.S. PGPub 2016/0005680), Otremba (U.S.
`
`PGPub 2014/0097528), Sutardja (U.S. Pat. 7528013), and further in view of Chia (U.S. PGPub
`
`2007/0130759).
`
`Regarding claim 5, the combination of Ikeda, Wilson, Israel, Otremba, and Sutardja does not
`
`explicitly teach a third electrode electrically connected to the gate terminal.
`
`Chia teaches wherein a leadframe terminal comprises an electrode electrically connected to the
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`gate terminal ([0023], [0026], [0056], [0072]; second lead frame layer).
`
`Therefore it would have been obvious to a person having ordinaryskill in the art at the time of
`
`the effective filing date to combine the teachings of Chia with Ikeda, Wilson, Israel, Otremba, and
`
`Sutardja suchthat a third electrode is electrically connected to the gate terminal for the purpose of
`
`defining raised features to increase adhesion and package strength ([0020], [0023)).
`
`Regarding claim 6, the combination of Ikeda, Wilson, Israel, and Chia teaches wherein the third
`
`electrode includes a materialsameas a material of the die pad (Chia, [0057]-[0058]). It would have been
`
`obvious to a person having ordinaryskill in the art to further combine the teachingsof Ikeda, Wilson,
`
`Israel, and Chia for the reasons set forth in the rejection of claim 1.
`
`Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Ikeda (U.S. PGPub
`
`2014/0183547)in view of Wilson (JP S62259462 A), Israel (U.S. PGPub 2016/0005680), Otremba (U.S.
`
`

`

`Application/Control Number: 17/190,261
`Art Unit: 2812
`
`Page 13
`
`PGPub 2014/0097528), Sutardja (U.S. Pat. 7528013), and further in view of Ikeda 2007 (U.S. PGPub
`
`2007/0089811).
`
`Regarding claim 24, regarding the limitation “a melting point of the adhesive is higher than a
`
`melting point of asecondary mounting adhesive for mounting the semiconductordevice on a printed
`
`circuit board”, claim scope is not limited by claim language that suggests or makes optional but does not
`
`require steps tobe performed, or by claim language that does not limit a claimtoa particular structure.
`
`See MPEP 2111.04.
`
`The combination of Ikeda, Wilson, Israel, Otremba, and Sutardja does not explicitly teach
`
`wherein the adhesive includes Pb and has a melting point of at least 260 °C and at most 330 °C.
`
`Israel teaches wherein the adhesive is Pb-solder with die attach performed at “about 350 °C”
`
`({0023]). Ikeda 2007 teaches whereina conventional lead solder for die bonding has a melting point of
`
`290 °C or higher ([0004]). In the case where the claimed ranges overlaporlie inside ranges disclosed by
`
`the prior art a prima facie case of obviousness exists. See MPEP 2144.05.
`
`Therefore it would have been obvious to a person having ordinaryskill in the art at the time of
`
`the effective filing date to combine the teachings of Israel 2004 with Ikeda, Wilson, Israel, Otremba, and
`
`Sutardja suchthat the adhesive includes Pb and has a melting point of at least 260 °C and at most 330 °C
`
`for the purpose of using a conventional Pb solder according to Ikeda.
`
`Conclusion
`
`Anyinquiry concerning this communication or earlier communications from the examiner
`
`should be directed to ALIA SABUR whose telephone number is (571)270-7219. The examiner can
`
`normally be reached M-F 9:30-5:30.
`
`Examiner interviews are available via telephone, in-person, and video conferencing using a
`
`USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use
`
`the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
`
`

`

`Application/Control Number: 17/190,261
`Art Unit: 2812
`
`Page 14
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`If attempts to reachthe examiner by telephone are unsuccessful, the examiner’s supervisor,
`
`Charles Garber can be reached on 571-272-2194. The fax phone number for the organization wherethis
`
`application or proceeding is assigned is 571-273-8300.
`
`Information regarding the status of published or unpublished applications may be obtained from
`
`Patent Center. Unpublished application information in Patent Center is available to registered users. To
`
`file and managepatent submissions in Patent Center,visit: https://patentcenter.us pto. gov.Visit
`
`https ://www.us pto.gov/patents/apply/patent-center for more information about Patent Center and
`
`https ://www.uspto.gov/patents/docx for information aboutfiling in DOCX format. For additional
`
`questions, contact the Electronic Business Center (EBC) at 866-217-9197(toll-free). If you would like
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`assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA)or
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`571-272-1000.
`
`/ALIA SABUR/
`Primary Examiner, Art Unit 2812
`
`