ENCODER, DECODER, ENCODING METHOD, AND DECODING METHOD
`
`CROSS REFERENCE TO RELATED APPLICATIONS
`
`This application is a U.S. continuation application of PCT International
`
`Patent Application Number PCT/JP2019/041105 filed on October 18, 2019,
`
`claiming the benefit of priority of U.S. Provisional Patent Application Number
`
`62/748623 filed on October 22, 2018, the entire contents of which are hereby
`
`incorporated by reference.
`
`10
`
`BACKGROUND
`
`1. Technical Field
`
`The present disclosure relates to video coding, and relates to, for
`
`example, a system, a constituent element, a method, etc., in encoding and
`
`decoding of videos.
`
`15
`
`1. Description of the Related Art
`
`The video coding technology has been developed from H.261 and
`
`MPEG-1 to H.264/AVC (Advanced Video Coding), MPEG-LA, H.265/HEVC
`
`(High Efficiency Video Coding), and H.266/VVC (Versatile Video Codec). With
`
`this development, it is always required to improve and optimize video coding
`
`20
`
`technology in order to process digital video data the amount of which has kept
`
`increasing in various kinds of applications.
`
`It is to be noted that Non Patent Literature 1 (H.265 (ISO/IEC 23008-2
`
`HEVC) / HEVC (High Efficiency Video Coding)) relates to one example of a
`
`conventional standard related to the above-described video coding technology.
`
`25
`
`SUMMARY
`
`For example, an encoder according to an aspect of the present disclosure
`
`1
`
`
`
`CROSS REFERENCE TO RELATED APPLICATIONS
`
`This application is a U.S. continuation application of PCT International
`
`Patent Application Number PCT/JP2019/041105 filed on October 18, 2019,
`
`claiming the benefit of priority of U.S. Provisional Patent Application Number
`
`62/748623 filed on October 22, 2018, the entire contents of which are hereby
`
`incorporated by reference.
`
`10
`
`BACKGROUND
`
`1. Technical Field
`
`The present disclosure relates to video coding, and relates to, for
`
`example, a system, a constituent element, a method, etc., in encoding and
`
`decoding of videos.
`
`15
`
`1. Description of the Related Art
`
`The video coding technology has been developed from H.261 and
`
`MPEG-1 to H.264/AVC (Advanced Video Coding), MPEG-LA, H.265/HEVC
`
`(High Efficiency Video Coding), and H.266/VVC (Versatile Video Codec). With
`
`this development, it is always required to improve and optimize video coding
`
`20
`
`technology in order to process digital video data the amount of which has kept
`
`increasing in various kinds of applications.
`
`It is to be noted that Non Patent Literature 1 (H.265 (ISO/IEC 23008-2
`
`HEVC) / HEVC (High Efficiency Video Coding)) relates to one example of a
`
`conventional standard related to the above-described video coding technology.
`
`25
`
`SUMMARY
`
`For example, an encoder according to an aspect of the present disclosure
`
`1
`
`
`
`is an encoderincluding circuitry and memory connected to the circuitry.
`
`In
`
`operation,
`
`the circuitry: derives a correction parameter using only a
`
`neighboring reconstructed image that neighbors a processing unit which has a
`
`determined size andis located at an upperleft of a current block to be processed
`
`in an image, among neighboring reconstructed images that neighbor the
`
`current block, and performs correction processing of the current block based on
`
`the correction parameter derived, when the current block has a size larger than
`
`the determined size.
`
`Some of implementations of embodiments according to the present
`
`10
`
`disclosure may:
`
`improve a coding efficiency;
`
`simplify encoding/decoding;
`
`increase an encoding/decoding speed; and efficiently select appropriate
`
`constituent elements / operations to be used in encoding and decoding, such as
`
`appropriate filters, block sizes, motion vectors, reference pictures, reference
`
`blocks, etc.
`
`15
`
`Further advantages and effects according to one aspect of the present
`
`disclosure will become apparent from the Specification and the Drawings.
`
`These advantages and/or effects are obtainable by some embodiments and
`
`features described in the Specification and the Drawings. However, not all of
`
`the features always need to be provided to obtain one or more advantages
`
`20
`
`and/oreffects.
`
`It
`
`is to be noted that
`
`these general or specific aspects may be
`
`implemented using a system, a method, an integrated circuit, a computer
`
`program, or a recording medium, or any combination thereof.
`
`25
`
`BRIEF DESCRIPTION OF DRAWINGS
`
`These and other objects, advantages and features of the disclosure will
`
`become apparent from the following description thereof taken in conjunction
`
`2
`
`
`
`with the accompanying drawings that illustrate a specific embodiment of the
`
`present disclosure.
`
`FIG.
`
`1 is a block diagram illustrating a configuration of an encoder
`
`according to an embodiment;
`
`FIG. 2 is a flow chart indicating one example of an overall encoding
`
`process performed by the encoder;
`
`FIG. 3 is a conceptual diagram illustrating one example of block
`
`splitting;
`
`FIG. 4A is a conceptual diagram illustrating one example of a slice
`
`10
`
`configuration:
`
`FIG. 4B is a conceptual diagram illustrating one example of a tile
`
`configuration;
`
`FIG. 5A is a chart indicating transform basis functions for various
`
`transform types;
`
`15
`
`FIG. 5B is a conceptual diagram illustrating example spatially varying
`
`transforms (SVT);
`
`FIG. 6A is a conceptual diagram illustrating one example of a filter
`
`shape used in an adaptive loop filter (ALF);
`
`FIG. 6B is a conceptual diagram illustrating another exampleof a filter
`
`20
`
`shape used in an ALF;
`
`FIG. 6C is a conceptual diagram illustrating another exampleof a filter
`
`shape used in an ALF;
`
`FIG. 7 is a block diagram indicating one example of a specific
`
`configuration of a loop filter which functions as a deblocking filter (DBF);
`
`25
`
`FIG. 8 is a conceptual diagram indicating an example of a deblocking
`
`filter having a symmetrical filtering characteristic with respect to a block
`
`boundary;
`
`
`
`FIG. 9 is a conceptual diagram for illustrating a block boundary on
`
`which a deblockingfilter process is performed;
`
`FIG. 10 is a conceptual diagram indicating examples of Bs values;
`
`FIG. 111s a flow chart illustrating one example of a process performed
`
`by a prediction processor of the encoder;
`
`FIG. 12 is a flow chart illustrating another example of a process
`
`performed by the prediction processor of the encoder:
`
`FIG. 13 is a flow chart illustrating another example of a process
`
`performed by the prediction processor of the encoder;
`
`10
`
`FIG.
`
`14 is a conceptual diagram illustrating sixty-seven intra
`
`prediction modes used in intra prediction in an embodiment;
`
`FIG. 15 is a flow chart illustrating an example basic processing flow of
`
`inter prediction;
`
`FIG. 16 is a flow chart illustrating one example of derivation of motion
`
`15
`
`vectors;
`
`FIG. 17 is a flow chart illustrating another example of derivation of
`
`motion vectors;
`
`FIG. 18 is a flow chart illustrating another example of derivation of
`
`motion vectors;
`
`20
`
`FIG. 19 is a flow chart illustrating an example of inter prediction in
`
`normal inter mode;
`
`FIG. 20 is a flow chart illustrating an example of inter prediction in
`
`merge mode;
`
`FIG. 21is a conceptual diagram for illustrating one example of a motion
`
`25
`
`vector derivation process in merge mode;
`
`FIG. 22 is a flow chart illustrating one example of frame rate up
`
`conversion (FRUC)process;
`
`
`
`FIG. 23 is a conceptual diagram forillustrating one example of pattern
`
`matching (bilateral matching) between two blocks along a motion trajectory;
`
`FIG. 24 is a conceptual diagram for illustrating one example of pattern
`
`matching (template matching) between a template in a current picture and a
`
`block in a reference picture;
`
`FIG. 25A is a conceptual diagram for illustrating one example of
`
`deriving a motion vector of each sub-block based on motion vectors of a
`
`plurality of neighboring blocks;
`
`FIG. 25B is a conceptual diagram for illustrating one example of
`
`10
`
`deriving a motion vector of each sub-block in affine mode in which three control
`
`points are used;
`
`FIG. 26A is a conceptual diagram for illustrating an affine merge mode;
`
`FIG. 26B is a conceptual diagram for illustrating an affine merge mode
`
`in which two control points are used;
`
`15
`
`FIG. 26C is a conceptual diagram for illustrating an affine merge mode
`
`in which three control points are used;
`
`FIG. 27 is a flow chart illustrating one example of a process in affine
`
`merge mode;
`
`FIG. 28A is a conceptual diagram for illustrating an affine inter mode
`
`20
`
`in which two control points are used;
`
`FIG. 28B is a conceptual diagram for illustrating an affine inter mode
`
`in which three control points are used;
`
`FIG. 29 is a flow chart illustrating one example of a process in affine
`
`inter mode;
`
`25
`
`FIG. 30A is a conceptual diagram for illustrating an affine inter mode
`
`in which a current block has three control points and a neighboring block has
`
`two control points;
`
`
`
`FIG. 30B is a conceptual diagram for illustrating an affine inter mode
`
`in which a current block has two control points and a neighboring block has
`
`three control points;
`
`FIG. 31A is a flow chart illustrating a merge mode process including
`
`decoder motion vector refinement (DMVR);
`
`FIG. 31B is a conceptual diagram for illustrating one example of a
`
`DMVR process;
`
`FIG. 32 is a flow chart illustrating one example of generation of a
`
`prediction image;
`
`10
`
`FIG. 33 is a flow chart illustrating another example of generation of a
`
`prediction image;
`
`FIG. 34 is a flow chart illustrating another example of generation of a
`
`prediction image:
`
`FIG. 35 is a flow chart illustrating one example of a prediction image
`
`15
`
`correction process performed by an overlapped block motion compensation
`
`(OBMC)process;
`
`FIG. 36 is a conceptual diagram for illustrating one example of a
`
`prediction image correction process performed by an OBMCprocess;
`
`FIG. 37 is a conceptual diagram for illustrating generation of two
`
`20
`
`triangular prediction images;
`
`FIG. 38 is a conceptual diagram for illustrating a model assuming
`
`uniform linear motion;
`
`FIG. 39 is a conceptual diagram for illustrating one example of a
`
`prediction image generation method using a luminance correction process
`
`25
`
`performedbya local illumination compensation (LIC) process;
`
`FIG. 40 is a block diagram illustrating a mounting example of the
`
`encoder;
`
`
`
`FIG. 41 is a block diagram illustrating a configuration of a decoder
`
`according to an embodiment;
`
`FIG. 42 is a flow chart illustrating one example of an overall decoding
`
`process performed by the decoder;
`
`FIG. 43 is a flow chart illustrating one example of a process performed
`
`by a prediction processor of the decoder;
`
`FIG. 44 is a flow chart illustrating another example of a process
`
`performed by the prediction processor of the decoder;
`
`FIG. 45 is a flow chart illustrating an example of inter prediction in
`
`10
`
`normal inter modein the decoder;
`
`FIG. 46 is a block diagram illustrating a mounting example of the
`
`decoder;
`
`FIG. 47 is a diagram schematically illustrating an example of a pipeline
`
`processing unit;
`
`15
`
`FIG. 48 is a diagram schematically illustrating an example of a pipeline
`
`structure in a decoder:
`
`FIG. 49A is a diagram schematically illustrating an example of
`
`conventional LIC processing;
`
`FIG. 49B is a diagram schematically illustrating another example of
`
`20
`
`conventional LIC processing;
`
`FIG. 50A is a flow chart indicating an example of an operation in local
`
`illumination compensation (LIC) processing in a decoder according to a first
`
`aspect;
`
`FIG. 50B is a flow chart indicating another example of an operation in
`
`25
`
`LIC processing in the decoder accordingto the first aspect:
`
`FIG. 51A is a diagram schematically illustrating an example of LIC
`
`processingin thefirst aspect;
`
`
`
`FIG. 51B is a diagram schematically illustrating another example of
`
`LIC processing in thefirst aspect;
`
`FIG. 52 is a diagram for explaining outline of luma mapping chroma
`
`scaling (LMCS)processing in the first aspect:
`
`FIG. 53 is a diagram illustrating an example of a luma mappingtable;
`
`FIG. 54 is a diagram for
`
`illustrating outline of chroma scaling
`
`processing;
`
`FIG. 55 is a flow chart indicating an operation performed by an encoder;
`
`FIG. 56 is a flow chart indicating an operation performed by a decoder;
`
`10
`
`FIG. 57 is a block diagram illustrating an overall configuration of a
`
`content providing system for implementing a content distribution service;
`
`FIG. 58 is a conceptual diagram illustrating one example of an encoding
`
`structure in scalable encoding;
`
`FIG. 59 is a conceptual diagram illustrating one example of an encoding
`
`15
`
`structure in scalable encoding;
`
`FIG. 60 is a conceptual diagram illustrating an example of a display
`
`screen of a web page;
`
`FIG. 61 is a conceptual diagram illustrating an example of a display
`
`screen of a web page:
`
`20
`
`FIG. 62 is a block diagram illustrating one example of a smartphone;
`
`and
`
`FIG. 63 is a block diagram illustrating an example of a configuration of
`
`a smartphone.
`
`25
`
`DETAILED DESCRIPTION OF THE EMBODIMENTS
`
`An encoder according to an aspect of the present disclosure is an
`
`encoder
`
`including circuitry and memory connected to the circuitry.
`
`In
`
`8
`
`
`
`operation,
`
`the circuitry: derives
`
`a correction parameter using only a
`
`neighboring reconstructed image that neighbors a processing unit which has a
`
`determined size andis located at an upperleft of a current block to be processed
`
`in an image, among neighboring reconstructed images that neighbor the
`
`current block, and performs correction processing of the current block based on
`
`the correction parameter derived, when the current block has a size larger than
`
`the determined size.
`
`In this way, it is possible to obtain all signals required to derive the
`
`correction parameter
`
`for
`
`the current block only using the neighboring
`
`10
`
`reconstructed image that neighbors the processing unit having the determined
`
`size located at the upper left of the current block. This makes it possible to
`
`increase the processing speed. Furthermore, it becomes possible to match
`
`processing results obtained when correction processing is performed for each
`
`current block to be processed and when a current block to be processed is split
`
`15
`
`into processing units and correction processing is performed for each processing
`
`unit.
`
`In addition, since only the neighboring reconstructed image that
`
`neighbors the processing unit having the determined size located at the upper
`
`left of the current block among the reconstructed images that neighbor the
`
`current block is used, it becomes possible to reduce memory amountfor storing
`
`20
`
`reconstructed images.
`
`For example, when the size of the current block is larger than the
`
`determinedsize, the circuitry may split the current block into processing units
`
`each having the determined size, derive the correction parameter for the
`
`processing unit located at the upper left of the current block, and perform the
`
`25
`
`correction processing of each of the processing units in the current block
`
`commonly using the correction parameter derived for the processing unit.
`
`In this way, there is no need to derive a new correction parameter for
`
`9
`
`
`
`anotherprocessing unit other than the processing unit located at the upperleft
`
`of the current block, it becomes possible to reduce the processing amount and
`
`increase the processing speed.
`
`For example, when the size of the current block is larger than the
`
`determined size in local illumination compensation (LIC) processing in inter
`
`prediction,
`
`the circuitry may derive an LIC correction parameter using a
`
`neighboring reconstructed image that neighbors the processing unit located at
`
`the upperleft of the current block and a neighboring reconstructed block that
`
`neighbors a reference block corresponding to the processing unit located at the
`
`10
`
`upper left, and perform correction processing by LIC processing of a prediction
`
`imagefor the current block using the LIC correction parameter derived.
`
`In this way, since it is possible to obtain all signals required to derive
`
`the correction parameter for the LIC processing of the prediction imagefor the
`
`current block in the LIC processing of the prediction image for the processing
`
`15
`
`unit located at the upper left of the current block, it becomes possible to
`
`increase the processing speed. Furthermore, it becomes possible to match
`
`processing results obtained when LIC processing is performed for each current
`
`block to be processed and when a current block to be processed is split into
`
`processing units and LIC processing is performed for each processing unit.
`
`In
`
`20
`
`addition, since only the neighboring reconstructed image that neighbors the
`
`area which is the processing unit having the determined size located at the
`
`upper left of the current block among the neighboring reconstructed images
`
`that neighbor the current block is used, it becomes possible to reduce memory
`
`amount for storing reconstructed images.
`
`For example, the determined size may beasize of a pipeline processing
`25
`
`unit.
`
`In this way, since it is possible to set the processing unit having an
`
`10
`
`
`
`appropriate size based on the size of the pipeline processing unit, it is possible
`
`to appropriately reduce the amount of memory to be mounted.
`
`For example, the determined size may be 64 x 64 pixels.
`
`In this way,it is possible to appropriately reduce the amount of memory
`
`to be mounted.
`
`In addition, a decoder according to an aspect of the present disclosure is
`
`a decoder including circuitry and memory connected to the circuitry.
`
`In
`
`operation,
`
`the circuitry: derives a correction parameter using only a
`
`neighboring reconstructed image that neighbors a processing unit which has a
`
`10
`
`determined size and is located at an upperleft of a current block to be processed
`
`in an image, among neighboring reconstructed images that neighbor the
`
`current block, and performs correction processing of the current block based on
`
`the correction parameter derived, when the current block has a size larger than
`
`the determined size.
`
`15
`
`In this way, it is possible to obtain all signals required to derive the
`
`correction parameter
`
`for
`
`the current block only using the neighboring
`
`reconstructed image that neighbors the processing unit having the determined
`
`sizes located at the upperleft of the current block. This makes it possible to
`
`increase the processing speed. Furthermore, it becomes possible to match
`
`20
`
`processing results obtained when correction processing is performed for each
`
`current block to be processed and when a current block to be processed is split
`
`into processing units and correction processing is performed for each processing
`
`unit.
`
`In addition, since only the neighboring reconstructed image that
`
`neighbors an area which is the processing unit having the determined size
`
`25
`
`located at the upperleft of the current block among the reconstructed images
`
`that neighbor the current block is used, it becomes possible to reduce memory
`
`amountfor storing reconstructed images.
`
`11
`
`
`
`For example, when the size of the current block is larger than the
`
`determinedsize, the circuitry may split the current block into processing units
`
`each having the determined size, derive the correction parameter for the
`
`processing unit located at the upperleft of the current block, and perform the
`
`correction processing of each of the processing units in the current block
`
`commonly using the correction parameter derived for the processing unit.
`
`In this way, there is no need to derive a new correction parameter for
`
`another processing unit other than a leading pipeline processing unit in the
`
`current block, it becomes possible to reduce the processing amount and increase
`
`10
`
`the processing speed.
`
`For example, when the size of the current block is larger than the
`
`determined size in local illumination compensation (LIC) processing in inter
`
`prediction,
`
`the circuitry may derive an LIC correction parameter using a
`
`neighboring reconstructed imagethat neighbors the processing unit located at
`
`15
`
`the upperleft of the current block and a neighboring reconstructed block that
`
`neighbors a reference block corresponding to the processing unit located at the
`
`upper left, and perform correction processing by LIC processing of a prediction
`
`image for the current block using the LIC correction parameter derived.
`
`In this way, since it is possible to obtain all signals required to derive
`
`20
`
`the correction parameterfor the LIC processing of the prediction image for the
`
`current block in the LIC processing of the prediction image for the processing
`
`unit located at the upper left of the current block, it becomes possible to
`
`increase the processing speed. Furthermore, it becomes possible to match
`
`processing results obtained when LIC processing is performed for each current
`
`25
`
`block to be processed and when a current block to be processed is split into
`
`processing units and LIC processing is performed for each processing unit.
`
`In
`
`addition, since only the neighboring reconstructed image that neighbors the
`
`12
`
`
`
`area which is the processing unit having the determined size located at the
`
`upper left of the current block among the neighboring reconstructed images
`
`that neighbor the current block is used, it becomes possible to reduce memory
`
`amount for storing reconstructed images.
`
`For example, the determined size may beasize of a pipeline processing
`
`unit.
`
`In this way, since it is possible to set the processing unit having an
`
`appropriate size based on the size of the pipeline processing unit, it is possible
`
`to appropriately reduce the amount of memory to be mounted.
`
`10
`
`For example, the determined size may be 64 x 64 pixels.
`
`In this way,it is possible to appropriately reduce the amount of memory
`
`to be mounted.
`
`In addition, an encoding method according to an aspect of the present
`
`disclosure is an encoding method including: deriving a correction parameter
`
`15
`
`using only a neighboring reconstructed image that neighbors a processing unit
`
`which has a determined size andis located at upperleft of a current block to be
`
`processed in an image, among neighboring reconstructed images that neighbor
`
`the current block, and performing correction processing of the current block
`
`based on the correction parameter derived, when the current block has a size
`
`20
`
`larger than the determined size.
`
`In this way, it is possible to obtain all signals required to derive the
`
`correction parameter
`
`for
`
`the current block only using the neighboring
`
`reconstructed image that neighbors the processing unit having the determined
`
`sizes located at the upperleft of the current block. This makes it possible to
`
`25
`
`increase the processing speed. Furthermore, it becomes possible to match
`
`processing results obtained when correction processing is performed for each
`
`current block to be processed and when a current block to be processed is split
`
`13
`
`
`
`into processing units and correction processing is performed for each processing
`
`unit.
`
`In addition, since only the neighboring reconstructed image that
`
`neighbors the area which is the processing unit having the determined size
`
`located at the upperleft of the current block among the reconstructed images
`
`that neighbor the current block is used, it becomes possible to reduce memory
`
`amountfor storing reconstructed images.
`
`In addition, a decoding method according to an aspect of the present
`
`disclosure is a decoding method, including: deriving a correction parameter
`
`using only a neighboring reconstructed image that neighbors a processing unit
`
`10
`
`which has a determined size andis located at upperleft of a current block to be
`
`processed in an image, among neighboring reconstructed images that neighbor
`
`the current block, and performing correction processing of the current block
`
`based on the correction parameter derived, when the current block has a size
`
`larger than the determined size.
`
`15
`
`In this way, it is possible to obtain all signals required to derive the
`
`correction parameter
`
`for
`
`the current block only using the neighboring
`
`reconstructed image that neighbors the processing unit having the determined
`
`sizes located at the upperleft of the current block. This makes it possible to
`
`increase the processing speed. Furthermore, it becomes possible to match
`
`20
`
`processing results obtained when correction processing is performed for each
`
`current block to be processed and when a current block to be processed is split
`
`into processing units and correction processing is performed for each processing
`
`unit.
`
`In addition, since only the neighboring reconstructed image that
`
`neighbors an area which is the processing unit having the determined size
`
`25
`
`located at the upperleft of the current block among the reconstructed images
`
`that neighbor the current block is used, it becomes possible to reduce memory
`
`amountfor storing reconstructed images.
`
`14
`
`
`
`These general and specific aspects may be implemented using a system,
`
`a device, a method, an integrated circuit, a computer program, or a
`
`computer-readable recording medium such as a CD-ROM,or any combination
`
`of systems, devices, methods,
`
`integrated circuits, computer programs, or
`
`computer-readable recording media.
`
`Hereinafter, embodiments will be described with reference to the
`
`drawings. Note that the embodiments described below each show a general or
`
`specific example. The numerical values, shapes, materials, components, the
`
`arrangement and connection of the components, steps, the relation and order of
`
`10
`
`the steps, etc., indicated in the following embodiments are mere examples, and
`
`are not intended to limit the scope of the claims.
`
`Embodiments of an encoder and a decoder will be described below.
`
`The embodiments are examples of an encoder and a decoder to which the
`
`processes and/or configurations presented in the description of aspects of the
`
`15
`
`present disclosure are applicable. The processes and/or configurations can
`
`also be implemented in an encoderand a decoder different from those according
`
`to the embodiments.
`
`For
`
`example,
`
`regarding the processes
`
`and/or
`
`configurations as applied to the embodiments, any of the following may be
`
`implemented:
`
`20
`
`(1)
`
`Any of the components of the encoder or the decoder according
`
`to the embodiments presented in the description of aspects of the present
`
`disclosure may be substituted or combined with another component presented
`
`anywherein the description of aspects of the present disclosure.
`
`(2)
`
`In the encoder or the decoder according to the embodiments,
`
`25
`
`discretionary changes may be made to functions or processes performed by one
`
`or more components of
`
`the encoder or
`
`the decoder,
`
`such as addition,
`
`substitution, removal, etc., of the functions or processes. For example, any
`
`15
`
`
`
`function or process may be substituted or combined with anotherfunction or
`
`process presented anywhere in the description of aspects of the present
`
`disclosure.
`
`(3)
`
`In methods implemented by the encoder or
`
`the decoder
`
`according to the embodiments, discretionary changes may be made such as
`
`addition, substitution, and removal of one or more of the processes included in
`
`the method. For example, any process in the method may be substituted or
`
`combined with another process presented anywhere in the description of
`
`aspects of the present disclosure.
`
`10
`
`(4)
`
`One or more components included in the encoder or the decoder
`
`according to embodiments may be combined with a component presented
`
`anywhere in the description of aspects of the present disclosure, may be
`
`combined with a component
`
`including one or more functions presented
`
`anywhere in the description of aspects of the present disclosure, and may be
`
`15
`
`combined with a component
`
`that
`
`implements one or more processes
`
`implemented by a component presented in the description of aspects of the
`
`present disclosure.
`
`(5)
`
`A component including one or more functions of the encoder or
`
`the decoder according to the embodiments, or a component that implements one
`
`20
`
`or more processes of the encoderor the decoder according to the embodiments,
`
`may be combinedor substituted with a component presented anywhere in the
`
`description of aspects of the present disclosure, with a componentincluding one
`
`or more functions presented anywhere in the description of aspects of the
`
`present disclosure, or with a component that implements one or more processes
`
`25
`
`presented anywherein the description of aspects of the present disclosure.
`
`(6)
`
`In methods implemented by the encoder or
`
`the decoder
`
`according to the embodiments, any of the processes included in the method may
`
`16
`
`
`
`be substituted or combined with a process presented anywhere in the
`
`description of aspects of the present disclosure or with any corresponding or
`
`equivalent process.
`
`(7)
`
`One or more processes included in methods implemented by the
`
`encoder or the decoder according to the embodiments may be combined with a
`
`process presented anywhere in the description of aspects of the present
`
`disclosure.
`
`(8)
`
`The implementation of the processes and/or configurations
`
`presented in the description of aspects of the present disclosure is not limited to
`
`10
`
`the encoder or the decoder according to the embodiments. For example, the
`
`processes and/or configurations may be implemented in a device used for a
`
`purpose different from the moving picture encoder or the moving picture
`
`decoder disclosed in the embodiments.
`
`[Encoder]
`
`15
`
`First, an encoder according to an embodiment will be described. FIG. 1
`
`is a block diagram illustrating a configuration of encoder 100 according to the
`
`embodiment. Encoder 100 is a video encoder which encodes a video in units of
`
`a block.
`
`Asillustrated in FIG. 1, encoder 100 is an apparatus which encodes an
`
`20
`
`image in units of a block, and includessplitter 102, subtractor 104, transformer
`
`106, quantizer 108, entropy encoder 110,
`
`inverse quantizer 112,
`
`inverse
`
`transformer 114, adder 116, block memory 118, loop filter 120, frame memory
`
`122, intra predictor 124, inter predictor 126, and prediction controller 128.
`
`Encoder 100 is implemented as, for example, a generic processor and
`
`25
`
`memory.
`
`In this case, when a software program stored in the memory is
`
`executed by the processor, the processor functions as splitter 102, subtractor
`
`104, transformer 106, quantizer 108, entropy encoder 110, inverse quantizer
`
`17
`
`
`
`112, inverse transformer 114, adder 116, loop filter 120, intra predictor 124,
`
`inter predictor 126, and prediction controller 128. Alternatively, encoder 100
`
`may be implemented as one or more dedicated electronic circuits corresponding
`
`to splitter 102, subtractor 104, transformer 106, quantizer 108, entropy encoder
`
`110, inverse quantizer 112, inverse transformer 114, adder 116, loop filter 120,
`
`intra predictor 124, inter predictor 126, and prediction controller 128.
`
`Hereinafter, an overall flow of processes performed by encoder 100 is
`
`described, and then each of constituent elements included in encoder 100 will
`
`be described.
`
`10
`
`[Overall Flow of Encoding Process]
`
`FIG. 2 is a flow chart indicating one example of an overall encoding
`
`process performed by encoder 100.
`
`First, splitter 102 of encoder 100 splits each of pictures included in an
`
`input image whichis a video into a plurality of blocks having a fixed size (e.g.,
`
`15
`
`128x128 pixels) (Step Sa_1). Splitter 102 then selects a splitting pattern for
`
`the fixed-size block (also referred to as a block shape) (Step Sa_2).
`
`In other
`
`words, splitter 102 further splits the fixed-size block into a plurality of blocks
`
`which form the selected splitting pattern. Encoder 100 performs, for each of
`
`the plurality of blocks, Steps Sa_3 to Sa_9 for the block (that is a current block
`
`20
`
`to be encoded).
`
`In other words, a prediction processor which includesall or part of intra
`
`predictor 124, inter predictor 126, and prediction controller 128 generates a
`
`prediction signal (also referred to as a prediction block) of the current block to
`
`be encoded (also referred to as a current block) (Step Sa_3).
`
`25
`
`Next, subtractor 104 generates a difference between the current block
`
`and a prediction block as a prediction residual (also referred to as a difference
`
`block) (Step Sa_4).
`
`18
`
`
`
`Next, transformer 106 transforms the difference block and quantizer
`
`108 quantizes the result, to generate a plurality of quantized coefficients (Step
`
`Sa_5).
`
`It is to be noted that the block having the plurality of quantized
`
`coefficients is also referred to as a coefficient block.
`
`Next, entropy encoder 110 encodes (specifically, entropy encodes) the
`
`coefficient block and a prediction parameter related to generation of a
`
`prediction signal to generate an encoded signal (Step Sa_6).
`
`It is to be noted
`
`that
`
`the encoded signal
`
`is also referred to as an encoded bitstream, a
`
`compressed bitstream, or a stream.
`
`10
`
`Next,
`
`inverse quantizer 112 performs inverse quantization of the
`
`coefficient block and inverse transformer 114 performs inverse transform of the
`
`result, to restore a plurality of prediction residuals (that is, a difference block)
`
`(Step Sa_7).
`
`Next, adder 116 adds the prediction block to the restored difference
`
`15
`
`block to reconstruct the current block as a reconstructed image(also referred to
`
`as a reconstructed block or a decoded image block) (Step Sa_8).
`
`In this way,
`
`the reconstructed image is generated.
`
`When the reconstructed image is generated, loop filter 120 performs
`
`filtering of the reconstructed image as necessary (Step Sa_9).
`
`20
`
`Encoder 100 then determines whether encoding of the entire picture
`
`has been finished (Step Sa_10). When determining that the encoding has not
`
`yet been finished (No in Step Sa_10), processes from Step Sa_2 are executed
`
`repeatedly.
`
`Although encoder 100 selects one splitting pattern for a fixed-size block,
`
`25
`
`and encodeseach block accordingto the splitting pattern in the above-described
`
`example, it is to be noted that each block may be encoded according to a
`
`corresponding oneof a plurality of splitting patterns.
`
`In this case, encoder 100
`
`19
`
`
`
`may evaluate a cost for each of the plurality of s
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