throbber
DECODER AND DECODING METHOD
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`CROSS REFERENCE TO RELATED APPLICATIONS
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`This application is a U.S. continuation application of PCT International
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`Patent Application Number PCT/JP2019/047886 filed on December 6, 2019
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`claiming the benefit of priority of U.S. Provisional Patent Application Number
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`62/776780 filed on December 7, 2018, U.S. Provisional Patent Application
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`Number 62/776792 filed on December 7, 2018, U.S. Provisional Patent
`
`Application Number 62/808540 filed on February 21, 2019, and U.S.
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`10
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`Provisional Patent Application Number 62/839033 filed on April 26, 2019, the
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`entire contents of which are hereby incorporated by reference.
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`1. Technical Field
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`BACKGROUND
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`15
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`This disclosure relates to at least one of an encoder, an encoding
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`method, a decoder, or a decoding method.
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`2. Description of the Related Art
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`With advancement in video coding technology, from H.261 and MPEG-1
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`20
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`to H.264/AVC (Advanced Video Coding), MPEG-LA, H.265/HEVC (High
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`Efficiency Video Coding) and H.266/VVC (Versatile Video Coding),
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`there
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`remains a constant need to provide improvements and optimizations to the
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`video coding technology to process an ever-increasing amount of digital video
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`data in various applications.
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`SUMMARY
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`According to one aspect of the present disclosure, a decoder includes
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`1
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`

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`memory and a processor coupled to the memory. The processor is configured
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`to split a current picture into tiles, generate a slice having a rectangular shape
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`and located at a lower-right corner of the current picture, the slice including at
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`least a part of a tile among thetiles, generate first information on a region of
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`the slice with header information,
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`the header information not
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`including
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`information identical to the first information, and decode theslice with the first
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`information.
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`BRIEF DESCRIPTION OF DRAWINGS
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`These and other objects, advantages and features of the disclosure will
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`become apparent from the following description thereof taken in conjunction
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`with the accompanying drawings that illustrate a specific embodiment of the
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`present disclosure.
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`FIG.
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`1 is a block diagram illustrating a configuration of an encoder
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`15
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`according to an embodiment;
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`FIG. 2 is a flow chart indicating one example of an overall encoding
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`process performed by the encoder;
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`FIG. 3 is a conceptual diagram illustrating one example of block
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`splitting:
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`FIG. 4A is a conceptual diagram illustrating one example of a slice
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`configuration;
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`FIG. 4B is a conceptual diagram illustrating one example of a tile
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`configuration;
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`FIG. 5A is a chart indicating transform basis functions for various
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`transform types;
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`FIG. 5B is a conceptual diagram illustrating example spatially varying
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`transforms (SVT);
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`

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`FIG. 6A is a conceptual diagram illustrating one example of a filter
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`shape used in an adaptive loop filter (ALF);
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`FIG. 6B is a conceptual diagram illustrating another exampleof a filter
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`shape used in an ALF;
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`FIG. 6C is a conceptual diagram illustrating another exampleof a filter
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`shape used in an ALF;
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`FIG. 7 is a block diagram indicating one example of a specific
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`configuration of a loop filter which functions as a deblocking filter (DBF);
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`FIG. 8 is a conceptual diagram indicating an example of a deblocking
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`filter having a symmetrical filtering characteristic with respect to a block
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`boundary;
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`FIG. 9 is a conceptual diagram for illustrating a block boundary on
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`which a deblockingfilter process is performed;
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`FIG. 10 is a conceptual diagram indicating examples of Bs values;
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`FIG. 11 is a flow chartillustrating one example of a process performed
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`by a prediction processor of the encoder;
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`FIG. 12 is a flow chart illustrating another example of a process
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`performed by the prediction processor of the encoder;
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`FIG. 13 is a flow chart illustrating another example of a process
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`performed by the prediction processorof the encoder;
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`FIG.
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`14 is a conceptual diagram illustrating sixty-seven intra
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`prediction modes used in intra prediction in an embodiment;
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`FIG. 15 is a flow chart illustrating an example basic processing flow of
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`inter prediction;
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`FIG. 16 is a flow chart illustrating one example of derivation of motion
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`vectors;
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`FIG. 17 is a flow chart illustrating another example of derivation of
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`motion vectors;
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`FIG. 18 is a flow chart illustrating another example of derivation of
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`motion vectors;
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`FIG. 19 is a flow chart illustrating an example of inter prediction in
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`normal inter mode;
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`FIG. 20 is a flow chart illustrating an example of inter prediction in
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`merge mode;
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`FIG. 21is a conceptual diagram for illustrating one example of a motion
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`vector derivation process in merge mode;
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`FIG. 22 is a flow chart illustrating one example of frame rate up
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`conversion (FRUC)process;
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`FIG. 23 is a conceptual diagram for illustrating one example of pattern
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`matching (bilateral matching) between two blocks along a motion trajectory;
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`FIG. 24 is a conceptual diagram for illustrating one example of pattern
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`matching (template matching) between a template in a current picture and a
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`block in a reference picture;
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`FIG. 25A is a conceptual diagram for illustrating one example of
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`deriving a motion vector of each sub-block based on motion vectors of a
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`plurality of neighboring blocks;
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`FIG. 25B is a conceptual diagram for illustrating one example of
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`deriving a motion vector of each sub-block in affine mode in which three control
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`points are used;
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`FIG. 26A is a conceptual diagram forillustrating an affine merge mode;
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`FIG. 26B is a conceptual diagram for illustrating an affine merge mode
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`in which two control points are used;
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`FIG. 26C is a conceptual diagram forillustrating an affine merge mode
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`in which three control points are used;
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`

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`FIG. 27 is a flow chart illustrating one example of a process in affine
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`merge mode;
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`FIG. 28A is a conceptual diagram for illustrating an affine inter mode
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`in which twocontrol points are used;
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`FIG. 28B is a conceptual diagram for illustrating an affine inter mode
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`in which three control points are used;
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`FIG. 29 is a flow chart illustrating one example of a process in affine
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`inter mode;
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`FIG. 30A is a conceptual diagram for illustrating an affine inter mode
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`in which a current block has three control points and a neighboring block has
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`two control points;
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`FIG. 30B is a conceptual diagram for illustrating an affine inter mode
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`in which a current block has two control points and a neighboring block has
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`three control points;
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`FIG. 31A is a flow chart illustrating a merge mode process including
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`decoder motion vector refinement (DMVR);
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`FIG. 31B is a conceptual diagram for illustrating one example of a
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`DMVR process;
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`FIG. 32 is a flow chart illustrating one example of generation of a
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`prediction image;
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`FIG. 33 is a flow chart illustrating another example of generation of a
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`prediction image;
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`FIG. 34 is a flow chart illustrating another example of generation of a
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`prediction image;
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`FIG. 35 is a flow chart illustrating one example of a prediction image
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`correction process performed by an overlapped block motion compensation
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`(OBMC)process;
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`FIG. 36 is a conceptual diagram for illustrating one example of a
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`prediction image correction process performed by an OBMCprocess;
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`FIG. 37 is a conceptual diagram for illustrating generation of two
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`triangular prediction images;
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`FIG. 38 is a conceptual diagram for illustrating a model assuming
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`uniform linear motion;
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`FIG. 39 is a conceptual diagram for illustrating one example of a
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`prediction image generation method using a luminance correction process
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`performedbya local illumination compensation (LIC) process;
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`10
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`FIG. 40 is a block diagram illustrating a mounting example of the
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`encoder;
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`FIG. 41 is a block diagram illustrating a configuration of a decoder
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`according to an embodiment;
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`FIG. 42 is a flow chart illustrating one example of an overall decoding
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`15
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`process performed by the decoder;
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`FIG. 43 is a flow chart illustrating one example of a process performed
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`by a prediction processor of the decoder;
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`FIG. 44 is a flow chart illustrating another example of a process
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`performed by the prediction processor of the decoder;
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`FIG. 45 is a flow chart illustrating an example of inter prediction in
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`normal inter mode in the decoder;
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`FIG. 46 is a block diagram illustrating a mounting example of the
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`decoder;
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`FIG. 47A is a diagram illustrating one example of a picture
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`configuration in which a picture is split into one or moretile sets with respect to
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`tile boundaries, according to Aspect 1 of Embodiment1.
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`FIG. 47B is a diagram illustrating another example of the picture
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`

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`configuration in which the pictureis split into one or moretile sets with respect
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`to tile boundaries, according to Aspect 1 of Embodiment1.
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`FIG. 47C is a diagram illustrating another example of the picture
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`configuration in which the picture is split into one or moretile sets with respect
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`to tile boundaries, according to Aspect 1 of Embodiment1.
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`FIG. 47D is a diagram illustrating another example of the picture
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`configuration in which the picture is split into one or moretile sets with respect
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`to tile boundaries, according to Aspect 1 of Embodiment1.
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`FIG. 48Ais a diagram illustrating one example of syntax for encoding a
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`tile group included in a picture in encodingof the picture, according to Aspect 1
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`of Embodiment1.
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`FIG. 48B is a diagram illustrating one example of syntax with respect
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`to a tile group, according to Aspect 1 of Embodiment 1.
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`FIG. 49A is a diagram illustrating a basic encoding order and one
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`15
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`example of tile sets included in a picture, according to Aspect 1 of Embodiment
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`1.
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`FIG. 49B is a diagram illustrating an example in which,in the same tile
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`sets as FIG. 49A, the encoding orderof tile groups is changed.
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`FIG. 50A is a flow chart illustrating a decoding process performed on a
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`tile group by a decoderaccording to Aspect 1 of Embodiment1.
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`FIG. 50B is a flow chart illustrating one example of an error detection
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`process and an error concealment process during the decoding process
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`performed on a tile group by the decoderaccording to Aspect 1 of Embodiment
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`1.
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`25
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`FIG. 51A is a diagram illustrating one example of the case wheretile
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`extraction information SEI is encoded after a picture, according to Aspect 1 of
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`Embodiment 1.
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`

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`FIG. 51B is a diagram illustrating one example of the case where tile
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`extraction information SEI is encoded before a picture, according to Aspect 1 of
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`Embodiment1.
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`FIG. 52 is a diagram illustrating one example of syntax for encodingtile
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`extraction information SEI, according to Aspect 1 of Embodiment 1.
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`FIG. 53 is a diagram illustrating one example of syntax for encoding a
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`tile included in a picture in encoding of the picture, according to Aspect 2 of
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`Embodiment 1.
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`FIG. 54A is a diagram illustrating a basic encoding order and one
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`10
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`example of tile sets included in a picture, according to Aspect 2 of Embodiment
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`1.
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`FIG. 54B is a diagram illustrating an example in which,in tile sets each
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`including the sametile groups as FIG. 54A, the encoding order of tiles is
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`changed.
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`15
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`FIG. 55A is a flow chart illustrating a decoding process performed on a
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`tile by a decoder according to Aspect 2 of Embodiment1.
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`FIG. 55B is a flow chart illustrating one example of an error detection
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`process and an error concealment process during the decoding process
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`performed onatile by the decoder according to Aspect 2 of Embodiment 1.
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`FIG. 56A is a diagram illustrating one example of the case where tile
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`extraction information SEI is encoded after a picture, according to Aspect 2 of
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`Embodiment1.
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`FIG. 56B is a diagram illustrating one example of the case where tile
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`extraction information SEI is encoded before a picture, according to Aspect 2 of
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`25
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`Embodiment 1.
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`FIG. 57 is a diagram illustrating one example of syntax for encodingtile
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`extraction information SEI, according to Aspect 2 of Embodiment 1.
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`8
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`

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`FIG. 58A is a diagram illustrating one example of a picture
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`configuration when a picture is split into rectangular regions and encoded,
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`according to Aspect. 3 of Embodiment 1.
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`FIG. 58B is a diagram illustrating another example of the picture
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`configuration when the picture is split into rectangular regions and encoded,
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`according to Aspect 3 of Embodiment1.
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`FIG. 59 is a diagram illustrating one example of syntax of a picture
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`parameter set (PPS) for splitting and encoding a picture in encoding of the
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`picture, according to Aspect 3 of Embodiment1.
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`10
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`FIG. 60 is a flow chart illustrating one example of a rectangular slice
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`setting process performed in a rectangular slice mode by a decoder according to
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`Aspect 3 of Embodiment1.
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`FIG. 61 is a diagram illustrating one example of syntax of a picture
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`parameter set (PPS) for splitting and encoding a picture in encoding of the
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`15
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`picture, according to Aspect 4 of Embodiment1.
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`FIG. 62 is a flow chart illustrating one example of a rectangular slice
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`setting process performed in a rectangular slice mode by a decoder according to
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`Aspect 4 of Embodiment1.
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`FIG. 63 is a diagram illustrating one example of syntax of a picture
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`20
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`parameter set (PPS) for splitting and encoding a picture in encoding of the
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`picture, according to Aspect 5 of Embodiment 1.
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`FIG. 64 is a flow chart illustrating one example of a slice modesetting
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`process when a decoder decodes
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`slice data, according to Aspect
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`5 of
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`Embodiment1.
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`25
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`FIG. 65 is a diagram ilustrating one example of syntax of a picture
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`parameter set (PPS) for splitting and encoding a picture in encoding of the
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`picture, according to Aspect 6 of Embodiment 1.
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`

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`FIG. 66 is a flow chart illustrating one example of a brick setting
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`process when a decoder decodes brick data, according to Aspect 6 of
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`Embodiment1.
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`FIG. 67 is a block diagram illustrating an implementation example of
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`an encoder according to Embodiment1.
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`FIG. 68 is a flow chart illustrating an operation example of the encoder
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`shown in FIG. 67.
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`FIG. 69 is a block diagram illustrating an implementation example of a
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`decoder according to Embodiment 1.
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`10
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`FIG. 70 is a flow chart illustrating an operation example of the decoder
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`shownin FIG. 69.
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`FIG. 71 is a block diagram illustrating an overall configuration of a
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`content providing system for implementing a content distribution service;
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`FIG. 72 is a conceptual diagram illustrating one example of an encoding
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`15
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`structure in scalable encoding;
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`FIG. 73 is a conceptual diagram illustrating one example of an encoding
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`structure in scalable encoding;
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`FIG. 74 is a conceptual diagram illustrating an example of a display
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`screen of a web page:
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`FIG. 75 is a conceptual diagram illustrating an example of a display
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`screen of a web page;
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`FIG. 76 is a block diagram illustrating one example of a smartphone:
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`and
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`FIG. 77 is a block diagram illustrating an example of a configuration of
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`a smartphone.
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`DETAILED DESCRIPTION OF THE EMBODIMENTS
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`

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`For example, an encoder according to one aspect of the present
`
`disclosure is an encoder that encodes an image.
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`The encoder includes:
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`circuitry; and memory coupled to the circuitry,
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`in which in operation,
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`the
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`circuitry:
`
`splits a current picture to be encoded into two or moretiles:
`
`encodes the current picture by performing the encoding onaslice basis, the
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`slice being rectangular-shaped and made up of one or moretiles or a part of a
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`tile obtained by the splitting; and in the encoding of the current picture,
`
`excludes, from header information, information on a region occupied byaslice
`
`located at a lower-right corner of the current picture.
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`10
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`With this, it is possible to exclude and omit a part of information on a
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`slice setting method from a picture parameter set, and thus the encoder can
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`reduce a coding amount.
`
`Moreover, for example, the information on the region is information
`
`indicating a position of a lower-right corner of the slice located at
`
`the
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`15
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`lower-right corner of the current picture.
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`Moreover, for example, the information on the region is information
`
`indicating a position of an upper-left corner and a position of a lower-right
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`corner of the slice located at the lower-right corner of the current picture.
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`Moreover, for example, the information on the region is information
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`20
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`represented by syntax.
`
`Moreover,
`
`for example,
`
`in operation,
`
`the circuitry further,
`
`in the
`
`encoding of the current picture, adds,
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`to the header information, position
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`information of an upper-left corner of a slice located at the beginning of the
`
`current picture as information indicating a position of an upper-left corner of
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`25
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`the current picture.
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`Moreover, a decoder according to one aspect of the present disclosure is
`
`a decoder that decodes animage. The decoderincludes: circuitry; and memory
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`11
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`

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`coupled to the circuitry, in which in operation, the circuitry: splits a current
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`picture to be decoded into two or more tiles; decodes the current picture by
`
`performing the decoding onaslice basis, theslice being rectangular-shaped and
`
`made up of one or moretiles or a partof a tile obtained by the splitting; and in
`
`the decoding of the current picture, sets information on a region occupied by a
`
`slice located at a lower-right corner of the current picture in a predetermined
`
`manner without using header information, and the information on the region 1s
`
`excluded from the header information.
`
`With this, it is possible to perform decoding even when a part of
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`10
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`information on a slice setting method is excluded from a picture parameterset.
`
`Accordingly, the decoder can reduce a coding amount of a bitstream to be
`
`obtained.
`
`Moreover, for example, the information on the region is information
`
`indicating a position of a lower-right corner of the slice located at
`
`the
`
`15
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`lower-right corner of the current picture.
`
`Moreover, for example, the information on the region is information
`
`indicating a position of an upper-left corner and a position of a lower-right
`
`corner of the slice located at the lower-right corner of the current picture.
`
`Moreover, for example, the information on the region is information
`
`20
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`represented by syntax.
`
`Moreover,
`
`for example,
`
`in operation,
`
`the circuitry further,
`
`in the
`
`decoding of the current picture, decodes position information of an upper-left
`
`corner of a slice located at
`
`the beginning of the current picture from
`
`information indicating a position of an upper-left corner of the current picture,
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`25
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`the information indicating the position of the upper-left corner of the current
`
`picture being included in the header information.
`
`Moreover, for example, an encoding method according to one aspect of
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`12
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`

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`the present disclosure is an encoding method of encoding an image. The
`
`encoding method includes: splitting a current picture to be encoded into two or
`
`more tiles; encoding the current picture by performing the encoding onaslice
`
`basis, the slice being rectangular-shaped and made up of one or more tiles or a
`
`part of a tile obtained by the splitting; and in the encoding of the current
`
`picture, excluding, from header information, information on a region occupied
`
`by a slice located at a lower-right corner of the current picture.
`
`With this, it is possible to exclude and omit a part of information on a
`
`slice setting method from a picture parameter set, and thus the encoding
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`10
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`method can reduce a coding amount.
`
`Moreover, for example, a decoding method according to one aspect of the
`
`present disclosure is a decoding method of decoding an image. The decoding
`
`method comprising: splitting a current picture to be decoded into two or more
`
`tiles; decoding the current picture by performing the decoding onaslice basis,
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`15
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`the slice being rectangular-shaped and made up of one or moretiles or a part of
`
`a tile obtained by the splitting: and in the decoding of the current picture,
`
`setting information on a region occupied by a slice located at a lower-right
`
`corner of the current picture in a predetermined manner without using header
`
`information, in which the information on the region is excluded from the header
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`20
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`information.
`
`With this, it is possible to perform decoding even when a part of
`
`information on a slice setting method is excluded from a picture parameterset.
`
`Accordingly, the decoding method can reduce a coding amountof a bitstream to
`
`be obtained.
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`25
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`Furthermore, these general and specific aspects may be implemented
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`using a system, a device, a method, an integrated circuit, a computer program,
`
`a non-transient recording medium such as a computer-readable CD-ROM, or
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`

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`any combination of systems, devices, methods, integrated circuits, computer
`
`programs or recording media.
`
`Hereinafter, embodiments will be described with reference to the
`
`drawings. Note that the embodiments described below each show a general or
`
`specific example. The numerical values, shapes, materials, components, the
`
`arrangement and connection of the components, steps, the relation and order of
`
`the steps, etc., indicated in the following embodiments are mere examples, and
`
`are not intended to limit the scope of the claims.
`
`Embodiments of an encoder and a decoder will be described below.
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`10
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`The embodiments are examples of an encoder and a decoder to which the
`
`processes and/or configurations presented in the description of aspects of the
`
`present disclosure are applicable. The processes and/or configurations can
`
`also be implemented in an encoder anda decoderdifferent from those according
`
`to the embodiments.
`
`For
`
`example,
`
`regarding the processes
`
`and/or
`
`15
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`configurations as applied to the embodiments, any of the following may be
`
`implemented:
`
`(1) Any of the components of the encoder or the decoder according to the
`
`embodiments presented in the description of aspects of the present disclosure
`
`may be substituted or combined with another component presented anywhere
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`20
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`in the description of aspects of the present disclosure.
`
`(2) In the encoder or
`
`the decoder according to the embodiments,
`
`discretionary changes may be madeto functions or processes performed by one
`
`or more components of
`
`the encoder or
`
`the decoder,
`
`such as addition,
`
`substitution, removal, etc., of the functions or processes. For example, any
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`25
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`function or process may be substituted or combined with another function or
`
`process presented anywhere in the description of aspects of the present
`
`disclosure.
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`

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`(3) In methods implemented by the encoderor the decoder according to
`
`the embodiments, discretionary changes may be made such as addition,
`
`substitution, and removal of one or more of the processes included in the
`
`method. For example, any process in the method may be substituted or
`
`combined with another process presented anywhere in the description of
`
`aspects of the present disclosure.
`
`(4) One or more components included in the encoder or the decoder
`
`according to embodiments may be combined with a component presented
`
`anywhere in the description of aspects of the present disclosure, may be
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`10
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`combined with a component
`
`including one or more functions presented
`
`anywherein the description of aspects of the present disclosure, and may be
`
`combined with a component
`
`that
`
`implements one or more processes
`
`implemented by a component presented in the description of aspects of the
`
`present disclosure.
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`15
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`(5) A component including one or more functions of the encoder or the
`
`decoder according to the embodiments, or a component that implements one or
`
`more processes of the encoder or the decoder according to the embodiments,
`
`may be combinedor substituted with a component presented anywherein the
`
`description of aspects of the present disclosure, with a component including one
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`20
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`or more functions presented anywhere in the description of aspects of the
`
`present disclosure, or with a component that implements one or more processes
`
`presented anywherein the description of aspects of the present disclosure.
`
`(6) In methods implemented by the encoderor the decoder according to
`
`the embodiments, any of the processes included in the method may be
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`25
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`substituted or combined with a process presented anywhere in the description
`
`of aspects of the present disclosure or with any corresponding or equivalent
`
`process.
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`15
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`

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`(7) One or more processes included in methods implemented by the
`
`encoder or the decoder according to the embodiments may be combined with a
`
`process presented anywhere in the description of aspects of the present
`
`disclosure.
`
`(8) The implementation of
`
`the processes
`
`and/or configurations
`
`presented in the description of aspects of the present disclosure is not limited to
`
`the encoder or the decoder according to the embodiments. For example, the
`
`processes and/or configurations may be implemented in a device used for a
`
`purpose different from the moving picture encoder or the moving picture
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`10
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`decoder disclosed in the embodiments.
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`[Encoder]
`
`First, an encoder according to an embodiment will be described. FIG.
`
`1is a block diagram illustrating a configuration of encoder 100 according to the
`
`embodiment. Encoder 100 is a video encoder which encodesa video in units of
`
`15
`
`a block.
`
`Asillustrated in FIG. 1, encoder 100 is an apparatus which encodes an
`
`imagein unitsof a block, and includessplitter 102, subtractor 104, transformer
`
`106, quantizer 108, entropy encoder 110,
`
`inverse quantizer 112,
`
`inverse
`
`transformer 114, adder 116, block memory 118, loop filter 120, frame memory
`
`20
`
`122, intra predictor 124, inter predictor 126, and prediction controller 128.
`
`Encoder 100 is implemented as, for example, a generic processor and
`
`memory.
`
`In this case, when a software program stored in the memory is
`
`executed by the processor, the processor functions as splitter 102, subtractor
`
`104, transformer 106, quantizer 108, entropy encoder 110, inverse quantizer
`
`25
`
`112, inverse transformer 114, adder 116, loop filter 120, intra predictor 124,
`
`inter predictor 126, and prediction controller 128. Alternatively, encoder 100
`
`may be implemented as one or more dedicated electronic circuits corresponding
`
`16
`
`

`

`to splitter 102, subtractor 104, transformer 106, quantizer 108, entropy encoder
`
`110, inverse quantizer 112, inverse transformer 114, adder 116, loop filter 120,
`
`intra predictor 124, inter predictor 126, and prediction controller 128.
`
`Hereinafter, an overall flow of processes performed by encoder 100 is
`
`described, and then each of constituent elements included in encoder 100 will
`
`be described.
`
`[Overall Flow of Encoding Process]
`
`FIG. 2 is a flow chart indicating one example of an overall encoding
`
`process performed by encoder 100.
`
`10
`
`First, splitter 102 of encoder 100 splits each of pictures included in an
`
`input image whichis a video into a plurality of blocks havinga fixed size (e.¢.,
`
`128x128 pixels) (Step Sa_1). Splitter 102 then selects a splitting pattern for
`
`the fixed-size block (also referred to as a block shape) (Step Sa_2).
`
`In other
`
`words, splitter 102 further splits the fixed-size block into a plurality of blocks
`
`15
`
`which form the selected splitting pattern. Encoder 100 performs, for each of
`
`the plurality of blocks, Steps Sa_3 to Sa_9 for the block (that is a current block
`
`to be encoded).
`
`In other words, a prediction processor which includesall or part of intra
`
`predictor 124, inter predictor 126, and prediction controller 128 generates a
`
`20
`
`prediction signal (also referred to as a prediction block) of the current block to
`
`be encoded (also referred to as a current block) (Step Sa_3).
`
`Next, subtractor 104 generates a difference between the current block
`
`and a prediction block as a prediction residual (also referred to as a difference
`
`block) (Step Sa_4).
`
`25
`
`Next, transformer 106 transforms the difference block and quantizer
`
`108 quantizes the result, to generate a plurality of quantized coefficients (Step
`
`Sa_5).
`
`It is to be noted that the block having the plurality of quantized
`
`17
`
`

`

`coefficients is also referred to as a coefficient block.
`
`Next, entropy encoder 110 encodes (specifically, entropy encodes) the
`
`coefficient block and a prediction parameter related to generation of a
`
`prediction signal to generate an encoded signal (Step Sa_6).
`
`It is to be noted
`
`that
`
`the encoded signal
`
`is also referred to as an encoded bitstream, a
`
`compressed bitstream, or a stream.
`
`Next,
`
`inverse quantizer 112 performs inverse quantization of the
`
`coefficient block and inverse transformer 114 performs inverse transform of the
`
`result, to restore a plurality of prediction residuals (that is, a difference block)
`
`10
`
`(Step Sa_7).
`
`Next, adder 116 adds the prediction block to the restored difference
`
`block to reconstruct the current block as a reconstructed image(also referred to
`
`as a reconstructed block or a decoded image block) (Step Sa_8).
`
`In this way,
`
`the reconstructed imageis generated.
`
`15
`
`When the reconstructed image is generated, loop filter 120 performs
`
`filtering of the reconstructed image as necessary (Step Sa_9).
`
`Encoder 100 then determines whether encoding of the entire picture
`
`has been finished (Step Sa_10). When determining that the encoding has not
`
`yet been finished (No in Step Sa_10), processes from Step Sa_2 are executed
`
`20
`
`repeatedly.
`
`Although encoder 100 selects one splitting pattern for a fixed-size block,
`
`and encodes each block accordingto the splitting pattern in the above-described
`
`example, it is to be noted that each block may be encoded according to a
`
`corresponding one of a plurality of splitting patterns.
`
`In this case, encoder 100
`
`25
`
`may evaluate a cost for each of the plurality of splitting patterns, and, for
`
`example, may select the encoded signal obtainable by encoding according to the
`
`splitting pattern which yields the smallest cost as an encoded signal which is
`
`18
`
`

`

`output.
`
`As illustrated, the processes in Steps Sa_1 to Sa_10 are performed
`
`sequentially by encoder 100. Alternatively, two or more of the processes may
`
`be performed in parallel, the processes may be reordered,etc.
`
`[Splitter]
`
`Splitter 102 splits each of pictures included in an input video into a
`
`plurality of blocks, and outputs each block to subtractor 104. For example,
`
`splitter 102 first splits a picture into blocks of a fixed size (for example,
`
`128x128). Other fixed block sizes may be employed. The fixed-size block is
`
`10
`
`also referred to as a coding tree unit (CTU). Splitter 102 then splits each
`
`fixed-size block into blocks of variable sizes (for example, 64x64 or smaller),
`
`based on recursive quadtree and/or binary tree block splitting.
`
`In other words,
`
`splitter 102 selects a splitting pattern. The variable-size block is also referred
`
`to as a coding unit (CU), a prediction unit (PU), or a transform unit (TU).
`
`Itis
`
`15
`
`to be noted that, in various kinds of processing examples, there is no need to
`
`differentiate between CU, PU, and TU;all or some of the blocks in a picture
`
`may be processed in units of a CU, a PU, or a TU.
`
`FIG. 3 is a conceptual diagram illustrating one example of block
`
`splitting according to an embodiment.
`
`In FIG. 3, the solid lines represent
`
`20
`
`block boundaries of blocks split by quadtree block splitting, and the dashed
`
`lines represent block boundaries of blocks split by binary tree block splitting.
`
`Here, block 10 is a square block having 128128 pixels (128128 block).
`
`This 128x128 block 10 is first split into four square 64x64 blocks (quadtree
`
`block splitting).
`
`25
`
`The upper-left 64x64 block is
`
`further vertically split
`
`into two
`
`rectangular 32x64 blocks, and the left 32x64 block is further vertically split
`
`into two rectangular 16x64 blocks (binary tree block splitting). As a result,
`
`19
`
`

`

`the upper-left 64x64 block is split into two 16x64 blocks 11 and 12 and one
`
`32x64 block 13.
`
`The upper-right 64x64 block is horizontally split into two rectangular
`
`64x32 blocks 14 and 15 (binarytree block splitting).
`
`The lower-left 64x64 block is first split into four square 3232 blocks
`
`(quadtree block splitting). The upper-left block and the lower-right block
`
`among the four 32x32 blocks are further split. The upper-left 32x32 block is
`
`vertically split into two rectangle 16x32 blocks, and the right 1632 block is
`
`further horizontally split into two 1616 blocks (binary tree block splitting).
`
`10
`
`The lower-right 3232 block is horizontally split into two 32x16 blocks (binary
`
`tree block splitting). As a result, the lower-left 64x64 block is split into 1632
`
`block 16, two 16X16 blocks 17 and 18, two 32x32 blocks 19 and 20, and two
`
`32x16 blocks 21 and 22.
`
`The lower-right 64x64 block 23 is not split.
`
`15
`
`As described above,
`
`in FIG.
`
`3, block 10 is split
`
`into thirteen
`
`variable-size block

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