www.uspto.gov
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`
`17/391,315
`
`08/02/2021
`
`Jing Ya LI
`
`2021-1435A
`
`3959
`
`iP
`Lind&
`Wenderoth,
`Wenderoth, Lind & Ponack, L.L.P.
`1025 Connecticut Avenue, NW
`Suite 500
`Washington, DC 20036
`
`CHIO, TAT CHI
`
`PAPER NUMBER
`
`ART UNIT
`2486
`
`NOTIFICATION DATE
`
`DELIVERY MODE
`
`12/20/2023
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
`following e-mail address(es):
`eoa@ wenderoth.com
`kmiller@wenderoth.com
`
`PTOL-90A (Rev. 04/07)
`
`

`

`Office Action Summary
`
`Application No.
`17/391,315
`Examiner
`TAT CHI CHIO
`
`Applicant(s)
`Ll etal.
`Art Unit
`2486
`
`AIA (FITF) Status
`Yes
`
`-- The MAILING DATEof this communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`A SHORTENED STATUTORYPERIOD FOR REPLYIS SET TO EXPIRE 3 MONTHS FROM THE MAILING
`DATE OF THIS COMMUNICATION.
`Extensionsof time may be available underthe provisions of 37 CFR 1.136(a). In no event, however, may a reply betimely filed after SIX (6) MONTHSfrom the mailing
`date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHSfrom the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, evenif timely filed, may reduce any earned patent term
`adjustment. See 37 CFR 1.704(b).
`
`Status
`
`
`
`1)C) Responsive to communication(s) filed on
`CA declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/werefiledon
`
`2a)C) This action is FINAL. 2b)¥)This action is non-final.
`3) An election was madeby the applicant in responseto a restriction requirement set forth during the interview
`on__; the restriction requirement and election have been incorporatedinto this action.
`4)() Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Exparte Quayle, 1935 C.D. 11, 453 O.G. 213.
`
`Disposition of Claims*
`1-20 is/are pending in the application.
`)
`Claim(s)
`5a) Of the above claim(s) 19-20 is/are withdrawn from consideration.
`) © Claim(s)__ is/are allowed.
`) 1-18 is/are rejected.
`)
`Claim(s
`() Claim(s)__ is/are objectedto.
`( Claim(s)
`are subjectto restriction and/or election requirement
`* If any claims have been determined allowable, you maybeeligible to benefit from the Patent Prosecution Highway program at a
`participating intellectual property office for the corresponding application. For more information, please see
`http:/Awww.uspto.gov/patents/init_events/pph/index.jsp or send an inquiry to PPHfeedback@uspto.gov.
`
`) )
`
`Application Papers
`10) The specification is objected to by the Examiner.
`11)0) The drawing(s) filedon__ is/are: a)C) accepted or b){) objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121(d).
`
`Priority under 35 U.S.C. § 119
`12)£) Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d)or (f).
`Certified copies:
`_—_c)L) None ofthe:
`b)L) Some**
`a)Q) All
`1.1) Certified copies of the priority documents have been received.
`2.1.) Certified copies of the priority documents have been received in Application No. |
`3.2.) Copies of the certified copies of the priority documents have been receivedin this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`*“ See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`1)
`
`Notice of References Cited (PTO-892)
`
`Information Disclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`2)
`Paper No(s)/Mail Date
`U.S. Patent and Trademark Office
`
`3)
`
`4)
`
`(LJ Interview Summary (PTO-413)
`Paper No(s)/Mail Date
`(Qj Other:
`
`PTOL-326 (Rev. 11-13)
`
`Office Action Summary
`
`Part of Paper No./Mail Date 20231205
`
`

`

`Application/Control Number: 17/391 ,315
`Art Unit: 2486
`
`Page 2
`
`DETAILED ACTION
`
`Notice of Pre-AlA or AIA Status
`
`1.
`
`The present application, filed on or after March 16, 2013, is being examined
`
`underthe first inventor to file provisions of the AIA.
`
`Election/Restrictions
`
`1.
`
`Applicant’s election without traverse of Group | (claims 1-18) in the reply filed on
`
`11/17/2023 is acknowledged.
`
`Double Patenting
`
`2.
`
`The nonstatutory double patenting rejection is based on a judicially created
`
`doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the
`
`unjustified or improper timewise extension of the “right to exclude” granted by a patent
`
`and to prevent possible harassment by multiple assignees. A nonstatutory double
`
`patenting rejection is appropriate where the conflicting claims are not identical, but at
`
`least one examined application claim is not patentably distinct from the reference
`
`claim(s) because the examined application claim is either anticipated by, or would have
`
`been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46
`
`USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed.
`
`Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum,
`
`686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619
`
`(CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
`
`A timelyfiled terminal disclaimer in compliance with 37 CFR 1.321 (c) or 1.321 (d)
`
`may be used to overcome an actualor provisional rejection based on nonstatutory
`
`double patenting provided the reference application or patent either is shown to be
`
`

`

`Application/Control Number: 17/391 ,315
`Art Unit: 2486
`
`Page 3
`
`commonly owned with the examined application, or claims an invention made as a
`
`result of activities undertaken within the scopeof a joint research agreement. See
`
`MPEP § 717.02 for applications subject to examination underthe first inventor to file
`
`provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146et seq.for
`
`applications not subject to examination underthe first inventor to file provisions of the
`
`AlA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
`
`The filing of a terminal disclaimerbyitself is not a complete reply to a
`
`nonstatutory double patenting (NSDP)rejection. A complete reply requires that the
`
`terminal disclaimer be accompanied by a reply requesting reconsideration of the prior
`
`Office action. Even where the NSDP rejection is provisional the reply must be complete.
`
`See MPEP § 804, subsection |.B.1. For a reply to a non-final Office action, see 37 CFR
`
`1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A requestfor
`
`reconsideration while not provided for in 37 CFR 1.113(c) may befiled after final for
`
`consideration. See MPEP §§ 706.07(e) and 714.13.
`
`The USPTOInternet website contains terminal disclaimer forms which may be
`
`used. Please visit www.uspto.gov/patent/patents-forms. The actualfiling date of the
`
`application in which the form is filed determines what form (e.g., PTO/SB/25,
`
`PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal
`
`Disclaimer may befilled out completely online using web-screens. An eTerminal
`
`Disclaimer that meets all requirements is auto-processed and approved immediately
`
`upon submission. For more information about eTerminal Disclaimers, refer to
`
`www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
`
`

`

`Application/Control Number: 17/391 ,315
`Art Unit: 2486
`
`Page 4
`
`3.
`
`Claims 1-18 are rejected on the ground of nonstatutory double patenting as being
`
`unpatentable over claims 1-6 of U.S. Patent No. US 11,394,968 B2 (“reference patent”).
`
`Although the claims at issue are notidentical, they are not patentably distinct from each
`
`other because
`
`Consider application claim 1, claim 1 of the reference patent discloses an
`
`encoder that encodes a current block to be encodedin an image, the encoder
`
`comprising: circuitry; and memory coupledto the circuitry, wherein in operation, the
`
`circuitry: judges whetherthe current block is a sub-block of affine mode; generates a
`
`first prediction image based on a motion vector,the first prediction image being an
`
`image with full-pel precision; generates a second prediction image using an
`
`interpolation filter by interpolating a value at a fractional-pel position betweenfull-pel
`
`positions includedin the first prediction image; and encodesthe current block based on
`
`the second prediction image, and when the current block is not the sub-block for the
`
`affine mode,the circuitry: judges whethera size of the current blockis larger than 4x4
`
`pixels; selectsafirst interpolation filter as the interpolation filter for generating the
`
`second prediction image, whenthe size of the current blockis larger than 4x4 pixels;
`
`and selects a second interpolation filter as the interpolationfilter for generating the
`
`second prediction image, when the size of the current block is not larger than 4x4
`
`pixels, when the current block is the sub-blockfor the affine mode, the circuitry selects
`
`the secondinterpolation filter as the interpolation filter for generating the second
`
`prediction image, and the secondinterpolation filter has fewer taps than the first
`
`interpolation filter.
`
`

`

`Application/Control Number: 17/391 ,315
`Art Unit: 2486
`
`Page 5
`
`Claim 1 of the reference patent disclosesall the limitations in the application
`
`claim. Thus, non-statutory double patenting applies.
`
`Consider application claim 2, claim 1 of the reference patent discloses an
`
`encoder that encodes a current block to be encodedin an image, the encoder
`
`comprising: circuitry; and memory coupled to the circuitry, wherein in operation, the
`
`circuitry: judges whetherthe current block is a sub-block of affine mode; generates a
`
`first prediction image based on a motion vector,the first prediction image being an
`
`image with full-pel precision; generates a second prediction image using an
`
`interpolation filter by interpolating a value at a fractional-pel position betweenfull-pel
`
`positions included in the first prediction image; and encodesthe current block based on
`
`the second prediction image, and when the current block is not the sub-block for the
`
`affine mode,the circuitry: judges whethera size of the current blockis larger than 4x4
`
`pixels; selectsafirst interpolation filter as the interpolation filter for generating the
`
`second prediction image, when the size of the current blockis larger than 4x4 pixels;
`
`and selects a secondinterpolation filter as the interpolationfilter for generating the
`
`second prediction image, when the size of the current block is not larger than 4x4
`
`pixels, when the current block is the sub-blockfor the affine mode, the circuitry selects
`
`the secondinterpolation filter as the interpolation filter for generating the second
`
`prediction image, and the secondinterpolation filter has fewer taps thanthe first
`
`interpolation filter.
`
`Claim 1 of the reference patent disclosesall the limitations in the application
`
`claim. Thus, non-statutory double patenting applies.
`
`

`

`Application/Control Number: 17/391 ,315
`Art Unit: 2486
`
`Page 6
`
`Consider application claim 3, claim 1 of the reference patent discloses an
`
`encoder that encodes a current block to be encodedin an image, the encoder
`
`comprising: circuitry; and memory coupled to the circuitry, wherein in operation, the
`
`circuitry: judges whetherthe current block is a sub-block of affine mode; generates a
`
`first prediction image based on a motion vector,the first prediction image being an
`
`image with full-pel precision; generates a second prediction image using an
`
`interpolation filter by interpolating a value at a fractional-pel position betweenfull-pel
`
`positions included in the first prediction image; and encodesthe current block based on
`
`the second prediction image, and when the current block is not the sub-block for the
`
`affine mode,the circuitry: judges whethera size of the current blockis larger than 4x4
`
`pixels; selectsafirst interpolation filter as the interpolation filter for generating the
`
`second prediction image, whenthe size of the current blockis larger than 4x4 pixels;
`
`and selects a second interpolation filter as the interpolationfilter for generating the
`
`second prediction image, when the size of the current blockis not larger than 4x4
`
`pixels, when the current block is the sub-block for the affine mode, the circuitry selects
`
`the secondinterpolation filter as the interpolation filter for generating the second
`
`prediction image, and the secondinterpolation filter has fewer taps thanthe first
`
`interpolation filter.
`
`Claim 1 of the reference patent discloses all the limitations in the application
`
`claim. Thus, non-statutory double patenting applies.
`
`Consider application claim 4, claim 1 of the reference patent discloses an
`
`encoder that encodes a current block to be encodedin an image, the encoder
`
`comprising: circuitry; and memory coupled to the circuitry, wherein in operation, the
`
`

`

`Application/Control Number: 17/391 ,315
`Art Unit: 2486
`
`Page 7
`
`circuitry: judges whetherthe current block is a sub-block of affine mode; generates a
`
`first prediction image based on a motion vector,the first prediction image being an
`
`image with full-pel precision; generates a second prediction image using an
`
`interpolation filter by interpolating a value at a fractional-pel position betweenfull-pel
`
`positions included in the first prediction image; and encodes the current block based on
`
`the second prediction image, and when the current block is not the sub-block for the
`
`affine mode,the circuitry: judges whether a size of the current blockis larger than 4x4
`
`pixels; selectsafirst interpolation filter as the interpolation filter for generating the
`
`second prediction image, whenthe size of the current blockis larger than 4x4 pixels;
`
`and selects a secondinterpolation filter as the interpolationfilter for generating the
`
`second prediction image, when the size of the current blockis not larger than 4x4
`
`pixels, when the current block is the sub-blockfor the affine mode, the circuitry selects
`
`the secondinterpolation filter as the interpolation filter for generating the second
`
`prediction image, and the secondinterpolation filter has fewer taps thanthe first
`
`interpolation filter.
`
`Claim 1 of the reference patent disclosesall the limitations in the application
`
`claim. Thus, non-statutory double patenting applies.
`
`Consider application claim 5, claim 1 of the reference patent discloses an
`
`encoder that encodes a current block to be encodedin an image, the encoder
`
`comprising: circuitry; and memory coupled to the circuitry, wherein in operation, the
`
`circuitry: judges whetherthe current block is a sub-block of affine mode; generates a
`
`first prediction image based on a motion vector,the first prediction image being an
`
`image with full-pel precision; generates a second prediction image using an
`
`

`

`Application/Control Number: 17/391 ,315
`Art Unit: 2486
`
`Page 8
`
`interpolation filter by interpolating a value at a fractional-pel position betweenfull-pel
`
`positions included in the first prediction image; and encodesthe current block based on
`
`the second prediction image, and when the current block is not the sub-block for the
`
`affine mode,the circuitry: judges whether a size of the current blockis larger than 4x4
`
`pixels; selectsafirst interpolation filter as the interpolation filter for generating the
`
`second prediction image, whenthe size of the current blockis larger than 4x4 pixels;
`
`and selects a second interpolation filter as the interpolationfilter for generating the
`
`second prediction image, when the size of the current blockis not larger than 4x4
`
`pixels, when the current block is the sub-block for the affine mode, the circuitry selects
`
`the secondinterpolation filter as the interpolation filter for generating the second
`
`prediction image, and the secondinterpolation filter has fewer taps thanthe first
`
`interpolation filter.
`
`Claim 1 of the reference patent disclosesall the limitations in the application
`
`claim. Thus, non-statutory double patenting applies.
`
`Consider application claim 6, claim 2 of the reference patent disclosesthe first
`
`interpolation filter is an 8-tapfilter.
`
`Claim 2 of the reference patent disclosesall the limitations in the application
`
`claim. Thus, non-statutory double patenting applies.
`
`Consider application claim 7, claim 3 of the reference patent disclosesthe first
`
`interpolation filter is an 6-tapfilter.
`
`Claim 3 of the reference patent disclosesall the limitations in the application
`
`claim. Thus, non-statutory double patenting applies.
`
`

`

`Application/Control Number: 17/391 ,315
`Art Unit: 2486
`
`Page 9
`
`Consider application claim 8, claim 1 of the reference patent discloses an
`
`encoder that encodes a current block to be encodedin an image, the encoder
`
`comprising: circuitry; and memory coupled to the circuitry, wherein in operation, the
`
`circuitry: judges whetherthe current block is a sub-block of affine mode; generates a
`
`first prediction image based on a motion vector,the first prediction image being an
`
`image with full-pel precision; generates a second prediction image using an
`
`interpolation filter by interpolating a value at a fractional-pel position betweenfull-pel
`
`positions includedin the first prediction image; and encodesthe current block based on
`
`the second prediction image, and when the current block is not the sub-block for the
`
`affine mode,the circuitry: judges whethera size of the current blockis larger than 4x4
`
`pixels; selectsafirst interpolation filter as the interpolation filter for generating the
`
`second prediction image, when the size of the current blockis larger than 4x4 pixels;
`
`and selects a second interpolation filter as the interpolationfilter for generating the
`
`second prediction image, when the size of the current block is not larger than 4x4
`
`pixels, when the current block is the sub-blockfor the affine mode, the circuitry selects
`
`the secondinterpolation filter as the interpolation filter for generating the second
`
`prediction image, and the secondinterpolation filter has fewer taps thanthe first
`
`interpolation filter.
`
`Claim 1 of the reference patent disclosesall the limitations in the application
`
`claim. Thus, non-statutory double patenting applies.
`
`Consider application claim 9, claim 4 of the reference patent discloses A
`
`decoder that decodes a current block to be decodedin an image, the decoder
`
`comprising: circuitry; and memory coupled to the circuitry, wherein in operation, the
`
`

`

`Application/Control Number: 17/391 ,315
`Art Unit: 2486
`
`Page 10
`
`circuitry: judges whetherthe current block is a sub-block of affine mode; generates a
`
`first prediction image based on a motion vector,the first prediction image being an
`
`image with full-pel precision; generates a second prediction image using an
`
`interpolation filter by interpolating a value at a fractional-pel position betweenfull-pel
`
`positions included in the first prediction image; and decodes the current block based on
`
`the second prediction image, and when the current block is not the sub-block for the
`
`affine mode,the circuitry: judges whethera size of the current blockis larger than 4x4
`
`pixels; selectsafirst interpolation filter as the interpolation filter for generating the
`
`second prediction image, whenthe size of the current blockis larger than 4x4 pixels;
`
`and selects a secondinterpolation filter as the interpolation filter for generating the
`
`second prediction image, when the size of the current blockis not larger than 4x4
`
`pixels, when the current block is the sub-blockfor the affine mode, the circuitry selects
`
`the secondinterpolation filter as the interpolation filter for generating the second
`
`prediction image, and the secondinterpolation filter has fewer taps thanthe first
`
`interpolation filter..
`
`Claim 4 of the reference patent disclosesall the limitations in the application
`
`claim. Thus, non-statutory double patenting applies.
`
`Consider application claim 10, claim 4 of the reference patent discloses A
`
`decoder that decodes a current block to be decodedin an image, the decoder
`
`comprising: circuitry; and memory coupled to the circuitry, wherein in operation, the
`
`circuitry: judges whetherthe current block is a sub-block of affine mode; generates a
`
`first prediction image based on a motion vector,the first prediction image being an
`
`image with full-pel precision; generates a second prediction image using an
`
`

`

`Application/Control Number: 17/391 ,315
`Art Unit: 2486
`
`Page 11
`
`interpolation filter by interpolating a value at a fractional-pel position betweenfull-pel
`
`positions included in the first prediction image; and decodes the current block based on
`
`the second prediction image, and when the current block is not the sub-block for the
`
`affine mode,the circuitry: judges whethera size of the current blockis larger than 4x4
`
`pixels; selectsafirst interpolation filter as the interpolation filter for generating the
`
`second prediction image, when the size of the current blockis larger than 4x4 pixels;
`
`and selects a second interpolation filter as the interpolationfilter for generating the
`
`second prediction image, when the size of the current blockis not larger than 4x4
`
`pixels, when the current block is the sub-block for the affine mode, the circuitry selects
`
`the secondinterpolation filter as the interpolation filter for generating the second
`
`prediction image, and the secondinterpolation filter has fewer taps thanthe first
`
`interpolation filter..
`
`Claim 4 of the reference patent disclosesall the limitations in the application
`
`claim. Thus, non-statutory double patenting applies.
`
`Consider application claim 11, claim 4 of the reference patent discloses A
`
`decoder that decodes a current block to be decodedin an image, the decoder
`
`comprising: circuitry; and memory coupled to the circuitry, wherein in operation, the
`
`circuitry: judges whetherthe current block is a sub-block of affine mode; generates a
`
`first prediction image based on a motion vector,the first prediction image being an
`
`image with full-pel precision; generates a second prediction image using an
`
`interpolation filter by interpolating a value at a fractional-pel position betweenfull-pel
`
`positions included in the first prediction image; and decodes the current block based on
`
`the second prediction image, and when the current block is not the sub-block for the
`
`

`

`Application/Control Number: 17/391 ,315
`Art Unit: 2486
`
`Page 12
`
`affine mode,the circuitry: judges whethera size of the current blockis larger than 4x4
`
`pixels; selectsafirst interpolation filter as the interpolation filter for generating the
`
`second prediction image, when the size of the current blockis larger than 4x4 pixels;
`
`and selects a second interpolation filter as the interpolationfilter for generating the
`
`second prediction image, when the size of the current block is not larger than 4x4
`
`pixels, when the current block is the sub-blockfor the affine mode, the circuitry selects
`
`the secondinterpolation filter as the interpolation filter for generating the second
`
`prediction image, and the secondinterpolation filter has fewer taps thanthe first
`
`interpolation filter..
`
`Claim 4 of the reference patent disclosesall the limitations in the application
`
`claim. Thus, non-statutory double patenting applies.
`
`Consider application claim 12, claim 4 of the reference patent discloses A
`
`decoderthat decodes a current block to be decodedin an image, the decoder
`
`comprising: circuitry; and memory coupled to the circuitry, wherein in operation, the
`
`circuitry: judges whetherthe current block is a sub-block of affine mode; generates a
`
`first prediction image based on a motion vector,the first prediction image being an
`
`image with full-pel precision; generates a second prediction image using an
`
`interpolation filter by interpolating a value at a fractional-pel position betweenfull-pel
`
`positions included in the first prediction image; and decodesthe current block based on
`
`the second prediction image, and when the current block is not the sub-block for the
`
`affine mode,the circuitry: judges whethera size of the current blockis larger than 4x4
`
`pixels; selectsafirst interpolation filter as the interpolation filter for generating the
`
`second prediction image, when the size of the current blockis larger than 4x4 pixels;
`
`

`

`Application/Control Number: 17/391 ,315
`Art Unit: 2486
`
`Page 13
`
`and selects a secondinterpolation filter as the interpolationfilter for generating the
`
`second prediction image, when the size of the current blockis not larger than 4x4
`
`pixels, when the current block is the sub-blockfor the affine mode, the circuitry selects
`
`the secondinterpolation filter as the interpolation filter for generating the second
`
`prediction image, and the secondinterpolation filter has fewer taps thanthe first
`
`interpolation filter..
`
`Claim 4 of the reference patent disclosesall the limitations in the application
`
`claim. Thus, non-statutory double patenting applies.
`
`Consider application claim 13, claim 4 of the reference patent discloses A
`
`decoder that decodes a current block to be decodedin an image, the decoder
`
`comprising: circuitry; and memory coupled to the circuitry, wherein in operation, the
`
`circuitry: judges whetherthe current block is a sub-block of affine mode; generates a
`
`first prediction image based on a motion vector,the first prediction image being an
`
`image with full-pel precision; generates a second prediction image using an
`
`interpolation filter by interpolating a value at a fractional-pel position betweenfull-pel
`
`positions included in the first prediction image; and decodes the current block based on
`
`the second prediction image, and when the current block is not the sub-block for the
`
`affine mode,the circuitry: judges whethera size of the current blockis larger than 4x4
`
`pixels; selectsafirst interpolation filter as the interpolation filter for generating the
`
`second prediction image, when the size of the current blockis larger than 4x4 pixels;
`
`and selects a second interpolation filter as the interpolation filter for generating the
`
`second prediction image, when the size of the current blockis not larger than 4x4
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`pixels, when the current block is the sub-blockfor the affine mode, the circuitry selects
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`

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`Application/Control Number: 17/391 ,315
`Art Unit: 2486
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`Page 14
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`the secondinterpolation filter as the interpolation filter for generating the second
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`prediction image, and the secondinterpolation filter has fewer taps thanthe first
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`interpolation filter..
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`Claim 4 of the reference patent disclosesall the limitations in the application
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`claim. Thus, non-statutory double patenting applies.
`
`Consider application claim 14, claim 5 of the reference patent discloses the
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`first interpolation filter is an 8-tapfilter.
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`Claim 5 of the reference patentdisclosesall the limitations in the application
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`claim. Thus, non-statutory double patenting applies.
`
`Consider application claim 15, claim 6 of the reference patent discloses the
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`first interpolation filter is an 6-tapfilter.
`
`Claim 6 of the reference patentdisclosesall the limitations in the application
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`claim. Thus, non-statutory double patenting applies.
`
`Consider application claim 16, claim 4 of the reference patent discloses A
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`decoder that decodes a current block to be decodedin an image, the decoder
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`comprising: circuitry; and memory coupledto the circuitry, wherein in operation, the
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`circuitry: judges whetherthe current block is a sub-block of affine mode; generates a
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`first prediction image based on a motion vector,the first prediction image being an
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`image with full-pel precision; generates a second prediction image using an
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`interpolation filter by interpolating a value at a fractional-pel position betweenfull-pel
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`positions includedin the first prediction image; and decodes the current block based on
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`the second prediction image, and when the current block is not the sub-block for the
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`affine mode,the circuitry: judges whethera size of the current blockis larger than 4x4
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`

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`Application/Control Number: 17/391 ,315
`Art Unit: 2486
`
`Page 15
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`pixels; selectsafirst interpolation filter as the interpolation filter for generating the
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`second prediction image, when the size of the current blockis larger than 4x4 pixels;
`
`and selects a second interpolation filter as the interpolationfilter for generating the
`
`second prediction image, when the size of the current block is not larger than 4x4
`
`pixels, when the current block is the sub-blockfor the affine mode, the circuitry selects
`
`the secondinterpolation filter as the interpolation filter for generating the second
`
`prediction image, and the secondinterpolationfilter has fewer taps thanthe first
`
`interpolation filter..
`
`Claim 4 of the reference patent disclosesall the limitations in the application
`
`claim. Thus, non-statutory double patenting applies.
`
`Consider application claim 17, claim 17 recites the method implementedby the
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`encoderrecited in claim 1. Thus, it is rejected for the same reasons.
`
`Consider application claim 18, claim 18 recites the method implementedby the
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`decoderrecited in claim 9. Thus, it is rejected for the same reasons.
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`Claim Rejections - 35 USC § 103
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`2.
`
`The following is a quotation of 35 U.S.C. 103 which forms the basisfor all
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`obviousness rejections set forth in this Office action:
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`A patent for a claimed invention may not be obtained, notwithstanding that the claimed
`invention is not identically disclosed as set forth in section 102, if the differences between the
`claimed invention and the prior art are such that the claimed invention as a whole would have
`been obvious before the effectivefiling date of the claimed invention to a person having
`ordinary skill in the art to which the claimed invention pertains. Patentability shall not be
`negated by the manner in which the invention was made.
`
`3.
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`The factual inquiries for establishing a background for determining obviousness
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`under 35 U.S.C. 103 are summarized as follows:
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`Application/Control Number: 17/391 ,315
`Art Unit: 2486
`
`Page 16
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`1. Determining the scope and contentsof the prior art.
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`2. Ascertaining the differences betweenthe prior art and the claims at issue.
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`3. Resolving the level of ordinary skill in the pertinent art.
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`4. Considering objective evidence presentin the application indicating
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`obviousness or nonobviousness.
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`4.
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`Claim(s) 1-3, 6-7, 9-11, 14-15, and 17-18 is/are rejected under 35 U.S.C. 103 as
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`being unpatentable over Karczewicz et al. (US 2010/0074332 A1) in view of Piao etal.
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`(US 2020/0374562 A1).
`
`Consider claim 1, karczewicz teaches an encoder that encodesa current block
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`to be encodedin an image, the encoder comprising: circuitry ([0039]); and memory
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`coupled tothe circuitry (Fig. 1-2), wherein in operation, the circuitry: generates a
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`first prediction image having full-pel precision, based on a motion vector of the
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`current block ((0046], [0051], and Fig. 2; prediction unit; [0049] and Fig. 4; full pixels);
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`generates a second prediction image having fraction-pel precision by
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`interpolating a value at a fraction-pel position between full-pel positions included
`
`in the first prediction image ([0047] — [0052], [0060]), using a first interpolation
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`filter or a second interpolation filter (([0047], [0050], [0060], [0083] — [0085]))
`
`
`
`
`
`differing in-atotalnumberoftapsfromthefirst interpolation fitter; and encodes
`
`
`
`
`
`
`
`
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`the current block based on the second prediction image (46 of Fig. 2), and in the
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`generating of the second prediction image, the circuitry switches between using
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`the first interpolation filter and the second interpolation filter ([0047], [0050],
`
`
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`[0060], [0083] — [0085]) dependingonwhetheran_affine-modeis_usedforthe
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`currentblock.
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`

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`Application/Control Number: 17/391 ,315
`Art Unit: 2486
`
`Page 17
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`However, Karczewicz does not explicitly teach the secondinterpolation filter
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`differing in a total numberof taps from thefirst interpolation filter and switching between
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`using the first interpolation filter and the second interpolation filter depending on
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`whether an affine mode is used for the current block.
`
`Piao teaches the secondinterpolation filter differing in a