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`
`UNITEDSTATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`
`17/456,914
`
`11/30/2021
`
`Atsushi HARIKAT
`
`ISHII-65436
`
`1770
`
`PEARNE & GORDON LLP
`1801 EAST 9TH STREET
`SUITE 1200
`
`CLEVELAND,OH 44114-3108
`
`IMTTAZ, SM SOHEL
`
`2812
`
`07/25/2024
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
`following e-mail address(es):
`
`patdocket@ pearne.com
`
`PTOL-90A (Rev. 04/07)
`
`

`

`Office Action Summary
`
`Application No.
`17/456,914
`Examiner
`SMS IMTIAZ
`
`Applicant(s)
`HARIKAI et al.
`Art Unit
`2812
`
`AIA (FITF) Status
`Yes
`
`-- The MAILING DATEof this communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`A SHORTENED STATUTORYPERIOD FOR REPLYIS SET TO EXPIRE 3 MONTHS FROM THE MAILING
`DATE OF THIS COMMUNICATION.
`Extensionsof time may be available underthe provisions of 37 CFR 1.136(a). In no event, however, may a reply betimely filed after SIX (6) MONTHSfrom the mailing
`date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHSfrom the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, evenif timely filed, may reduce any earned patent term
`adjustment. See 37 CFR 1.704(b).
`
`Status
`
`
`
`1) Responsive to communication(s)filed on applicant's amendmentsfiled on 07/08/2024.
`C) A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/werefiled on
`2a)[¥) This action is FINAL.
`2b) (J This action is non-final.
`3) An election was madeby the applicant in responseto a restriction requirement set forth during the interview
`on
`; the restriction requirement and election have been incorporated into this action.
`4)(2) Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Exparte Quayle, 1935 C.D. 11, 453 O.G. 213.
`
`Disposition of Claims*
`1-5 is/are pending in the application.
`)
`Claim(s)
`5a) Of the above claim(s) _ is/are withdrawn from consideration.
`C] Claim(s)
`is/are allowed.
`Claim(s) 1-5 is/are rejected.
`(] Claim(s)__ is/are objectedto.
`C] Claim(s
`are subjectto restriction and/or election requirement
`)
`* If any claims have been determined allowable, you maybeeligible to benefit from the Patent Prosecution Highway program at a
`participating intellectual property office for the corresponding application. For more information, please see
`http://www.uspto.gov/patents/init_events/pph/index.jsp or send an inquiry to PPHfeedback@uspto.gov.
`
`) ) ) )
`
`Application Papers
`10)( The specification is objected to by the Examiner.
`11) The drawing(s) filed on 11/30/2021 is/are: a)[¥) accepted or b)() objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121(d).
`
`Priority under 35 U.S.C. § 119
`12)(¥) Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d)or (f).
`Certified copies:
`_—_c)L) None ofthe:
`b)L) Some**
`a)Y) All
`1.) Certified copies of the priority documents have been received.
`2.1.) Certified copies of the priority documents have been received in Application No. |
`3.2.) Copies of the certified copies of the priority documents have been receivedin this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`*“ See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`1)
`
`Notice of References Cited (PTO-892)
`
`2) (J Information Disclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`Paper No(s)/Mail Date
`U.S. Patent and Trademark Office
`
`3)
`
`4)
`
`(LJ Interview Summary (PTO-413)
`Paper No(s)/Mail Date
`(Qj Other:
`
`PTOL-326 (Rev. 11-13)
`
`Office Action Summary
`
`Part of Paper No./Mail Date 20240717
`
`

`

`Application/Control Number: 17/456,914
`Art Unit: 2812
`
`Page 2
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`DETAILED ACTION
`
`This office action is in responseto applicant’s amendmentsfiled on 07/08/2024.
`
`Currently claims 1-5 are pending in the application.
`
`Response to Arguments
`
`Applicant’s arguments with respect to claim 1 have been considered but are
`
`moot because the new ground of rejection does not rely on any reference applied in the
`
`prior rejection of record for any teaching or matter specifically challenged in the
`
`argument.
`
`Claim Rejections - 35 USC § 103
`
`In the event the determination of the status of the application as subject to AIA 35
`
`U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any
`
`correction of the statutory basis for the rejection will not be considered a new ground of
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`rejection if the prior art relied upon, and the rationale supporting the rejection, would be
`
`the same under either status.
`
`The following is a quotation of 35 U.S.C. 103 which forms the basis forall
`
`obviousnessrejections set forth in this Office action:
`
`A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention
`is not identically disclosed as set forth in section 102 ofthis title, if the differences between the
`claimed invention and the prior art are such that the claimed invention as a whole would have
`been obvious before the effectivefiling date of the claimed invention to a person having ordinary
`skill in the art to which the claimed invention pertains. Patentability shall not be negated by the
`manner in which the invention was made.
`
`The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966),
`
`that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are
`
`summarized asfollows:
`
`1. Determining the scope and contentsof the prior art.
`2. Ascertaining the differences between the prior art and the claims at issue.
`3. Resolving the level of ordinary skill in the pertinent art.
`
`

`

`Application/Control Number: 17/456,914
`Art Unit: 2812
`
`Page 3
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`4. Considering objective evidence present in the application indicating obviousness or
`nonobviousness.
`
`Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over US
`
`2018/0096892 A1 (Sandoh)andfurther in view of US 2018/0240678 A1 (Itou).
`
`Regarding claim 1, Sanceh discloses, an element chip manufacturing
`
`method comprising:
`
`
`
`a preparing process of preparing a substrate (WS) including a plurality of
`
`eiement regions (V1TD, as annotated on Fig. 3) and a dividing
`
`region (L, as annotated! on Fig. S} that defines the element regions
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`GWID) (Fig. 3: 0026), [0029)},
`
`the substrate QAV'S} having a first principal surface and a second orincipal
`
`-
`surface (as annotated on Fig. 3} located opposite to the first
`
`principal surface (as annotated on Fig. 3: O029),
`
`

`

`Application/Control Number: 17/456,914
`Art Unit: 2812
`
`Page 4
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`the substrate inclucing a semiconductolayer (substrate uses
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`silicon, sapphire, or gallium arsenide as a base material each of
`
`which are semiconductor layers; (026);
`
`
`
`a groave forming process (step S2: Fig. 2) of forming 4 groove (30, as
`
`annotated on Fig. G: (D032) in the dividing region (L} from thefirst
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`orincipal surface side of the substrate (VS),
`
`the groave (40} being formed hallway (ihe thickness H can be
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`considered halhvay of the semiconductor layer that made the
`
`substrate WS, [O032)) in a thickness direction of the
`
`semiconductor layer (as annotated on Fig. &: [00G2)); and
`
`Note: In MPEP 2125 (i), if is stated that Orawings and pictures can
`
`anticipate clanmis Hfthey clearly show the structure which is claimed.
`
`in re
`
`Mraz, 455 F.2d 1069, 173 USPO 25 (OCPA 1972). Furthermore, the
`
`applicant has not presented persuasive evidencein Spec.
`
`

`

`Application/Control Number: 17/456,914
`Art Unit: 2812
`
`Page 5
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`para. [0011] that the claimed groove-depth is for a particular
`
`purpose thatis critical to the overall claimed invention (i.e.
`
`the invention would not work without the specific
`
`depth). Also, the applicant has not shown that the claimed
`
`depth produce a result that was new or unexpected enough
`
`to patentably distinguish the claimed invention over the cited
`
`prior art.
`
`[
`
`adeei
`
`—
`
`{{~I
`
`
`
`Fig. 7
`
`a grinding process of grinding (step $5; Fig. 2: [G040B the substrate (WS)
`
`from the second principal surface side, to divide the substrate intc a
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`olurality of element chins (Fig. 7; [O040)),
`
`Bul Sandoh fails to teach explicitly, wherein the groove formed in the groove
`
`forming pracess includes a first region cansittuted by a side surface
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`navirig a first surface roughness, arid a second region consiiuted by a
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`

`

`Application/Control Number: 17/456,914
`Art Unit: 2812
`
`Page 6
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`side surface having a second surface roughness larger than thefirst
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`surlase roughness in the semiconductor layer; in the grinding process,
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`qrinciing of the substrate is performed unti reaching the first region of the
`
`groove;
`
`However, in analogous art, fou discloses, wherein the groove (as annotaied
`
`on Fig. SB) formed in ihe groove farming process inclucies a first region
`
`fas annotated on Fig. SB} cansttiuled by 4 side surface having a first
`
`surface roughness (with scaliog S71; Fig. 3A}, and a second region (as
`
`anndtated on Fig. SB} canshtuted by a side surface havirig a second
`
`surface roughness (with scaliop O2: Fig. SB) larger than the first surface
`
`roughness ($4) in the semiconductor layer dayer iz is a semiconductor
`
`layer: (0023}) (Fig. $B: [0051] - (GOSS):
`
`

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`Application/Control Number: 17/456,914
`Art Unit: 2812
`
`Page 7
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`Therefore, it would have been obvious to one of ordinary skill in the art before the
`
`effective filing date of the claimed invention, having the teachings of Sandoh and Itou
`
`before him/her, to modify the teachings of an element chip manufacturing method with
`
`grooves in the dividing region as taught by Sandoh andto include the teachingsof
`
`grooveswith two regions with two different surface roughnesses as taught by iiou since
`
`in MPEP 2148(I) (A), it is stated that Combining prior art elements according to known methods to
`
`yield predictable results is obvious. The line of separation between these two different
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`roughnessregions can be used as a stopping point of the subsequent grinding process.
`
`Absent this important teaching in Sandoh, a person with ordinary skill in the art would
`
`be motivated to reach out to Itou while using an element chin manufacturing methad of
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`Sandoh.
`
`With the teaching of ltou, regarding the higher surface roughness in the second
`
`region, itis well within the purview of a person with ordinary skill in the art,
`
`to perform the grinding of the substrate until reaching the first region of the
`
`groove so that the remaining portion haverelatively lower surface
`
`roughness(Fig. 7; [0040)).
`
`Regarding claim 2, the combination of Sandoh and Hou discloses, the
`
`element chip manufacturing method according to claim 1, wherein the
`
`groove forming processincludes:
`
`

`

`Application/Control Number: 17/456,914
`Art Unit: 2812
`
`Page 8
`
`Fig. 3B
`
`groave
`
`\
`
`a first plasma processing processof trenching the substrate by
`
`continuously etching the substrate, to form the first region (Fig. 3A; [0058];
`
`ltou Reference); and
`
`a second plasma processing process of trenching the substrate by
`
`repeating an etching step of etching the substrate, a depositing
`
`step of depositing a protection film, and a protection film removing
`
`step of removing at least a portion of the protection film, to form the
`
`second region (Fig. 3B; [0071] — [0073]; Itou Reference).
`
`Regarding claim 3, the combination of Sandoh and Nou disclases, the
`
`element chip manufacturing method according to claim 2, wherein the
`
`groove forming processis started from the first plasma processing
`
`process (Fig. 3A; [0058]; Itou Reference).
`
`

`

`Application/Control Number: 17/456,914
`Art Unit: 2812
`
`Page 9
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`Regarding claim 4, the combination of SandohandItou discloses,the
`
`element chip manufacturing method according to claim 2, wherein, in the
`
`groove forming process, the first plasma processing process and the
`
`subsequent second plasma processing processare performedlast (Figs.
`
`3A and 3B; [0058], [0071] — [0073]; Itou Reference), and, in the grinding
`
`process, grinding of the substrate is performed until reaching the first
`
`region of the groove (Fig. 7; [0040]; Sandoh Reference and rationale in
`
`Claim 1), the first region having been formedin thefirst plasma processing
`
`process performedlast (Fig. 3A; [0058]; Itou Reference).
`
`Note: The examiner notes that in MPEP 2144.04 (IV) (C), it is stated that
`
`selection of any order of performing process steps is prima facie obviousin the
`
`absence of new or unexpected results; in re Burhans, 154 F.2d 690, 69 USPQ 330
`
`(CCPA 1946).
`
`Regarding claim 5, the combination of SandohandItou discloses,the
`
`element chip manufacturing method according to claim 2, wherein, in the
`
`groove forming process, the first plasma processing process is performed
`
`last (Figs. 3A and 3B; [0058], [0071] — [0073]; Itou Reference), and, in the
`
`grinding process, grinding of the substrate is performed until reaching the
`
`first region of the groove (Fig. 7; [0040]; Sandoh Reference and rationale
`
`in Claim 1), the first region having been formedin the first plasma
`
`processing process performed last (Fig. 3A; [0058]; ltou Reference).
`
`Note: The examiner notes that in MPEP 2144.04 (IV) (C), it is stated that
`
`selection of any order of performing process steps is prima facie obviousin the
`
`absence of new or unexpected results; in re Burhans, 154 F.2d 690, 69 USPQ 330
`
`(CCPA 1946).
`
`

`

`Application/Control Number: 17/456,914
`Art Unit: 2812
`
`Page 10
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`Examiner’s Note
`
`The examiner included a few prior arts which were not usedin the rejection but
`
`are relevant to the disclosure.
`
`1. US 2019/0074185 (Karasaki) — A method of manufacturing an elementchip
`
`is disclosed that can suppressresidual debris in plasma dicing. A back
`
`surface of a semiconductor wafer is held on a dicing tape. Then, a surface of
`
`the wafer is coated with a mask that includes a water-insoluble lower mask
`
`and a water-soluble upper mask. Subsequently, an opening is formed in the
`
`mask byirradiating the mask with laser light to expose a dividing region.
`
`Then, the semiconductor wafer is caused to comeinto contact with water to
`
`remove the upper mask covering each of the element regions while leaving
`
`the lower layer. After that, the wafer is exposed to plasma to perform etching
`
`on the dividing region exposed from the opening until the etching reaches the
`
`back surface, thereby dicing the semiconductor wafer into a plurality of
`
`element chips. Thereafter, the lower layer mask left on the front surface of the
`
`semiconductor chips is removed.
`
`US 2018/0233395 A1 (Okita) - A method of manufacturing a semiconductor
`
`chip is disclosed that includes: preparing a semiconductor wafer; forming a
`
`mask on a front surface of the semiconductor wafer so as to cover each of the
`
`element regions and to expose the dividing region; exposing the front surface
`
`to plasma in a state where a back surface of the semiconductor wafer is held
`
`with a dicing tape to dice the semiconductor wafer into a plurality of
`
`semiconductor chips by etching the dividing region exposed from the mask up
`
`

`

`Application/Control Number: 17/456,914
`Art Unit: 2812
`
`Page 11
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`to the back surface while protecting each of the element regions with the
`
`mask from plasma; and removing the mask from the front surface together
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`with an adhesive tape by peeling off the adhesive tape after sticking the
`
`adhesive tape to the side of the front surface.
`
`3. US 2017/0229365 A1 (Harikai) - In a plasma processing step that is used in
`
`the method of manufacturing the element chip for manufacturing a plurality of
`
`element chips by dividing a substrate having a plurality of element regions,
`
`the substrate is divided into element chips by exposing the substrate to a first
`
`plasma. Therefore, element chips having a first surface, a second surface,
`
`and a side surface connecting the first surface and the second surface are
`
`held spaced from each other on a carrier. A protection film covering the
`
`element chip is formed only on the side surface andit is possible to suppress
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`creep-up of a conductive material to the side surface in the mounting step by
`
`exposing the element chips to second plasma in which a mixed gasof
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`fluorocarbon and helium is used as a raw material gas.
`
`

`

`Application/Control Number: 17/456,914
`Art Unit: 2812
`
`Page 12
`
`Conclusion
`
`Applicant's amendment necessitated the new ground(s) of rejection presented in
`
`this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP
`
`§ 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37
`
`CFR 1.136(a).
`
`A shortened statutory period for reply to this final action is set to expire THREE
`
`MONTHS from the mailing date of this action.
`
`In the eventa first replyis filed within
`
`TWO MONTHS of the mailing date of this final action and the advisory action is not
`
`mailed until after the end of the THREE-MONTHshortenedstatutory period, then the
`
`shortened statutory period will expire on the date the advisory action is mailed, and any
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`extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of
`
`the advisory action.
`
`In no event, however, will the statutory period for reply expire later
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`than SIX MONTHS from the date of this final action.
`
`Anyinquiry concerning this communication or earlier communications from the
`
`examiner should be directed to S M SOHEL IMTIAZ whosetelephone numberis (408)
`
`918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
`
`If attempts to reach the examiner by telephone are unsuccessful, the examiner’s
`
`supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone
`
`number for the organization wherethis application or proceeding is assigned is 571-
`
`273-8300.
`
`

`

`Application/Control Number: 17/456,914
`Art Unit: 2812
`
`Page 13
`
`Information regarding the status of an application may be obtained from the
`
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`
`published applications may be obtained from either Private PAIR or Public PAIR.
`
`Status information for unpublished applications is available through Private PAIR only.
`
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`
`/S M SOHEL IMTIAZ/
`Primary Patent Examiner
`Art Unit 2812
`07/18/2024
`
`