`gee=tiex
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`FIRST NAMED INVENTOR
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`ATTORNEY DOCKET NO.
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`CONFIRMATIONNO.
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`17/664,426
`
`05/23/2022
`
`KAZUKO NISHIMURA
`
`083710-3691
`
`6896
`
`TITLE OF INVENTION: IMAGING DEVICE
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`CONFIRMATIONNO.
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`17/664,426
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`05/23/2022
`
`KAZUKO NISHIMURA
`
`083710-3691
`
`6896
`
`TITLE OF INVENTION: IMAGING DEVICE
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`FIRST NAMED INVENTOR
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`ATTORNEY DOCKET NO.
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`CONFIRMATIONNO.
`
`17/664,426
`
`05/23/2022
`
`KAZUKO NISHIMURA
`
`083710-3691
`
`6896
`
`McDermott Will and Emery LLP
`The McDermott Building
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`CAMARGO,MARLYS.B.
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`

`

`.
`
`.
`
`17/664,426
`
`NISHIMURAetal.
`
`MARLY S CAMARGO
`
`2697
`
`Yes
`
`-- The MAILING DATEof this communication appears on the cover sheet with the correspondence address--
`All claims being allowable, PROSECUTION ON THE MERITSIS (OR REMAINS) CLOSED in this application. If not included
`herewith (or previously mailed), a Notice of Allowance (PTOL-85) or other appropriate communication will be mailed in due course. THIS
`NOTICE OF ALLOWABILITY IS NOT A GRANTOF PATENTRIGHTS.This application is subject to withdrawal from issue at the initiative
`of the Office or upon petition by the applicant. See 37 CFR 1.313 and MPEP 1308.
`1.4] This communication is responsiveto application filed on 05/23/2022.
`(J A declaration(s)/affidavit(s}) under 37 CFR 1.130(b) was/werefiled on
`
`.
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`2._) Anelection was madeby the applicant in responseto a restriction requirement set forth during the interview on
`restriction requirement and election have been incorporatedinto this action.
`
`; the
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`3.{¥) The allowed claim(s) is/are 1-14 . As a result of the allowed claim(s), you maybeeligible to benefit from the Patent Prosecution
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`* Certified copies not received:
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`5.) CORRECTED DRAWINGS (as "replacement sheets") must be submitted.
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`Paper No./Mail Date
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`6.LJ DEPOSIT OFand/or INFORMATION aboutthe deposit of BIOLOGICAL MATERIAL must be submitted. Note the
`attached Examiner's comment regarding REQUIREMENT FOR THE DEPOSIT OF BIOLOGICAL MATERIAL.
`
`4[¥] Acknowledgmentis made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
`Certified copies:
`c) () Noneofthe:
`a) MAI
`b) (] Some*
`1.
`Certified copies of the priority documents have been received.
`2. (J Certified copies of the priority documents have been received in Application No.
`3. (J Copiesof the certified copies of the priority documents have been receivedin this national stage application from the
`International Bureau (PCT Rule 17.2(a)).
`
`Primary Examiner, Art Unit 2697
`
`Attachment(s)
`1.[¥] Notice of References Cited (PTO-892)
`2.[¥] Information Disclosure Statements (PTO/SB/08),
`Paper No./Mail Date
`.
`3.) Examiner's Comment Regarding Requirementfor Deposit
`of Biological Material
`4.C] Interview Summary (PTO-413),
`Paper No./Mail Date.
`IMARLY S CAMARGO/
`
`5. (2 Examiner's Amendment/Comment
`6.
`Examiner's Statement of Reasons for Allowance
`
`7. CL Other
`
`.
`
`U.S. Patent and Trademark Office
`PTOL-37 (Rev. 08-13)
`
`Notice of Allowability
`
`.
`Part of Paper No./Mail Date 20230122
`
`

`

`Application/Control Number: 17/664,426
`Art Unit: 2697
`
`Page 2
`
`Notice of Pre-AlA or AIA Status
`
`The present application, filed on or after March 16, 2013, is being examined
`
`under the first inventor to file provisions of the AIA.
`
`Changein Art Unit Designation for Your Application
`
`1.
`
`The Art Unit designation of your application in the USPTO has changed from
`
`2699 to 2697. The examiner assigned to this application remains the same. To aid in
`
`correlating any papers for this application, all further correspondence regarding this
`
`application should be directed to Art Unit 2697.
`
`DETAILED ACTION
`
`2.
`
`This is the initial Office Action based on the application filed on May 13, 2022. The
`
`Examiner acknowledges the following:
`
`3.
`
`4.
`
`5.
`
`Claims 1 — 14 werefiled.
`
`The drawings filed on 05/23/2022 are accepted by the Examiner.
`
`Currently claims
`
`1
`
`-— 14 are pending and they are being considered for
`
`examination.
`
`Information Disclosure Statement
`The IDS documentfiled on 05/23/2022 is acknowledged by the Examiner.
`
`6.
`
`Priority
`
`7.
`
`Acknowledgment
`
`is made of applicant’s claimed priority based on the PCT
`
`application PCT/JP2020/040233 of 10/27/2020, which is based on a Japanese patent
`
`

`

`Application/Control Number: 17/664,426
`Art Unit: 2697
`
`Page 3
`
`application JP 2019-231609, indicating the foreign priority date as December 23, 2019.
`
`Certified copies were filed/mailed to the office on 06/28/2022.
`
`Allowable Subject Matter
`
`Claims 1 — 14 are allowed.
`
`The following is an examiner's statement of
`
`reasons for allowance: The
`
`8.
`
`9.
`
`prior/related art of record teaches,
`
`An imaging device (Yanagida — US 2019/0149756 A1), comprising pixel cells
`
`arranged in a matrix having rows and columns, the pixel cells including first pixel cells
`
`and second pixel cells different from the first pixel cells, the first pixel cells and the second
`
`pixel cells being located in one of the columns, each of the pixel cells comprising: a
`
`photoelectric converter that converts incident light into signal charge, a first transistor
`
`having a first gate, a first source andafirst drain, the first gate being coupled to the
`
`photoelectric converter, and a second transistor having a second gate, a second source
`
`and a second drain, either the first source or the first drain being configured to electrically
`
`couple to the photoelectric converter via the second transistor; a first line coupled to one
`
`of the first source and the first drain of each of the first pixel cells; and a second line
`
`coupled to one ofthe first source and the first drain of each of the second pixel cells, the
`
`second line being different from the first line and, further comprising: voltage switching
`
`circuitry that is coupled to the other of the first source and the first drain of each of the
`
`first pixel cells and that is coupled to the other of the first source and the first drain of each
`
`of the second pixel cells, the voltage switching circuitry being configured to switch voltage
`
`supply to the other of the first source and the first drain of each of the first pixel cells
`
`

`

`Application/Control Number: 17/664,426
`Art Unit: 2697
`
`Page 4
`
`between a first voltage and a second voltage different from the first voltage, the voltage
`
`switching circuitry being configured to switch voltage supply to the other of the first source
`
`and the first drain of each of the second pixel cells between the first voltage and the
`
`second voltage. Yanagida teaches some features of the instant invention such as an
`
`imaging device comprising pixel cells arranged in a matrix in rows and columns, wherein
`
`each pixel cell includes a photodiode to convert imping light into a signal charge, a first
`
`transistor having a first gate, a first source and a first drain and the first gate being coupled
`
`to the photodiode, a second source and drain; a voltage switching circuitry coupled to the
`
`other pf the first source and the first drain of each of the pixel cells; the voltage switching
`
`circuitry being configured to switch voltage supply to the other of the first source and the
`
`first drain of each of the second pixel cells between the first voltage and the second
`
`voltage; however,
`
`it fails to tech or to fairly suggest the features disclosed in the
`
`independent claims 1 and 6 such as a Current supply that supplies a current to s first node
`
`between the amplification transistor and the feedback transistor; and a first select
`
`transistor of which one of the source or a drain is connected to the other of source or the
`
`drain of the amplification transistor; a second select transistor of which one of a source
`
`or a drain is connected to the one of the source or drain of the amplification transistor as
`
`in claims 1 and 6 or a second voltage supply circuit connected to the other of the source
`
`or the drain of the second select transistor as in claim 1.
`
`Another prior/related art
`
`teaches
`
`an imaging device
`
`(Nishimura
`
`-— US
`
`2016/0190187 Ai — art from the IDS) comprising a unit pixel cell comprising: a
`
`photoelectric converter that generates an electric signal through photoelectric conversion
`
`of incident light; and a signal detection circuit that detects the electric signal, the signal
`
`

`

`Application/Control Number: 17/664,426
`Art Unit: 2697
`
`Page 5
`
`detection circuit comprising a first transistor that amplifies the electric signal, a second
`
`transistor that selectively transmits output of the first transistor to outside of the unit pixel
`
`cell, and a feedbackcircuit that forms a feedback loop through which the electric signal
`
`is negatively fed back, the feedbackloop passing through the first transistor, the feedback
`
`circuit comprising a third transistor provided on the feedback loop, a gate of the third
`
`transistor being connected to a voltage control circuit that outputs at least three voltages
`
`different from each other, wherein the first transistor is provided on the feedback loop
`
`and, further comprising a constant current source provided on an output side ofthe first
`
`transistor. Nishimura teaches an imaging device with a pixel cell including a photodiode,
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`a signal detection circuit that detects the electric signal from the photodiode, withafirst
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`and a secondtransistors and a feedbackcircuit that forms feedback loop through which
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`the electric signal is negatively fed back; however,it fails to teach or to fairly suggest
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`similar limitations as discussed for Yanagida art.
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`The prior/related art also teaches an imaging device (Yamada — US 2019/0238768
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`Ai — art from the IDS) comprising: a photoelectric converter that converts light into an
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`electric charge; a transfer transistor; a charge accumulation node coupled to the
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`photoelectric converter via the transfer transistor; a first signal detection transistor having
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`a gate coupled to the charge accumulation node; a first reset transistor one of a source
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`and a drain of which is coupled to the charge accumulation node; and a secondreset
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`transistor one of a source and a drain of which is coupled to the photoelectric converter,
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`wherein one of a source and a drain of the first signal detection transistor is coupled to
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`the other of the source and the drain of the first reset transistor and the other of the source
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`and drain of the second reset transistor and further comprising: a feedbacktransistor
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`

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`Application/Control Number: 17/664,426
`Art Unit: 2697
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`Page 6
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`coupled between the one of the source and the drain of the first signal detection transistor
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`and the other of the source and drain ofthe first reset transistor; a first capacitor having
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`a first end and a second end, the first end being coupled to the charge accumulation
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`node, the second end being coupled to the other of the source and drain ofthe first reset
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`transistor; and a second capacitor having a third end and a fourth end, the third end being
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`coupled to a node between the first reset transistor and the feedbacktransistor. Yamada
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`teaches an imaging device including a photodiode; a transfer transistor; a charge
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`accumulation node coupled to the photodiode; a first signal detection transistor; a first
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`reset transistor and a second resettransistor and further including a feedback transistor
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`coupled between the one of a sourceor drain of the first signal detection transistor and
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`the other of the source or drain of the first reset transistor; a first capacitor havingafirst
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`end and a second end, the first end being coupled to the charge accumulation node, the
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`second end being coupledto the other of the source and drain ofthe first reset transistor;
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`however, it fails to teach or to suggestsimilarlimitations as discussed above for Yanagida
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`art.
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`In summary, the prior/related art teaches an imaging device comprising pixel cells
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`arranged in a matrix in rows and columns, wherein each pixel cell includes a photodiode
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`to convert imping light into a signal charge, a first transistor havingafirst gate,afirst
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`source andafirst drain and the first gate being coupled to the photodiode, a second
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`source and drain; a voltage switching circuitry coupled to the other pf the first source and
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`the first drain of each of the pixel cells; the voltage switching circuitry being configured to
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`switch voltage supply to the other of the first source and the first drain of each of the
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`second pixel cells between the first voltage and the second voltage or an imaging device
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`

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`Application/Control Number: 17/664,426
`Art Unit: 2697
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`Page 7
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`with a pixel cell including a photodiode, a signal detection circuit that detects the electric
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`signal from the photodiode, with a first and a second transistors and a feedbackcircuit
`
`that forms feedback loop through which the electric signal is negatively fed back or an
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`imaging device including a photodiode; a transfer transistor; a charge accumulation node
`
`coupled to the photodiode; a first signal detection transistor; a first reset transistor and a
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`second resettransistor and further including a feedbacktransistor coupled between the
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`one of a source or drain ofthe first signal detection transistor and the other of the source
`
`or drain of the first reset transistor; a first capacitor having a first end and a second end,
`
`the first end being coupled to the charge accumulation node, the second end being
`
`coupled to the other of the source and drain ofthe first reset transistor; however, each
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`one either alone or in combination fails to teach or to fairly suggest the combination of
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`limitations as disclosed in the independent claims 1 and 6, asit follows below.
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`Regarding Claim 1:
`
`Yanagida combined with Nishimura and Yamada teach an imaging device
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`comprising pixel cells arranged in a matrix in rows and columns, wherein each pixel cell
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`includes a photodiode to convert imping light into a signal charge, a first transistor having
`
`a first gate, a first source andafirst drain and the first gate being coupled to the
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`photodiode, a second source and drain; a voltage switching circuitry coupled to the other
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`pf the first source and the first drain of each of the pixel cells; the voltage switching
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`circuitry being configured to switch voltage supply to the other of the first source and the
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`first drain of each of the second pixel cells between the first voltage and the second
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`voltage or an imaging device with a pixel cell including a photodiode, a signal detection
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`Application/Control Number: 17/664,426
`Art Unit: 2697
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`Page 8
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`circuit that detects the electric signal from the photodiode, with a first and a second
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`transistors and a feedbackcircuit that forms feedback loop through which the electric
`
`signal is negatively fed back or an imaging device including a photodiode; a transfer
`
`transistor; a charge accumulation node coupled to the photodiode; a first signal detection
`
`transistor; a first reset transistor and a second reset transistor and further including a
`
`feedback transistor coupled between the one of a source or drain of the first signal
`
`detection transistor and the other of the source or drain of the first reset transistor;afirst
`
`capacitor having a first end and a second end, the first end being coupled to the charge
`
`accumulation node, the second end being coupledto the other of the source and drain of
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`the first reset transistor; however, either alone or in combination, they fail to teach or to
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`fairly suggest the combination oflimitations as disclosed in claim 1, mainly the underlined
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`portions.
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`The combination of Yanagida with Nishimura and Yamadafail to explicitly disclose
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`“An imaging device comprising: a pixel including: a photoelectric converter that converts
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`light into a signal charge; a charge accumulator that accumulates the signal charge; an
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`amplification transistor having a gate connected to the charge accumulator; a feedback
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`transistor of which one of a source or a drain is electrically connected to the charge
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`accumulator and the other of the source or the drain is connected to one of a source ora
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`drain of the amplification transistor; a current supply that supplies a currentto a first node
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`between the amplification transistor and_the feedback transistor; and_a_first select
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`transistor of which one of a source or a drain is connected to the other of the source or
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`the drain of the amplification transistor; a second select transistor of which one of a source
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`or a drain is connected to the one of the source or the drain of the amplification transistor;
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`

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`Application/Control Number: 17/664,426
`Art Unit: 2697
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`Page 9
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`a current source/voltage source switching circuit that includes a current source an