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`UNITEDSTATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`
`17/806,367
`
`06/10/2022
`
`Shogo OKITA
`
`ISHII-66340
`
`1199
`
`PEARNE & GORDON LLP
`1801 EAST 9TH STREET
`SUITE 1200
`
`CLEVELAND,OH 44114-3108
`
`LU, IONG-PING
`
`1713
`
`06/21/2024
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
`following e-mail address(es):
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`patdocket@ pearne.com
`
`PTOL-90A (Rev. 04/07)
`
`

`

`
`
`Disposition of Claims*
`1-4 is/are pending in the application.
`)
`Claim(s)
`5a) Of the above claim(s) _ is/are withdrawn from consideration.
`C) Claim(s)
`is/are allowed.
`Claim(s) 1-4 is/are rejected.
`(] Claim(s)__ is/are objectedto.
`C] Claim(s
`are subjectto restriction and/or election requirement
`)
`* If any claims have been determined allowable, you maybeeligible to benefit from the Patent Prosecution Highway program at a
`participating intellectual property office for the corresponding application. For more information, please see
`http://www.uspto.gov/patents/init_events/pph/index.jsp or send an inquiry to PPHfeedback@uspto.gov.
`
`) ) ) )
`
`Application Papers
`10)( The specification is objected to by the Examiner.
`11) The drawing(s)filed on 6/10/2022 is/are:
`a)[(¥) accepted or b)() objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121(d).
`
`Priority under 35 U.S.C. § 119
`12)(¥) Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d)or (f).
`Certified copies:
`_—_c)L) None ofthe:
`b)L) Some**
`a)Y) All
`1.) Certified copies of the priority documents have been received.
`2.1.) Certified copies of the priority documents have been received in Application No. |
`3.2.) Copies of the certified copies of the priority documents have been receivedin this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`*“ See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`1)
`
`Notice of References Cited (PTO-892)
`
`Information Disclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`2)
`Paper No(s)/Mail Date 6/10/2022.
`U.S. Patent and Trademark Office
`
`3)
`
`4)
`
`(LJ Interview Summary (PTO-413)
`Paper No(s)/Mail Date
`(Qj Other:
`
`PTOL-326 (Rev. 11-13)
`
`Office Action Summary
`
`Part of Paper No./Mail Date 20240615
`
`Application No.
`Applicant(s)
`17/806,367
`OKITA et al.
`
`Office Action Summary Art Unit|AIA (FITF)StatusExaminer
`JIONG-PING LU
`1713
`Yes
`
`
`
`-- The MAILING DATEof this communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`A SHORTENED STATUTORYPERIOD FOR REPLYIS SET TO EXPIRE 3 MONTHS FROM THE MAILING
`DATE OF THIS COMMUNICATION.
`Extensionsof time may be available underthe provisions of 37 CFR 1.136(a). In no event, however, may a reply betimely filed after SIX (6) MONTHSfrom the mailing
`date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHSfrom the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, evenif timely filed, may reduce any earned patent term
`adjustment. See 37 CFR 1.704(b).
`
`Status
`
`1) Responsive to communication(s) filed on 6/10/2022.
`C} A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/werefiled on
`
`2a)() This action is FINAL. 2b)¥)This action is non-final.
`3) An election was madeby the applicant in responseto a restriction requirement set forth during the interview
`on
`; the restriction requirement and election have been incorporated into this action.
`4)(2) Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Exparte Quayle, 1935 C.D. 11, 453 O.G. 213.
`
`

`

`Application/Control Number: 17/806,367
`Art Unit: 1713
`
`Page 2
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`DETAILED ACTION
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`Notice of Pre-AlA or AIA Status
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`The present application, filed on or after March 16, 2013,
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`is being examined
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`underthefirst inventor to file provisions of the AIA.
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`In the event the determination of the status of the application as subject to AIA 35
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`U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any
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`correction of the statutory basis for the rejection will not be considered a new ground of
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`rejection if the prior art relied upon, and the rationale supporting the rejection, would be
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`the same under either status.
`
`Claim Rejections - 35 USC § 102
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`1.
`
`The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that
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`form the basis for the rejections under this section madein this Office Action:
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`A person shall be entitled to a patent unless —
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`(a)(1) the claimed invention waspatented, described in a printed publication, orin public use,
`on sale or otherwise available to the public before the effective filing date of the claimed
`invention.
`
`2.
`
`Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park
`
`et al. (US20190279902).
`
`Regarding claim 1, Park discloses an element chip manufacturing method
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`(abstract), comprising: a step of preparing a substrate including a semiconductor layer
`
`havingafirst principal surface and a second principal surface and a wiring layer formed
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`on the semiconductor layer on thefirst principal surface side, the substrate having a
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`plurality of element regions and a dicing region defining the element regions (paragraph
`
`

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`Application/Control Number: 17/806,367
`Art Unit: 1713
`
`Page 3
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`0029 and Fig. 2A); alaser grooving step ofirradiating a laser beam from thefirst
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`principal surface side to the wiring layer at the dicing region, to form an aperture
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`exposing the semiconductor layer in the dicing region (paragraph 0036 and Fig. 2B);
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`and anindividualization step of etching the semiconductor layer exposed from the
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`aperture, with plasma, until reaching the second principal surface, to divide the
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`substrate into a plurality of element chips having the element regions (paragraphs 0058-
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`-59 and Fig. 2C), the laser grooving step including a groove forming step of irradiating a
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`first laser beam, to form a first groove exposing the semiconductorlayerin the dicing
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`region, and a widening step ofirradiating a second laser beam, with a beam center
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`positioned outside a side wall in a width direction of the first groove formedin the
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`groove forming step, to widenthefirst groove into the aperture (paragraphs 0037 and
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`0039; Fig. 4).
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`Regarding claim 2, Park discloses wherein the groove forming step includes a
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`step ofirradiating a third laser beam with a beam center positioned at an edge portion of
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`the dicing region, to form a second grooveas part of the first groove, and a step of
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`irradiating a fourth laser beam with a beam center positioned inside from the edge
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`portion of the dicing region, to expose the semiconductor layer on a side inner than the
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`edge portion, so that the first groove is formed (paragraphs 0037 and 0039; Fig. 4).
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`Regarding claim 3, Park discloses wherein in the widening step, the beam center
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`of the second laser beam is positioned away from the side wall by more than *% of a
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`beam diameter of the second laser beam (paragraph 0042 and Fig. 4B).
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`Regarding claim 4, Park discloses a substrate processing method for forming an
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`aperture at a predetermined region on a substrate including a semiconductor layer
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`

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`Application/Control Number: 17/806,367
`Art Unit: 1713
`
`Page 4
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`having a first principal surface and a second principal surface and a wiring layer formed
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`on the semiconductor layeron thefirst principal surface side, the aperture being formed
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`to expose the semiconductor layer (abstract and Fig. 2), the method comprising: an
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`irradiation step of irradiating a laser beam from thefirst principal surface side to the
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`wiring layer at the predetermined region (paragraph 0036 and Fig. 2B); the irradiation
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`step including a groove forming step ofirradiating a first laser beam, to formafirst
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`groove exposing the semiconductor layer in the predetermined region, and a widening
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`step ofirradiating a second laser beam, with a beam center positioned outside a side
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`wall in a width direction of the first groove formed in the groove forming step, to widen
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`the first groove into the aperture (paragraphs 0037 and 0039; Fig. 4).
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`Conclusion
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`Anyinquiry concerning this communication or earlier communications from the
`
`examiner should be directed to JJIONG-PING LU whose telephone numberis (571) 270-
`
`1135. The examiner can normally be reached on M-F: 9:00am — 5:00pm. If attempts to
`
`reach the examiner by telephone are unsuccessful,
`
`the examiner's supervisor, Joshua L
`
`Allen, can be reached at telephone number (571)270-3176. The fax phone numberfor
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`the organization where this application or proceeding is assigned is 571-273-8300.
`
`Information regarding the status of an application may be obtained from Patent
`
`Center. Status information for published applications may be obtained from Patent
`
`Center. Status information for unpublished applications is available through Patent
`
`Center for authorized users only. Should you have questions about accessto Patent
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`Center, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
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`

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`Application/Control Number: 17/806,367
`Art Unit: 1713
`
`Page 5
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`Examinerinterviews are available via telephone,
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`in-person, and video
`
`conferencing using a USPTO supplied web-based collaboration tool. To schedule an
`
`interview, applicant is encouraged to use the USPTO AutomatedInterview Request
`
`(AIR) Form at https:/Awww.uspto.gov/patents/uspto-automated-
`
`interview-request-air-
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`form.
`
`/JIONG-PING LU/
`Primary Examiner, Art Unit 1713
`
`