www.uspto.gov
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`
`17/840, 167
`
`06/14/2022
`
`Kentaro NAKANISHI
`
`070469-1206
`
`3066
`
`Rimon PC - Panasonic Corporation
`8300 Greensboro Dr
`Suite 500
`
`FORTIN, RYAN TIMOTHY
`
`4156
`
`08/22/2024
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
`following e-mail address(es):
`USPTOmail @rimonlaw.com
`
`eofficeaction @appcoll.com
`
`PTOL-90A (Rev. 04/07)
`
`

`

`
`
`Office Action Summary
`
`Application No.
`17/840,167
`Examiner
`RYAN T FORTIN
`
`Applicant(s)
`NAKANISHI et al.
`Art Unit
`AIA (FITF) Status
`4156
`Yes
`
`-- The MAILING DATEof this communication appears on the cover sheet with the correspondence address --
`Period for Reply
`
`A SHORTENED STATUTORYPERIOD FOR REPLYIS SET TO EXPIRE 3 MONTHS FROM THE MAILING
`DATE OF THIS COMMUNICATION.
`Extensionsof time may be available underthe provisions of 37 CFR 1.136(a). In no event, however, may a reply betimely filed after SIX (6) MONTHSfrom the mailing
`date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHSfrom the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, evenif timely filed, may reduce any earned patent term
`adjustment. See 37 CFR 1.704(b).
`
`Status
`
`1) Responsive to communication(s) filed on 14 June 2022.
`C} A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/werefiled on
`
`2a)() This action is FINAL. 2b)¥)This action is non-final.
`3) An election was madeby the applicant in responseto a restriction requirement set forth during the interview
`on
`; the restriction requirement and election have been incorporated into this action.
`4)(2) Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Exparte Quayle, 1935 C.D. 11, 453 O.G. 213.
`
`Disposition of Claims*
`1-13 is/are pending in the application.
`)
`Claim(s)
`5a) Of the above claim(s) _ is/are withdrawn from consideration.
`C} Claim(s)__ is/are allowed.
`Claim(s) 1-13 is/are rejected.
`(] Claim(s)__ is/are objectedto.
`C] Claim(s
`are subjectto restriction and/or election requirement
`)
`* If any claims have been determined allowable, you maybeeligible to benefit from the Patent Prosecution Highway program at a
`participating intellectual property office for the corresponding application. For more information, please see
`http://www.uspto.gov/patents/init_events/pph/index.jsp or send an inquiry to PPHfeedback@uspto.gov.
`
`) ) ) )
`
`Application Papers
`10)¥] The specification is objected to by the Examiner.
`11) The drawing(s) filed on 14 June 2022 is/are: a)(¥) accepted or b)( objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121(d).
`
`Priority under 35 U.S.C. § 119
`12)(¥) Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d)or (f).
`Certified copies:
`_—_c)L) None ofthe:
`b)L) Some**
`a)Y) All
`1.) Certified copies of the priority documents have been received.
`2.1.) Certified copies of the priority documents have been received in Application No. |
`3.2.) Copies of the certified copies of the priority documents have been receivedin this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`*“ See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`1)
`
`Notice of References Cited (PTO-892)
`
`(LJ Interview Summary (PTO-413)
`Paper No(s)/Mail Date
`(Qj Other:
`4)
`Information Disclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`2)
`Paper No(s)/Mail Date14June2022,
`U.S. Patent and Trademark Office
`
`3)
`
`PTOL-326 (Rev. 11-13)
`
`Office Action Summary
`
`Part of Paper No./Mail Date 20240730
`
`

`

`Application/Control Number: 17/840,167
`Art Unit: 4156
`
`Page 2
`
`DETAILED ACTION
`
`Notice of Pre-AlA or AIA Status
`
`1.
`
`The present application, filed on or after March 16, 2013,
`
`is being examined
`
`underthefirst inventor to file provisions of the AIA.
`
`Specification
`
`2.
`
`The disclosure is objected to because of the following minor typographical
`
`informalities, with suggestions for correction provided:
`
`-
`
`-
`
`-
`
`Page 16, lines 15 — 16: “the dark current [[to]] generated may be increased.”
`
`Page 16, line 30: “without beingreflected”
`
`Page 20, lines 24 — 25: “a semiconductor device according to ascerdingte-the
`
`embodiment”
`
`Appropriate correction is required. Applicant's cooperation is further requested in
`
`correcting any errors of which applicant may become awarein the specification.
`
`Claim Rejections - 35 USC § 102
`
`3.
`
`This application currently namesjoint inventors.
`
`In considering patentability of the
`
`claims the examiner presumes that the subject matter of the various claims was
`
`commonly ownedasof the effective filing date of the claimed invention(s) absent any
`
`evidenceto the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to
`
`point out the inventor and effective filing dates of each claim that was not commonly
`
`ownedasof the effectivefiling date of the later invention in order for the examiner to
`
`consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2)
`
`prior art against the later invention.
`
`

`

`Application/Control Number: 17/840,167
`Art Unit: 4156
`
`Page 3
`
`4.
`
`The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that
`
`form the basis for the rejections under this section madein this Office action:
`
`A person shall be entitled to a patent unless —
`
`(a)(1) the claimed invention was patented, described in a printed publication, orin public use, on sale,
`or otherwise available to the public beforethe effective filing date of the claimed invention.
`
`5.
`
`Claims 1 — 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by
`
`Okabe, T., ef a/., US 2012/0199893 A1, hereinafter “Okabe”. FIG. 3A of Okabeis
`
`reproduced below for reference.
`
`6.
`
`Regarding claim 1, Okabe discloses a semiconductor device (FIG. 10, para.
`
`[0077], solid-state image pickup apparatus 1001) comprising:
`
`-
`
`asilicon semiconductor substrate (FIG. 3A, para. [0047], semiconductor
`
`substrate 301) including a first region (FIGS. 3A and 10, para [0048], pixel
`
`converter (FIG. 7, para. [0044],
`
`section 1011)
`
`in whicha
`
`photoelectric
`
`pixel cell 100a, pixel cell 100b) is disposed, and a second region different from
`
`the first region (FIGS. 3A and 10, para. [0050], peripheral circuit section 1016);
`
`-
`
`atransistor which is disposed in the second region (FIG. 3A, para. [0050],
`
`transistor 304 in the peripheral circuit section 1016) and includes a sidewall
`
`made of an insulating material (FIG. 3A., para. [0049], transistor 304 has side
`
`spacers 312 on the side walls of the gate electrode 310; the side spacers 312 are
`
`made of a multilayer film including a silicon oxide layer, a silicon nitride layer 305,
`
`

`

`Application/Control Number: 17/840,167
`Art Unit: 4156
`
`Page 4
`
`and a silicon oxide layer 306; the “insulating material’ is taken to be silicon nitride
`
`because the side spacers 312 are “madeof”silicon nitride in that they include a
`
`silicon nitride layer);
`
`an anti-reflective film which is disposed above a main surface ofthe silicon
`
`semiconductor substrate in the first region and is madeof the insulating material
`
`(FIG. 3A, paras. [0048] and [0050], the “anti-reflective film” is taken to be the
`
`disclosed multi-layered laminate imparting anti-reflective properties, and
`
`includes: insulating film made of silicon oxide (not shown), an insulating film 305
`
`made ofsilicon nitride, an insulating film 306 madeofsilicon oxide, and insulating
`
`film 307 madeofsilicon nitride, formed in that order above the main surface 302
`
`in the pixel section 1011; see para. [0063] regarding the anti-reflective function of
`
`the laminate cited above; because the multi-layered laminate includes twosilicon
`
`nitride layers (305 / 307),
`
`it is taken to be “made ofthe insulating material’); and
`
`a first liner film which is disposed above the main surface of the silicon
`
`semiconductor substrate in the second region and is made of the insulating
`
`material (FIG. 3A, para. [0050], an insulating film 307 madeofsilicon nitride is
`
`formed over the main surface 302 in the peripheral circuit section 1016;
`
`insulating film 307 also functions as a “liner film” in the sense that it plays a role
`
`in the subsequent formation of contact holes as described in paragraph [0053],
`
`FIG. 3C (referenced as film 318 after patterning));
`
`wherein the anti-reflective film and thefirst liner film are integrally formed (the
`
`term “integrally formed’ is taken to have its meaning as defined by applicant at
`
`page8, lines 9 — 13 of the specification: “In the present embodiment,first liner
`
`

`

`Application/Control Number: 17/840,167
`Art Unit: 4156
`
`Page 5
`
`film 152 and anti-reflective film 151 are integrally formed.
`
`In other words, anti-
`
`reflective film 151 andfirst liner film 152 are formed as a single film (insulating
`
`film 150) above main surface 112 of semiconductor.”; as such, it is clear from the
`
`fabrication step shown in FIG. 3A of Okabethatsilicon nitride film 307 is formed
`
`as a single film across both sections 1011 and 1016, thus meeting applicant’s
`
`definition of “integrally formed” with respect to the anti-reflective film and thefirst
`
`liner film), and
`
`a thicknessof the anti-reflective film (the aforementioned multi-layered laminate:
`
`oxide/nitride/oxide/nitride)
`
`is larger than or equal to a sum of a thickness of the
`
`sidewall (side spacers 312: oxide/nitride/oxide) and a thicknessofthefirst liner
`
`film (insulating film 307: nitride) (according to applicant’s definitions of the
`
`foregoing thicknesses at page 9, lines 7 — 26 and page 12, lines 6 — 9, in Okabe
`
`the thickness of the anti-reflective film multi-layered laminate and the sum of
`
`sidewall andfirst liner film thicknesses would be the same,that is “equal to” one
`
`another, as they were formed of exactly the same four layers:
`
`oxide/nitride/oxide/nitride).
`
`7.
`
`Regarding claim 2, Okabe discloses the semiconductor device according to claim
`
`1 as above, and further discloses wherein the insulating material is a nitride (paras.
`
`[0048] and [0050], insulating films 305 and 307 madeofsilicon nitride).
`
`8.
`
`Regarding claim 3, Okabe discloses the semiconductor device according to claim
`
`1 as above,and further discloses wherein the photoelectric converter photoelectrically
`
`converts light having a wavelength of 650 nm or more (see para. [0047] regarding
`
`Okabe’s “photoelectric conversion portions’;
`
`the semiconductor substrate 301 including
`
`

`

`Application/Control Number: 17/840,167
`Art Unit: 4156
`
`Page 6
`
`n-type region 314 and p-type region 316, forming the photoelectric conversion portion,
`
`is madeof silicon, and a knownpropertyofsilicon-based photoelectric converters is that
`
`they are useful in the visible and near-infrared wavelengths, meeting the claim limitation
`
`of “a wavelength of 650 nm or more” (as evidence: e.g., Haapalinna, A., et a/., “Spectral
`
`reflectance of silicon photodiodes’, Applied Optics vol. 37 (4), pp. 729 — 32 (1998); and
`
`applicant’s acknowledgement of same at specification page 6, lines 18 — 25)).
`
`9.
`
`Regarding claim 4, Okabe discloses the semiconductor device according to claim
`
`1 as above, wherein the thickness of the anti-reflective film is 70 nm or more (para.
`
`[0063]: “the [oxide] insulating film (not shown) has a thickness of about 5 to 20 nm,
`
`[nitride]] insulating film 305 has a thickness of about 30 to 100 nm, [oxide] insulating film
`
`306 has a thickness of about 50 to 150 nm, and[nitride] insulating film 317 [portions of
`
`layer 307] has a thickness of about 30 to 100 nm”; the thickness range of the anti-
`
`reflective film multi-layered laminate as thus disclosed would be from 115 nm to 370
`
`nm, meeting “70 nm or more’).
`
`10.
`
`Regarding claim 5, Okabe discloses the semiconductor device according to claim
`
`1 as above, further comprising: a colorfilter which blockslight having a wavelength of
`
`less than 650 nm (FIG. 5B, paras. [0061] and [0114], colorfilter layer 339 including
`
`colorfilters corresponding to a plurality of colors; para. [0065], red colorfilter meets
`
`“blocks light having a wavelength of less than 650 nm”).
`
`11.
`
`Regarding claim 6, Okabe discloses the semiconductor device according to claim
`
`1 as above, wherein
`
`-
`
`the silicon semiconductor substrate further includes a third region in which the
`
`transistor and the photoelectric converter are not disposed (the “third region” is
`
`

`

`Application/Control Number: 17/840,167
`Art Unit: 4156
`
`Page 7
`
`taken to be anywherein “peripheral circuit section 1016” not having a transistor,
`
`e.g., “[e]lement isolation regions having a shallow trenchisolation (STI) structure”
`
`(para. [0101]), as shownin FIG. 3A, right edge of section 1016, STI 217),
`
`a secondliner film made of the insulating material is disposed above the main
`
`surface of the silicon semiconductor substrate in the third region (silicon nitride
`
`insulating film 307 is formed everywherein section 1016, including over STI 217
`
`(para. [0050])),
`
`the anti-reflective film, the first liner film, and the secondliner film are integrally
`
`formed (insulating film 307, same interpretation of “integrally formed” as
`
`discussed above, and as further defined at page 8,line 35 — page9, line 4), and
`
`the first liner film and the secondliner film are identical in thickness (insulating
`
`film 307 of the first and secondliner films being deposited as a single film in the
`
`same step across section 1016 meets “identical in thickness” (paras. [0050] and
`
`[0063])).
`
`Regarding claim 7, Okabe discloses:
`
`a method of manufacturing (para. [0046]) a semiconductor device (FIG. 10, para.
`
`[0077], solid-state image pickup apparatus 1001), the method comprising:
`
`(i) forming a photoelectric converter (FIG. 7, para. [0044], pixel cell 100a, pixel
`
`cell 100b) in a first region (FIGS. 3A and 10, para [0048], pixel section 1011) ina
`
`silicon semiconductor substrate (FIG. 3A, para. [0047], semiconductor substrate
`
`301);
`
`(ii) forming a gate electrode (FIG. 3A, para. [0047], gate electrode 310) ina
`
`second region different from the first region in the silicon semiconductor
`
`

`

`Application/Control Number: 17/840,167
`Art Unit: 4156
`
`Page 8
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`substrate (FIGS. 3A and 10, para. [0050], peripheral circuit section 1016), the
`
`gate electrode being included in a transistor (FIG. 3A, para. [0050], transistor 304
`
`in the peripheral circuit section 1016);
`
`-
`
`(iii) forming an insulating film by depositing an insulating material above a main
`
`surface of the silicon semiconductor substrate (para. [0048], “insulating film”is
`
`multi-layered: “FIG. 3A shows the step of forming insulating films over the
`
`elements. An insulating film madeof silicon oxide (not shown), an insulating film
`
`305 madeofsilicon nitride, and an insulating film 306 made of silicon oxide are
`
`formed in that order from the main surface 302 in the pixel section 1011.”;
`
`“insulating material’ is taken to be silicon nitride because the insulating film
`
`includes a silicon nitride layer);
`
`-
`
`(iv) forming a sidewall madeof the insulating material in sides of the gate
`
`electrode by etching the insulating film (FIG. 3A, para. [0049], side spacers 312
`
`are madeof the multi-layer film noted above,including the silicon oxide layer, the
`
`silicon nitride layer 305, and thesilicon oxide layer 306; the multi-layer film as
`
`shown is removed from everywhereelse in peripheral circuit section, so it has
`
`been etched); and
`
`
`
`- (v) forming an anti-reflective film andafirst liner film by further depositing the
`
`insulating material above the main surfaceof the silicon semiconductor substrate
`
`(further deposition of the insulating material is taken as thesilicon nitride film 307
`
`being deposited over the main surface 302 in both the pixel section 1011 and the
`
`peripheral circuit section 1016), the anti-reflective film being disposed above the
`
`main surface of the silicon semiconductor substrate in the first region and made
`
`

`

`Application/Control Number: 17/840,167
`Art Unit: 4156
`
`Page 9
`
`of the insulating material (FIG. 3A, paras. [0048] and [0050], the “anti-reflective
`
`film” is taken to be the disclosed multi-layered laminate imparting anti-reflective
`
`properties, and includes:
`
`insulating film madeof silicon oxide (not shown), an
`
`insulating film 305 made ofsilicon nitride, an insulating film 306 madeof silicon
`
`oxide, and insulating film 307 madeofsilicon nitride, formed in that order above
`
`the main surface 302 in the pixel section 1011; see para. [0063] regarding the
`
`anti-reflective function of the laminate cited above; because the multi-layered
`
`laminate includes twosilicon nitride layers (305 / 307),
`
`it is taken to be “made of
`
`the insulating material’), the first liner film being disposed above the main surface
`
`of the silicon semiconductor substrate in the second region and madeof the
`
`insulating material (FIG. 3A, para. [0050], an insulating film 307 madeofsilicon
`
`nitride is formed over the main surface 302 in the peripheral circuit section 1016;
`
`insulating film 307 also functions as a “liner film” in the sense that it plays a role
`
`in the subsequent formation of contact holes as described in paragraph [0053],
`
`FIG. 3C (referenced asfilm 318 after patterning)).
`
`13.
`
`Regarding claim 8 as above, Okabe discloses the method of manufacturing a
`
`semiconductor device according to claim 7, wherein a thickness of the anti-reflective
`
`film (the aforementioned multi-layered laminate: oxide/nitride/oxide/nitride)
`
`is larger than
`
`or equal to a sum of a thickness of the sidewall (side spacers 312: oxide/nitride/oxide)
`
`and a thicknessofthe first liner film (insulating film 307: nitride) (according to applicant’s
`
`definitions of the foregoing thicknesses at page Q, lines 7 — 26 and page 12,lines 6 —9,
`
`in Okabethe thicknessof the anti-reflective film multi-layered laminate and the sum of
`
`sidewall andfirst liner film thicknesses would be the same, that is “equal to” one
`
`

`

`Application/Control Number: 17/840,167
`Art Unit: 4156
`
`Page 10
`
`another, as they were formed of exactly the same fourlayers:
`
`oxide/nitride/oxide/nitride).
`
`14.|Regarding claim 9, Okabe discloses the method of manufacturing a
`
`semiconductor device according to claim 7 as above, wherein the insulating materialis
`
`a nitride (para. [0048] and [0050], insulating films 305 and 307 madeof silicon nitride).
`
`15.|Regarding claim 10, Okabe discloses the method of manufacturing a
`
`semiconductor device according to claim 7 as above, wherein the photoelectric
`
`converter photoelectrically converts light having a wavelength of 650 nm or more (see
`
`para. [0047] regarding Okabe’s “photoelectric conversion portions’; the semiconductor
`
`substrate 301 including n-type region 314 and p-type region 316, forming the
`
`photoelectric conversion portion,
`
`is made ofsilicon, and a knownproperty ofsilicon-
`
`based photoelectric converters is that they are useful in the visible and near-infrared
`
`wavelengths, meeting the claim limitation of “a wavelength of 650 nm or more” (as
`
`evidence: e.g., Haapalinna, A., et a/., “Spectral reflectance of silicon photodiodes’,
`
`Applied Optics vol. 37 (4), pp. 729 — 32 (1998); and applicant’s acknowledgement of
`
`same at specification page 6,lines 18 — 25)).
`
`16.|Regarding claim 11, Okabe discloses the method of manufacturing a
`
`semiconductor device according to claim 7 as above, wherein a thickness of the anti-
`
`reflective film is 70 nm or more (para. [0063]: “the [oxide] insulating film (not shown) has
`
`a thickness of about 5 to 20 nm, [nitride]] insulating film 305 has a thickness of about 30
`
`to 100 nm, [oxide] insulating film 306 has a thickness of about 50 to 150 nm, and
`
`[nitride] insulating film 317 [portions of layer 307] has a thickness of about 30 to 100
`
`

`

`Application/Control Number: 17/840,167
`Art Unit: 4156
`
`Page 11
`
`nm’; the thickness range of the anti-reflective film multi-layered laminate as thus
`
`disclosed would be from 115 nm to 370 nm, meeting “70 nm or more’).
`
`17.|Regarding claim 12, Okabe discloses the method of manufacturing a
`
`semiconductor device according to claim 7 as above, further comprising: disposing a
`
`colorfilter which blockslight having a wavelength of less than 650 nm (FIG. 5B, paras.
`
`[0061] and [0114], colorfilter layer 339 including colorfilters corresponding to a plurality
`
`of colors; para. [0065], red colorfilter meets “blocks light having a wavelength of less
`
`than 650 nm”).
`
`18.|Regarding claim 13, Okabe discloses the method of manufacturing a
`
`semiconductor device according to claim 7, wherein
`
`-
`
`(v) further includes forming a secondliner film made of the insulating material
`
`above the main surface of the silicon semiconductor substrate (silicon nitride
`
`insulating film 307 is formed everywherein section 1016, including over STI 217
`
`(para. [0050])) in a third region in which the transistor and the photoelectric
`
`converter are not disposed (the “third region” is taken to be anywhere in
`
`“peripheral circuit section 1016” not having a transistor, e.g., “[e]lement isolation
`
`regions having a shallow trench isolation (STI) structure” (para. [0101]), as
`
`shown in FIG. 3A, right edge of section 1016, STI 217),
`
`-
`
`the anti-reflective film, the first liner film, and the secondliner film are integrally
`
`formed (the term “integrally formed’ is taken to have its meaning as defined by
`
`applicant at page 8, lines 9 — 13 of the specification: “In the present embodiment,
`
`first liner film 152 [and secondliner film 153] and anti-reflective film 151 are
`
`integrally formed.
`
`In other words, anti-reflective film 151 andfirst liner film 152
`
`

`

`Application/Control Number: 17/840,167
`Art Unit: 4156
`
`Page 12
`
`[and secondliner film 153] are formed as a single film (insulating film 150) above
`
`main surface 112 of semiconductor.” (and as further defined at page 8,line 35 —
`
`page Y, line 4); as such, it is clear from the fabrication step shown in FIG. 3A of
`
`Okabethatsilicon nitride film 307 is formed as a single film across both sections
`
`1011 and 1016, thus meeting applicant’s definition of “integrally formed’ with
`
`respectto the anti-reflectivefilm and thefirst liner film), and
`
`-
`
`thefirst liner film and the secondlinerfilm are identical in thickness (insulating
`
`film 307 of the first and secondliner films being deposited as a single film in the
`
`same step across section 1016 meets “identical in thickness’ (paras. [0050] and
`
`[0063))).
`
`Conclusion
`
`19.
`
`The following prior art made of record and not relied upon is considered pertinent
`
`to applicant’s disclosure:
`
`- US 2019/0096946 A1 to Hirota ef al., see FIGS. 4A — 6C and associated text
`
`disclosing a device/method in a closely related art (/e., “imaging apparatus
`
`includes a substrate including a photoelectric conversion portion; andasilicon
`
`nitride layer arranged to coverat least a portion of the photoelectric conversion
`
`portion” (abstract)); and
`
`- US 2016/0126284 Aj
`
`to Kato et al, see FIG. 4 and associated text disclosing a
`
`device/method in a closely related art (/.e., “solid-state imaging device is provided
`
`with a semiconductor layer, a gate of a pixel transistor, a gate of a peripheral
`
`circuit transistor, a silicon nitride film and a sidewall” (abstract)).
`
`

`

`Application/Control Number: 17/840,167
`Art Unit: 4156
`
`Page 13
`
`20.=Anyinquiry concerning this communication or earlier communications from the
`
`examiner should be directed to Ryan Fortin whose telephone numberis 703-756-5649.
`
`The examiner can normally be reached on Monday — Thursday from 8:30 AM to 5:30
`
`PM. The examiner can also be reached onalternate Fridays.
`
`21.
`
`‘If attempts to reach the examiner by telephone are unsuccessful, the examiner's
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`supervisor, Britt Hanley, can be reached at telephone number 571-270-3042. The fax
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`phone numberfor the organization wherethis application or proceeding is assigned is
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`571-273-8300.
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`22.
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`Information regarding the status of an application may be obtained from the
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`Patent Center system. Status information for published applications may be obtained
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`from Patent Center. Status information for unpublished applications is available through
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`Patent Center to authorized users only. Should you have questions about access to the
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`Patent Center system, contact the Electronic Business Center (EBC) at 866-217-9197
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`(toll-free).
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`23.
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`Examinerinterviews are available via telephone and video conferencing using a
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`USPTO supplied web-based collaboration tool. To schedule an interview, applicant is
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`encouraged to use the USPTO Automated Interview Request (AIR) Form at
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`https://www.uspto.gov/patents/uspto-automated-interview-request-air-form.
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`/R.T.F./
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`Examiner, Art Unit 4156
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`/CALEEN O SULLIVAN/
`Primary Examiner, Art Unit 2899
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